Microelectronics Devices & Circuits

EE105 - Fall 2006 Microelectronic Devices and Circuits Prof. Jan M. Rabaey (jan@eecs)

Lecture 3: Semiconductor Basics (cntd) Semiconductor Manufacturing

Overview ƒ Last lecture – Carrier velocity and mobility – Drift currents – IC resistors

ƒ This lecture – Diffusion currents – Overview of IC fabrication process – Review of electrostatics

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Administrativia ƒ Make-up Lecture tomorrow Fr at 3:30pm (streamed) ƒ Another Make-up Lecture Monday at 4pm (streamed) NO LECTURE ON TUESDAY ƒ Labs start next TU – MAKE SURE TO ATTEND

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Some other reading material ƒ Sedra and Smith, Microelectronic Circuits, Fifth Edition, Oxford University Press ƒ Donald Neamen, Microelectronics – Circuit Analysis and Design, Third Edition, McGraw Hill ƒ R. F. Pierret, Semiconductor Device Fundamentals, Addison Wesley, 1996. (130 Text Book) ƒ R. S. Muller and T. I. Kamins with Mansun Chan, Device Electronics for Integrated Circuits, 3rd Edition; Wiley and Sons, Publisher.

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Resistivity Bulk silicon: uniform doping concentration, away from surfaces n-type example: in equilibrium, no = Nd When we apply an electric field,

n = Nd

J n = qμ n nE = qμ n N d E Conductivity σ n = qμ n N d ,eff = qμ n ( N d − N a ) Resistivity

ρn =

1

σn

=

1 qμ n N d ,eff

Ω − cm 5

Ohm’s Law

I = JA = J ⋅ (tW ) = σ t W E = σ t W R=

1 L ρ L = σtW t W

with

V ⎛ σ tW ⎞ V =⎜ ⎟ ⋅V = L ⎝ L ⎠ R

ρn =

1

σn

=

1 qμ n N d ,eff 6

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Sheet Resistance (Rs) ƒ IC resistors have a specified thickness – not under the control of the circuit designer ƒ Eliminate t by absorbing it into a new parameter: the sheet resistance (Rs)

R=

ρL ⎛ ρ ⎞⎛ L ⎞ ⎛L⎞ = ⎜ ⎟⎜ ⎟ = Rsq ⎜ ⎟

Wt

⎝ t ⎠⎝ W ⎠

⎝W ⎠ “Number of Squares”

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Using Sheet Resistance (Rs) ƒ Ion-implanted (or “diffused”) IC resistor

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Idealizations ƒ Why does current density Jn “turn”? ƒ What is the thickness of the resistor? ƒ What is the effect of the contact regions?

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Diffusion ƒ Diffusion occurs when there exists a concentration gradient ƒ In the figure below, imagine that we fill the left chamber with a gas at temperate T ƒ If we suddenly remove the divider, what happens? ƒ The gas will fill the entire volume of the new chamber. How does this occur?

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Diffusion (cont) ƒ The net motion of gas molecules to the right chamber was due to the concentration gradient ƒ If each particle moves on average left or right then eventually half will be in the right chamber ƒ If the molecules were charged (or electrons), then there would be a net current flow ƒ The diffusion current flows from high concentration to low concentration:

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Diffusion Equations ƒ Assume that the mean free path is λ ƒ Find flux of carriers crossing x=0 plane

n (0 ) n ( −λ )

F= 1 n(λ )vth 2

1 n(−λ )vth 2 −λ

F=

n (λ )

0

λ

1 vth (n(−λ ) − n(λ ) ) 2

dn ⎤ ⎡ dn ⎤ ⎞ 1 ⎛⎡ vth ⎜⎜ ⎢n(0) − λ ⎥ − ⎢n(0) + λ ⎥ ⎟⎟ dx ⎦ ⎣ dx ⎦ ⎠ 2 ⎝⎣ dn F = −vth λ dx J = − qF = qvth λ

dn dx 12

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Einstein Relation ƒ The thermal velocity is given by kT 1 2

mn*vth2 = 12 kT Mean Free Time

λ = vthτ c vth λ = vth2 τ c = kT

J = qvth λ

τc * n

m

=

kT qτ c q mn*

Mobility

⎛ kT ⎞ dn dn dn = q⎜⎜ μ n ⎟⎟ = qDn dx dx ⎝ q ⎠ dx Diffusion Coefficient

Dn

μn

⎛ kT = ⎜⎜ ⎝ q

⎞ ⎟⎟ = Vth ⎠

Einstein Relation

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Total Current ƒ When both drift and diffusion are present, the total current is given by the sum: J = J drift + J diff = qμ n nE + qDn

dn dx

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IC Fabrication: Photo-Lithographic Process optical mask oxidation

photoresist removal (ashing)

photoresist coating stepper exposure

Typical operations in a single photolithographic cycle (from [Fullman]). photoresist development acid etch process step

spin, rinse, dry

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IC Fabrication: Si Substrate ƒ Pure Si crystal is starting material (wafer) ƒ The Si wafer is extremely pure (~1 part in a billion impurities) ƒ Why so pure? – Si density is about 5 1022 atoms/cm3 – Desire intentional doping from 1014 – 1018 – Want unintentional dopants to be about 1-2 orders of magnitude less dense ~ 1012

ƒ Si wafers are polished to about 700 μm thick (mirror finish) ƒ The Si forms the substrate for the IC

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IC Fabrication: Oxide ƒ Si has a native oxide: SiO2 ƒ SiO2 (glass) is extremely stable and very convenient for fabrication ƒ It’s an insulator ƒ SiO2 windows are etched using photolithography ƒ These openings allow ion implantation into selected regions ƒ SiO2 can block ion implantation in other areas

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IC Fabrication: Patterning of SiO2 Chemical or plasma etch Si-substrate

Hardened resist SiO 2

(a) Silicon base material

Si-substrate

Photoresist SiO 2 Si-substrate

(d) After development and etching of resist, chemical or plasma etch of SiO 2 Hardened resist SiO 2

(b) After oxidation and deposition of negative photoresist Si-substrate UV-light Patterned optical mask

(e) After etching

Exposed resist Si-substrate (c) Stepper exposure

SiO 2 Si-substrate (f) Final result after removal of resist

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“Diffusion” Resistor N-type Diffusion Region

Oxide

P-type Si Substrate

ƒ Using ion implantation/diffusion, the thickness and dopant concentration of resistor is set by process ƒ ƒ ƒ ƒ

E.g. 100Ω/□ (unsilicided), 10Ω/□ (silicided) Shape of the resistor is set by design (layout) Metal contacts are connected to ends of the resistor Resistor is capacitively isolation from substrate – Reverse-biased PN Junction!

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Using Sheet Resistance (Rs) ƒ Ion-implanted (or “diffused”) IC resistor

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Poly Film Resistor Polysilicon Film (N+ or P+ type)

Oxide

P-type Si Substrate

ƒ To lower the capacitive parasitics, we should build the resistor further away from substrate ƒ We can deposit a thin film of “poly” Si (heavily doped) material on top of the oxide ƒ E.g. 10-100Ω/□ (unsilicided), 1Ω/□ (silicided) ƒ Bad absolute tolerance, very good relative tolerance 21

CMOS Process at a Glance Define active areas Etch and fill trenches

Implant well regions

Deposit and pattern polysilicon layer

Implant source and drain regions and substrate contacts

Create contact and via windows Deposit and pattern metal layers

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Electrostatics: a Tool for Device Modeling

Gauss’s Law

∇•( εE ) = ρ

Potential Def.

E = – ∇φ

Poisson’s Eqn.

∇• ( ε ( – ∇φ ) ) = – ε ∇ 2φ = ρ

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One-Dimensional Electrostatics dE ρ = dx ε

Gauss’s Law

∇⋅E =

Potential Def.

E=−

Poisson’s Eqn.

ρ ( x) d 2φ ( x) =− 2 dx ε

dφ dx

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Electrostatics Review (1) ƒ Electric field go from positive charge to negative charge (by convention) +++++++++++++++++++++ −−−−−−−−−−−−−−−

∇⋅E =

ρ ε

ƒ In words, if the electric field changes magnitude, there has to be charge involved! ƒ Result: In a charge-free region, the electric field must be constant! 25

Electrostatics Review (2) ƒ Gauss’ Law equivalently says that if there is a net electric field leaving a region, there has to be positive charge in that region: +++++++++++++++++++++ −−−−−−−−−−−−−−− Electric Fields are Leaving This Box!

Q

∫ E ⋅ dS = ε

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Electrostatics in 1D ƒ Everything simplifies in 1-D ∇⋅E =

dE ρ = dx ε

dE = x

E ( x) = E ( x0 ) + ∫

x0

ρ dx ε

ρ ( x' ) dx' ε

ƒ Consider a uniform charge distribution Zero field boundary condition

ρ (x)

E ( x)

ρ0 x1 ε

ρ0 x1

x x ρ ρ ( x' ) E ( x) = ∫ dx' = 0 x 0

ε

x1

ε

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Electrostatic Potential ƒ The electric field (force) is related to the potential (energy): E=−

dφ dx

ƒ Negative sign says that field lines go from high potential points to lower potential points (negative slope) ƒ Note: An electron should “float” to a high potential dφ φ1 point: dφ F = −e Fe = qE = −e

e

dx

e

dx

φ2

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More Potential ƒ Integrating this basic relation, we have that the potential φ (x) is the integral of the field: r

φ ( x) − φ ( x0 ) = − ∫ E ⋅ dl

r dl

C

ƒ In 1D, this is a simple integral:

E

φ ( x0 )

x

φ ( x) − φ ( x0 ) = − ∫ E ( x' )dx' x0

ƒ Going the other way, we have Poisson’s equation in 1D: d 2φ ( x) ρ ( x) =− 2 dx ε 29

Boundary Conditions ƒ Potential must be a continuous function. If not, the fields (forces) would be infinite ƒ Electric fields need not be continuous. We have already seen that the electric fields diverge on charges. In fact, across an interface we have: Δx

∫ ε E ⋅ dS = −ε E S + ε 1

E1 (ε 1 )

1

2

E2 S = Qinside

Qinside ⎯Δx ⎯→ ⎯0 → 0 − ε 1 E1S + ε 2 E2 S = 0

E2 (ε 2 )

S

E1 ε 2 = E2 ε 1 30

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IC MIM Capacitor Top Plate

Bottom Plate

Bottom Plate

Contacts Thin Oxide

Q = CV ƒ By forming a thin oxide and metal (or polysilicon) plates, a capacitor is formed ƒ Contacts are made to top and bottom plate ƒ Parasitic capacitance exists between bottom plate and substrate 31

Review of Capacitors Q

+ −

+++++++++++++++++++++

∫ E ⋅ dS = ε

Vs −−−−−−−−−−−−−−−

∫ E ⋅ dl = E t

0 ox

= Vs

∫ E ⋅ dS = E0 A =

Q

ε

Vs tox Vs Q A= tox ε E0 =

Q

∫ E ⋅ dS = − ε

Q = CVs C=

Aε tox

ƒ For an ideal metal, all charge must be at surface ƒ Gauss’ law: Surface integral of electric field over closed surface equals charge inside volume 32

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Capacitor Q-V Relation +++++++++++++++++++++

Q

y −−−−−−−−−−−−−−−

Q( y )

Vs

y Q = CVs

ƒ Total charge is linearly related to voltage ƒ Charge density is a delta function at surface (for perfect metals) 33

A Non-Linear Capacitor +++++++++++++++++++++

y

Q

−−−−−−−−−−−−−−−

Vs

Q( y ) y

Q = f (Vs )

ƒ We’ll soon meet capacitors that have a non-linear Q-V relationship ƒ If plates are not ideal metal, the charge density can penetrate into surface 34

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What’s the Capacitance? ƒ For a non-linear capacitor, we have Q = f (Vs ) ≠ CVs

ƒ We can’t identify a capacitance ƒ Imagine we apply a small signal on top of a bias voltage: Q = f (Vs + vs ) ≈ f (Vs ) +

df (V ) vs dV V =Vs

Constant charge

ƒ The incremental charge is therefore: Q = Q0 + q ≈ f (Vs ) +

df (V ) vs dV V =Vs

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Small Signal Capacitance ƒ Break the equation for total charge into two terms: Incremental Charge

Q = Q0 + q ≈ f (Vs ) +

df (V ) vs dV V =Vs

Constant Charge

q=

df (V ) vs = C vs dV V =Vs C≡

df (V ) dV V =Vs

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Example of Non-Linear Capacitor ƒ Next lecture we’ll see that for a PN junction, the charge is a function of the reverse bias: Q j (V ) = −qN a x p 1 − Charge At N Side of Junction

V

Voltage Across NP Junction

φb

Constants

ƒ Small signal capacitance: C j (V ) =

dQ j dV

=

qN a x p 2φb

1 1−

V

φb

=

C j0 1−

V

φb

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