Memory Management (interrupt Priority Approach) Ppt
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- Pages: 39
Amit Kumar Karna (4403) Devender Budhwar (4411) Dinesh Kumar (4412) NIT Warangal
ACKNOWLEDGEMENT
Special thanks to, Mr. P. Murlidhar Faculty, Department of E.C.E., NIT Warangal
NIT Warangal
AGENDA
Introduction Approach VHDL implementation RTL Viewer Simulation results Conclusion
INTRODUCTION
An MMU is a controller that allows a common resource memory to be shared by two or more processors depending on various input control signals.
INTRODUCTION…
Problem statement: Three processors are required to share a synchronous RAM of size 1024*16.The address bus is 10 bits wide and the data bus is 16 bits wide. There is a r/w’ signal which allows the processors to read data from the memory or write data into the memory. The controller is supposed to control access to the common memory depending on the request signals received by the three processors depending on certain algorithms.
Requirements
Synchronous RAM Address and Data Bus Multiplexer
AGENDA
Introduction Approach VHDL implementation RTL Viewer Simulation results Conclusion
PRIORITY INTERRUPT ALGORITHM
Each processor is assigned a priority and depending on the priority a CPU is given access. When a lower priority processor is active and the controller receives the request signal from a higher priority processor, the latter is given access until its job is finished after which the lower priority processor is given access. Nested interrupts should be allowed.
PRIORITY INTERRUPT state diagram
AGENDA
Introduction Approach VHDL implementation RTL Viewer Simulation results Conclusion
VHDL
VHSIC Hardware Description Language. Common language for designers. High level language. Simulation synthesis and analysis tools are available. Softwares: Quartus-II/Xlinix
DESIGN Unit Names ¾
Entity
¾
Architecture
¾
Name of the design (i.e., top-level entity) with suffix "Pkg“.
Testbench (entity, architecture, package)
¾
Name of the corresponding entity with suffix "Cfg“.
Package
¾
According to the modeling style used (i.e., Behavioral, Procedural, Dataflow, or Structural) or to some specific architecture property.
Configuration
¾
Meaningful name describing the purpose of the circuit.
Name of corresponding entity with suffix "Tb“.
Library (package)
Library name with suffix "Lib".
FPGA
Benefits of using FPGA ¾ Programmed by user at their site using programming hardware. ¾ Can implement tens of thousands of gates on logic on a single IC. ¾ Can be programmed many times. ¾ Short development time. ¾ Low cost. ¾ FPGA kit in lab: EP1C6Q240C8
Hierarchy ‘n’ fpga occupancy COMPONENTS:• Synchronous RAM • Address and Data Bus Multiplexer
Project navigator
AGENDA
Introduction Approach VHDL implementation RTL Viewer Simulation results Conclusion
MMU- Entity
MAIN – RTL VIEW
MAIN – TECHNOLOGY VIEW m u l ti p l e x:m u l t a d d A [0 ] a d d A [1 ] a d d A [2 ] a d d A [3 ] a d d A [4 ] a d d A [5 ] a d d A [6 ] a d d A [7 ] a d d A [8 ] a d d A [9 ] a d d B [0 ] a d d B [1 ] a d d B [2 ] a d d B [3 ] a d d B [4 ] a d d B [5 ] a d d B [6 ] a d d B [7 ] a d d B [8 ] a d d B [9 ] a d d C [0 ] a d d C [1 ] a d d C [2 ] a d d C [3 ] a d d C [4 ] a d d C [5 ] a d d C [6 ] a d d C [7 ] a d d C [8 ] a d d C [9 ] d a ta A [0 ] d a ta A [1 ] d a ta A [2 ] d a ta A [3 ] d a ta A [4 ] d a ta A [5 ] d a ta A [6 ] d a ta A [7 ] d a ta A [8 ] d a ta A [9 ] d a ta A [1 0 ] d a ta A [1 1 ] d a ta A [1 2 ] d a ta A [1 3 ] d a ta A [1 4 ] d a ta A [1 5 ] d a ta B [0 ] d a ta B [1 ] d a ta B [2 ] d a ta B [3 ] d a ta B [4 ] d a ta B [5 ] d a ta B [6 ] d a ta B [7 ] d a ta B [8 ] d a ta B [9 ] d a ta B [1 0 ] d a ta B [1 1 ] d a ta B [1 2 ] d a ta B [1 3 ] d a ta B [1 4 ] d a ta B [1 5 ] d a ta C [0 ] d a ta C [1 ] d a ta C [2 ] d a ta C [3 ] d a ta C [4 ] d a ta C [5 ] d a ta C [6 ] d a ta C [7 ] d a ta C [8 ] d a ta C [9 ] d a ta C [1 0 ] s ta r t rw B rw C
addA[0] addA[1] addA[2] addA[3] addA[4] addA[5] addA[6] addA[7] addA[8] addA[9] addB[0] addB[1] addB[2] addB[3] addB[4] addB[5] addB[6]
addB[8]
data_out_mux[0]~ 688
data_out_mux[1]~ 689
data_out_mux[1]~ 689
addC [1]
data_out_mux[2]~ 690
data_out_mux[2]~ 690
addC [2]
data_out_mux[3]~ 691
data_out_mux[3]~ 691
addC [3]
data_out_mux[4]~ 692
data_out_mux[4]~ 692
addC [4]
data_out_mux[5]~ 693
addC [5]
data_out_mux[6]~ 694
data_out_mux[5]~ 693
q _b[0]
data_out_mux[6]~ 694
q _b[1]
addC [6]
data_out_mux[7]~ 695
addC [7]
data_out_mux[8]~ 696
addC [8]
data_out_mux[9]~ 697
addC [9]
data_out_m ux[10]~ 698
data_out_mux[10]~ 698
q _b[5]
dataA[0]
data_out_m ux[11]~ 699
data_out_mux[11]~ 699
q _b[6]
data_out_mux[7]~ 695
q _b[2]
data_out_mux[8]~ 696
q _b[3]
data_out_mux[9]~ 697
q _b[4]
dataA[1]
data_out_m ux[12]~ 700
data_out_mux[12]~ 700
dataA[2]
data_out_m ux[13]~ 701
data_out_mux[13]~ 701
q _b[7] q _b[8]
dataA[3]
data_out_m ux[14]~ 702
data_out_mux[14]~ 702
q _b[9]
dataA[4]
data_out_m ux[15]~ 703
data_out_mux[15]~ 703
q _b[10]
dataA[5]
M ux0~ 131
M ux0~ 131
q _b[11]
dataA[6]
M ux1~ 132
M ux1~ 132
q _b[12]
dataA[7]
M ux2~ 132
M ux2~ 132
q _b[13]
dataA[8]
M ux3~ 132
M ux3~ 132
q _b[14]
dataA[9]
M ux4~ 132
M ux4~ 132
q _b[15]
dataA[12] dataA[13] dataA[14]
M ux5~ 132
M ux5~ 132
M ux6~ 132
M ux6~ 132
M ux7~ 132 M ux8~ 132 M ux9~ 132
dataA[15]
M ux10~ 139
dataB[0]
M ux11~ 139
dataB[1]
M ux12~ 139
dataB[2]
M ux13~ 139
dataB[3]
M ux14~ 139
dataB[4]
M ux15~ 139
dataB[5]
M ux16~ 139
dataB[6]
M ux17~ 139
dataB[7]
M ux18~ 139
M ux7~ 132 M ux8~ 132 M ux9~ 132 rw
D AT AIN
D AT AIN
dataB[10]
M ux21~ 139
!OE
dataB[11]
M ux22~ 139
dataB[12]
M ux23~ 139 M ux24~ 139 M ux25~ 139
dataB[15]
M ux26~ 180
PAD O U T
d a ta _ w r _ o u t[1 4 ]
O U T PU T
d a ta _ w r _ o u t[1 3 ] D AT AIN
PAD O U T
!OE
dataC [1] dataC [2]
d a ta _ w r _ o u t[1 5 ]
O U T PU T
d a ta _ w r _ o u t[1 4 ]
M ux19~ 139 M ux20~ 139
dataB[14]
PAD O U T
!OE
dataB[9]
dataB[13]
d a ta _ r d _ o u t[0 ] d a ta _ r d _ o u t[1 ] d a ta _ r d _ o u t[2 ] d a ta _ r d _ o u t[3 ] d a ta _ r d _ o u t[4 ] d a ta _ r d _ o u t[5 ] d a ta _ r d _ o u t[6 ] d a ta _ r d _ o u t[7 ] d a ta _ r d _ o u t[8 ] d a ta _ r d _ o u t[9 ] d a ta _ r d _ o u t[1 0 ] d a ta _ r d _ o u t[1 1 ] d a ta _ r d _ o u t[1 2 ] d a ta _ r d _ o u t[1 3 ] d a ta _ r d _ o u t[1 4 ] d a ta _ r d _ o u t[1 5 ]
d a ta _ w r _ o u t[1 5 ]
dataB[8]
dataC [0]
d a ta _ w r _ o u t[1 3 ]
O U T PU T
d a ta _ w r _ o u t[1 2 ]
dataC [3] dataC [4]
D AT AIN
dataC [5]
!OE
dataC [6]
dataC [8] dataC [9] dataC [10] dataC [11]
c u r r _ s ta te .s 2
D AT AA
com b~313 D A T AA D A T AC
R EG O U T
D A T AD LC E LL ( AAF 0)
D AT AC
c u r r _ s ta te .s 1
dataC [13]
C LK
p e n a b le A
C O M BO U T
D AT A B C O M BO U T
R EG O U T
D AT A D
D AT AA
c u r r _ s ta te .s 4
S YN C H _D AT A LC E LL ( C F C 0)
com b~320
D A T AC
D AT A A C O M BO U T
D AT A B
R EG O U T
com b~319 D AT AA D AT AB
R EGO U T
D AT A C
LC E LL ( 0100)
D AT AA D AT AB
! AC LR C LK
D A T AA D A T AB
D A T AD
! A C LR
D AT A D LC ELL (0100)
D AT AC
D AT AD
LC ELL ( 5455)
D A T AC
C O M BO U T
D A T AD LC ELL ( F F A5)
C O M BO U T
D AT AD
D AT AC
D AT AA
D AT AC
C O M BO U T
D AT AC
PAD O U T
!OE
d a ta _ w r _ o u t[7 ]
d a ta _ w r _ o u t[6 ] D AT AIN
rw
PAD O U T
!OE
LC E LL ( F A0A )
d a ta _ w r _ o u t[6 ]
O U T PU T
C O M BO U T
D AT AD
LC ELL (F E00)
d a ta _ w r _ o u t[8 ]
O U T PU T
D AT AIN
O U T PU T
LC E LL ( 0F 0C )
D AT AA C OM BOU T
D AT AD
!OE
D AT AD
com b~315 D AT AB
PAD O U T
d a ta _ w r _ o u t[7 ] D AT AB D AT AC
LC ELL ( 1044)
d a ta _ w r _ o u t[9 ]
d a ta _ w r _ o u t[8 ] D AT AIN
LC ELL ( 5544)
p e n a b le C
D AT AD
PAD O U T
O U T PU T
D AT AA
com b~318
C OM BOU T
d a ta _ w r _ o u t[1 0 ]
O U T PU T
penableC
d a ta _ w r _ o u t[9 ]
D AT AB
D AT AA D AT AB
PAD O U T
!OE
p e n a b le B C OM BOU T
d a ta _ w r _ o u t[1 1 ]
O U T PU T
D AT AIN !OE
D AT AIN
D AT AD
com b~317
PAD O U T
d a ta _ w r _ o u t[1 0 ]
dataC [15] penableA
com b~316
D AT AC
D A T AA
dataC [14]
penableB
LC ELL ( 3322) C OM BOU T
LC ELL (32F F )
D AT AA
LC ELL ( F F F E)
C O M BO U T
D AT AD
D AT AB
D AT AC D AT AD
D AT AB
d a ta _ w r _ o u t[1 2 ]
d a ta _ w r _ o u t[1 1 ] D AT AIN !OE
dataC [12]
! AC LR
! A C LR C LK
PAD O U T
O U T PU T
dataC [7]
C LK
re q C
data_out_mux[0]~ 688
addC [0]
dataA[11]
LC ELL ( 5050)
rw A
c lk
addB[9]
dataA[10]
c u r r _ s ta te .s 3 re s e t c lk re q A re q B
m e m o r y:m e m
addB[7]
d a ta _ w r _ o u t[5 ] D AT AIN
PAD O U T
!OE
d a ta _ w r _ o u t[5 ]
O U T PU T
d a ta _ w r _ o u t[4 ]
d a ta C [1 1 ] d a ta C [1 2 ] d a ta C [1 3 ] d a ta C [1 4 ] d a ta C [1 5 ]
D AT AIN
PAD O U T
!OE
d a ta _ w r _ o u t[4 ]
O U T PU T
d a ta _ w r _ o u t[3 ] D AT AIN
PAD O U T
!OE
d a ta _ w r _ o u t[3 ]
O U T PU T
d a ta _ w r _ o u t[2 ] D AT AIN
PAD O U T
!OE
d a ta _ w r _ o u t[2 ]
O U T PU T
d a ta _ w r _ o u t[1 ] D AT AIN
PAD O U T
!OE
d a ta _ w r _ o u t[1 ]
O U T PU T
d a ta _ w r _ o u t[0 ] D AT AIN
PAD O U T
!OE
d a ta _ w r _ o u t[0 ]
O U T PU T
p r e s e n t~ 1 4 D AT AB D AT AD
C OM BOU T
p r e s e n t[2 ] D AT AIN
PAD O U T
!OE
LC ELL ( 0033)
p r e s e n t[2 ]
O U T PU T
p r e s e n t[1 ] D AT AIN
PAD O U T
!OE
p r e s e n t[1 ]
O U T PU T
p r e s e n t[0 ] D AT AIN
PAD O U T
!OE O U T PU T
p r e s e n t[0 ]
MAIN - FLOW RESULT
Memory-entity
MEMORY – RTL VIEW
MEMORY – Technology view
Memory flow summary
Mux entity
Mux flow diagram
Mux rtl
MuX – tech view
AGENDA
Introduction Approach VHDL implementation RTL Viewer Simulation results Conclusion
SIMULATION STATE DIAGRAM
CONDITIONS GENERATED BY SIMULATION
Memory simulation
Mux simulation
MMU-SIMULATION
AGENDA
Introduction Approach VHDL implementation RTL Viewer Simulation results Conclusion
CONCLUSION
Memory can be simultaneously serviced to multi processes.
Being an Interrupt service procedure, time of processor is managed efficiently.
FPGA/VHDL combination is a very powerful design tool. •
Versatile, Adaptable, Efficient, Economic
The given algorithm can be used to implement process scheduling.
REFERENCES
A VHDL Primer, 3rd edition : J. Bhasker Computer Organization and Architecture: William Stallings
"It's
not
Thanks
that
i
am
genius,
but i stay a little longer with problems"
-
Einstein.
ACKNOWLEDGEMENT
Special thanks to, Mr. P. Murlidhar Faculty, Department of E.C.E., NIT Warangal
NIT Warangal
AGENDA
Introduction Approach VHDL implementation RTL Viewer Simulation results Conclusion
INTRODUCTION
An MMU is a controller that allows a common resource memory to be shared by two or more processors depending on various input control signals.
INTRODUCTION…
Problem statement: Three processors are required to share a synchronous RAM of size 1024*16.The address bus is 10 bits wide and the data bus is 16 bits wide. There is a r/w’ signal which allows the processors to read data from the memory or write data into the memory. The controller is supposed to control access to the common memory depending on the request signals received by the three processors depending on certain algorithms.
Requirements
Synchronous RAM Address and Data Bus Multiplexer
AGENDA
Introduction Approach VHDL implementation RTL Viewer Simulation results Conclusion
PRIORITY INTERRUPT ALGORITHM
Each processor is assigned a priority and depending on the priority a CPU is given access. When a lower priority processor is active and the controller receives the request signal from a higher priority processor, the latter is given access until its job is finished after which the lower priority processor is given access. Nested interrupts should be allowed.
PRIORITY INTERRUPT state diagram
AGENDA
Introduction Approach VHDL implementation RTL Viewer Simulation results Conclusion
VHDL
VHSIC Hardware Description Language. Common language for designers. High level language. Simulation synthesis and analysis tools are available. Softwares: Quartus-II/Xlinix
DESIGN Unit Names ¾
Entity
¾
Architecture
¾
Name of the design (i.e., top-level entity) with suffix "Pkg“.
Testbench (entity, architecture, package)
¾
Name of the corresponding entity with suffix "Cfg“.
Package
¾
According to the modeling style used (i.e., Behavioral, Procedural, Dataflow, or Structural) or to some specific architecture property.
Configuration
¾
Meaningful name describing the purpose of the circuit.
Name of corresponding entity with suffix "Tb“.
Library (package)
Library name with suffix "Lib".
FPGA
Benefits of using FPGA ¾ Programmed by user at their site using programming hardware. ¾ Can implement tens of thousands of gates on logic on a single IC. ¾ Can be programmed many times. ¾ Short development time. ¾ Low cost. ¾ FPGA kit in lab: EP1C6Q240C8
Hierarchy ‘n’ fpga occupancy COMPONENTS:• Synchronous RAM • Address and Data Bus Multiplexer
Project navigator
AGENDA
Introduction Approach VHDL implementation RTL Viewer Simulation results Conclusion
MMU- Entity
MAIN – RTL VIEW
MAIN – TECHNOLOGY VIEW m u l ti p l e x:m u l t a d d A [0 ] a d d A [1 ] a d d A [2 ] a d d A [3 ] a d d A [4 ] a d d A [5 ] a d d A [6 ] a d d A [7 ] a d d A [8 ] a d d A [9 ] a d d B [0 ] a d d B [1 ] a d d B [2 ] a d d B [3 ] a d d B [4 ] a d d B [5 ] a d d B [6 ] a d d B [7 ] a d d B [8 ] a d d B [9 ] a d d C [0 ] a d d C [1 ] a d d C [2 ] a d d C [3 ] a d d C [4 ] a d d C [5 ] a d d C [6 ] a d d C [7 ] a d d C [8 ] a d d C [9 ] d a ta A [0 ] d a ta A [1 ] d a ta A [2 ] d a ta A [3 ] d a ta A [4 ] d a ta A [5 ] d a ta A [6 ] d a ta A [7 ] d a ta A [8 ] d a ta A [9 ] d a ta A [1 0 ] d a ta A [1 1 ] d a ta A [1 2 ] d a ta A [1 3 ] d a ta A [1 4 ] d a ta A [1 5 ] d a ta B [0 ] d a ta B [1 ] d a ta B [2 ] d a ta B [3 ] d a ta B [4 ] d a ta B [5 ] d a ta B [6 ] d a ta B [7 ] d a ta B [8 ] d a ta B [9 ] d a ta B [1 0 ] d a ta B [1 1 ] d a ta B [1 2 ] d a ta B [1 3 ] d a ta B [1 4 ] d a ta B [1 5 ] d a ta C [0 ] d a ta C [1 ] d a ta C [2 ] d a ta C [3 ] d a ta C [4 ] d a ta C [5 ] d a ta C [6 ] d a ta C [7 ] d a ta C [8 ] d a ta C [9 ] d a ta C [1 0 ] s ta r t rw B rw C
addA[0] addA[1] addA[2] addA[3] addA[4] addA[5] addA[6] addA[7] addA[8] addA[9] addB[0] addB[1] addB[2] addB[3] addB[4] addB[5] addB[6]
addB[8]
data_out_mux[0]~ 688
data_out_mux[1]~ 689
data_out_mux[1]~ 689
addC [1]
data_out_mux[2]~ 690
data_out_mux[2]~ 690
addC [2]
data_out_mux[3]~ 691
data_out_mux[3]~ 691
addC [3]
data_out_mux[4]~ 692
data_out_mux[4]~ 692
addC [4]
data_out_mux[5]~ 693
addC [5]
data_out_mux[6]~ 694
data_out_mux[5]~ 693
q _b[0]
data_out_mux[6]~ 694
q _b[1]
addC [6]
data_out_mux[7]~ 695
addC [7]
data_out_mux[8]~ 696
addC [8]
data_out_mux[9]~ 697
addC [9]
data_out_m ux[10]~ 698
data_out_mux[10]~ 698
q _b[5]
dataA[0]
data_out_m ux[11]~ 699
data_out_mux[11]~ 699
q _b[6]
data_out_mux[7]~ 695
q _b[2]
data_out_mux[8]~ 696
q _b[3]
data_out_mux[9]~ 697
q _b[4]
dataA[1]
data_out_m ux[12]~ 700
data_out_mux[12]~ 700
dataA[2]
data_out_m ux[13]~ 701
data_out_mux[13]~ 701
q _b[7] q _b[8]
dataA[3]
data_out_m ux[14]~ 702
data_out_mux[14]~ 702
q _b[9]
dataA[4]
data_out_m ux[15]~ 703
data_out_mux[15]~ 703
q _b[10]
dataA[5]
M ux0~ 131
M ux0~ 131
q _b[11]
dataA[6]
M ux1~ 132
M ux1~ 132
q _b[12]
dataA[7]
M ux2~ 132
M ux2~ 132
q _b[13]
dataA[8]
M ux3~ 132
M ux3~ 132
q _b[14]
dataA[9]
M ux4~ 132
M ux4~ 132
q _b[15]
dataA[12] dataA[13] dataA[14]
M ux5~ 132
M ux5~ 132
M ux6~ 132
M ux6~ 132
M ux7~ 132 M ux8~ 132 M ux9~ 132
dataA[15]
M ux10~ 139
dataB[0]
M ux11~ 139
dataB[1]
M ux12~ 139
dataB[2]
M ux13~ 139
dataB[3]
M ux14~ 139
dataB[4]
M ux15~ 139
dataB[5]
M ux16~ 139
dataB[6]
M ux17~ 139
dataB[7]
M ux18~ 139
M ux7~ 132 M ux8~ 132 M ux9~ 132 rw
D AT AIN
D AT AIN
dataB[10]
M ux21~ 139
!OE
dataB[11]
M ux22~ 139
dataB[12]
M ux23~ 139 M ux24~ 139 M ux25~ 139
dataB[15]
M ux26~ 180
PAD O U T
d a ta _ w r _ o u t[1 4 ]
O U T PU T
d a ta _ w r _ o u t[1 3 ] D AT AIN
PAD O U T
!OE
dataC [1] dataC [2]
d a ta _ w r _ o u t[1 5 ]
O U T PU T
d a ta _ w r _ o u t[1 4 ]
M ux19~ 139 M ux20~ 139
dataB[14]
PAD O U T
!OE
dataB[9]
dataB[13]
d a ta _ r d _ o u t[0 ] d a ta _ r d _ o u t[1 ] d a ta _ r d _ o u t[2 ] d a ta _ r d _ o u t[3 ] d a ta _ r d _ o u t[4 ] d a ta _ r d _ o u t[5 ] d a ta _ r d _ o u t[6 ] d a ta _ r d _ o u t[7 ] d a ta _ r d _ o u t[8 ] d a ta _ r d _ o u t[9 ] d a ta _ r d _ o u t[1 0 ] d a ta _ r d _ o u t[1 1 ] d a ta _ r d _ o u t[1 2 ] d a ta _ r d _ o u t[1 3 ] d a ta _ r d _ o u t[1 4 ] d a ta _ r d _ o u t[1 5 ]
d a ta _ w r _ o u t[1 5 ]
dataB[8]
dataC [0]
d a ta _ w r _ o u t[1 3 ]
O U T PU T
d a ta _ w r _ o u t[1 2 ]
dataC [3] dataC [4]
D AT AIN
dataC [5]
!OE
dataC [6]
dataC [8] dataC [9] dataC [10] dataC [11]
c u r r _ s ta te .s 2
D AT AA
com b~313 D A T AA D A T AC
R EG O U T
D A T AD LC E LL ( AAF 0)
D AT AC
c u r r _ s ta te .s 1
dataC [13]
C LK
p e n a b le A
C O M BO U T
D AT A B C O M BO U T
R EG O U T
D AT A D
D AT AA
c u r r _ s ta te .s 4
S YN C H _D AT A LC E LL ( C F C 0)
com b~320
D A T AC
D AT A A C O M BO U T
D AT A B
R EG O U T
com b~319 D AT AA D AT AB
R EGO U T
D AT A C
LC E LL ( 0100)
D AT AA D AT AB
! AC LR C LK
D A T AA D A T AB
D A T AD
! A C LR
D AT A D LC ELL (0100)
D AT AC
D AT AD
LC ELL ( 5455)
D A T AC
C O M BO U T
D A T AD LC ELL ( F F A5)
C O M BO U T
D AT AD
D AT AC
D AT AA
D AT AC
C O M BO U T
D AT AC
PAD O U T
!OE
d a ta _ w r _ o u t[7 ]
d a ta _ w r _ o u t[6 ] D AT AIN
rw
PAD O U T
!OE
LC E LL ( F A0A )
d a ta _ w r _ o u t[6 ]
O U T PU T
C O M BO U T
D AT AD
LC ELL (F E00)
d a ta _ w r _ o u t[8 ]
O U T PU T
D AT AIN
O U T PU T
LC E LL ( 0F 0C )
D AT AA C OM BOU T
D AT AD
!OE
D AT AD
com b~315 D AT AB
PAD O U T
d a ta _ w r _ o u t[7 ] D AT AB D AT AC
LC ELL ( 1044)
d a ta _ w r _ o u t[9 ]
d a ta _ w r _ o u t[8 ] D AT AIN
LC ELL ( 5544)
p e n a b le C
D AT AD
PAD O U T
O U T PU T
D AT AA
com b~318
C OM BOU T
d a ta _ w r _ o u t[1 0 ]
O U T PU T
penableC
d a ta _ w r _ o u t[9 ]
D AT AB
D AT AA D AT AB
PAD O U T
!OE
p e n a b le B C OM BOU T
d a ta _ w r _ o u t[1 1 ]
O U T PU T
D AT AIN !OE
D AT AIN
D AT AD
com b~317
PAD O U T
d a ta _ w r _ o u t[1 0 ]
dataC [15] penableA
com b~316
D AT AC
D A T AA
dataC [14]
penableB
LC ELL ( 3322) C OM BOU T
LC ELL (32F F )
D AT AA
LC ELL ( F F F E)
C O M BO U T
D AT AD
D AT AB
D AT AC D AT AD
D AT AB
d a ta _ w r _ o u t[1 2 ]
d a ta _ w r _ o u t[1 1 ] D AT AIN !OE
dataC [12]
! AC LR
! A C LR C LK
PAD O U T
O U T PU T
dataC [7]
C LK
re q C
data_out_mux[0]~ 688
addC [0]
dataA[11]
LC ELL ( 5050)
rw A
c lk
addB[9]
dataA[10]
c u r r _ s ta te .s 3 re s e t c lk re q A re q B
m e m o r y:m e m
addB[7]
d a ta _ w r _ o u t[5 ] D AT AIN
PAD O U T
!OE
d a ta _ w r _ o u t[5 ]
O U T PU T
d a ta _ w r _ o u t[4 ]
d a ta C [1 1 ] d a ta C [1 2 ] d a ta C [1 3 ] d a ta C [1 4 ] d a ta C [1 5 ]
D AT AIN
PAD O U T
!OE
d a ta _ w r _ o u t[4 ]
O U T PU T
d a ta _ w r _ o u t[3 ] D AT AIN
PAD O U T
!OE
d a ta _ w r _ o u t[3 ]
O U T PU T
d a ta _ w r _ o u t[2 ] D AT AIN
PAD O U T
!OE
d a ta _ w r _ o u t[2 ]
O U T PU T
d a ta _ w r _ o u t[1 ] D AT AIN
PAD O U T
!OE
d a ta _ w r _ o u t[1 ]
O U T PU T
d a ta _ w r _ o u t[0 ] D AT AIN
PAD O U T
!OE
d a ta _ w r _ o u t[0 ]
O U T PU T
p r e s e n t~ 1 4 D AT AB D AT AD
C OM BOU T
p r e s e n t[2 ] D AT AIN
PAD O U T
!OE
LC ELL ( 0033)
p r e s e n t[2 ]
O U T PU T
p r e s e n t[1 ] D AT AIN
PAD O U T
!OE
p r e s e n t[1 ]
O U T PU T
p r e s e n t[0 ] D AT AIN
PAD O U T
!OE O U T PU T
p r e s e n t[0 ]
MAIN - FLOW RESULT
Memory-entity
MEMORY – RTL VIEW
MEMORY – Technology view
Memory flow summary
Mux entity
Mux flow diagram
Mux rtl
MuX – tech view
AGENDA
Introduction Approach VHDL implementation RTL Viewer Simulation results Conclusion
SIMULATION STATE DIAGRAM
CONDITIONS GENERATED BY SIMULATION
Memory simulation
Mux simulation
MMU-SIMULATION
AGENDA
Introduction Approach VHDL implementation RTL Viewer Simulation results Conclusion
CONCLUSION
Memory can be simultaneously serviced to multi processes.
Being an Interrupt service procedure, time of processor is managed efficiently.
FPGA/VHDL combination is a very powerful design tool. •
Versatile, Adaptable, Efficient, Economic
The given algorithm can be used to implement process scheduling.
REFERENCES
A VHDL Primer, 3rd edition : J. Bhasker Computer Organization and Architecture: William Stallings
"It's
not
Thanks
that
i
am
genius,
but i stay a little longer with problems"
-
Einstein.
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