Measurements And Analyses Of Substrate Noise

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 19, NO. 6, JUNE 2000

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Measurements and Analyses of Substrate Noise Waveform in Mixed-Signal IC Environment Makoto Nagata, Associate Member, IEEE, Jin Nagai, Takashi Morie, and Atsushi Iwata, Member, IEEE

Abstract—A transition-controllable noise source is developed in a 0.4- m -substrate -well CMOS technology. This noise source can generate substrate noises with controlled transitions in size, interstage delay and direction for experimental studies on substrate noise properties in a mixed-signal integrated circuit environment. Substrate noise measurements of 100 ps, 100- V resolution are performed by indirect sensing that uses the threshold voltage shift in a latch comparator and by direct probing that uses a PMOS source follower. Measured waveforms indicate that peaks reflecting logic transition frequencies have a time constant that is more than ten times larger than the switching time. Analyses with equivalent circuits confirm that charge transfer between the entire parasitic capacitance in digital circuits and an external supply through parasitic impedance to supply/return paths dominates the process, and the resultant return bounce appears as the substrate noise. Index Terms—Mixed analog–digital integrated circuits, substrate coupling, substrate Noise measurements, signal integrity.

I. INTRODUCTION

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YSTEMS-ON-A-CHIP (SOC) very large scale integrations (VLSI’s) require functional analog circuits such as analog-to-digital/digital-to-analog (AD/DA) converters, radio frequency (RF) circuits, and CMOS imagers to be placed on a die with high-speed digital processing circuits comprising millions of logic elements. Crosstalk from the digital circuits is a major cause of degrading analog signal integrity. Prediction of the system performance through a full-chip crosstalk verification is an essential part of a reliable mixed-signal LSI design. However, there is some difficulty caused by the fact that the crosstalk transmits mainly as substrate noise and is mixed with the analog signals through nonideal operations among analog circuits. Accordingly, it is necessary to develop compact substrate noise simulation models for efficient time-domain continuous analyses. Differential analog circuits show crosstalk rejection to a finite extent. The timing separation of analog clocks from their digital counterparts alleviates this problem as long as discrete time analog systems are used. Remedies widely used in the layout work include separate routing of analog supply/return paths from that for digital paths, guard-banding with dedicated

Manuscript received October 1, 1999; revised February 4, 2000. This work is supported by Semiconductor Technology Academic Research Center (STARC). This paper was recommended by Associate Editor R. Saleh. The authors are with the Faculty of Engineering, Hiroshima University 1-4-1 Kagamiyama, Higashi-Hiroshima, 739-8527 Japan. Publisher Item Identifier S 0278-0070(00)05343-4.

pads, and insertion of on-chip decoupling capacitors to the digital supply paths. Each of those measures has proven itself to be effective; however, the effective use of them has relied on the experience of designers. Early optimization in floor plans, timing, performance margins, and circuit topologies based on figures of their effects are necessary for meeting the short turnaround-time developments required by current industrial applications, which also necessitate chip-level substrate noise simulation techniques. The substrate itself can be treated as an equivalent resistive mesh or expressed in the form of an impedance matrix, thanks to well-established efficient node reduction techniques [1]–[4], point to point impedance calculation methods [5], and other advances. However, for simulating the noise generation process in large scale logic circuits, dynamic treatments are necessary. Here, simplification methodologies play a major role. A solver proposed in [6] formulates all of the parasitic effects between capacitors in the logic circuits, inductors in an assembly, resistors in the substrate mesh, and so on in a Laplace domain by applying asymptotic waveform evaluation [7]. A set of impulse stimuli representing logic switching currents are input to the system, and transient noise waveforms are calculated from the frequency domain responses by inverse Laplace transformation. On the other hand, the entire system is evaluated at a designer-specified frequency in [8], where all memory components can be treated as memoryless and, thus, resistive, and the reduced admittance matrix for the system response is prepared. Spatial noise amplitude distribution is estimated by injecting a sinusoidal supply current with a magnitude preestimated from power analyses to the matrix. Other approaches use behavioral modeling in an HDL-based simulation environment [9], [10], where acquisition of digital transition frequency from the event driven simulator and substrate noise synthesis as a function of that quantity in the continuous time simulator can be integrated. We have proposed mixed-level full-chip substrate noise verification techniques that use a macroscopic substrate noise model and have reported their validity based on the fact that performance deterioration in a modulator coupled with a digital noise source second-order could be simulated in several hours, which would take more than a month or be impossible with conventional circuit simulators [11]. In order to achieve reliable substrate noise analyses with those methodologies, exact and detailed understanding of the substrate noise properties is necessary. Although in-depth studies

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Fig. 1. Circuit schematic of transmition-controllable noise source.

Fig. 2. Substrate noise measurement techniques. (a) LC: Indirect sensing by the threshold voltage shift in a latch comparator. (b) SF LC: Direct probing by a PMOS source follower.

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on substrate noise propagation have been reported [2], [12], substrate noise generation mechanisms in large scale digital circuits have not been clarified. Further experimental research is required to elucidate this issue. Section II describes a design of a transition-controllable noise source and proposes two substrate noise measurement techniques for realizing 100 ps, 100- V resolution. A set of measurement results clarifying the substrate noise generation mechanism will be also provided. Then, substrate noise modeling with equivalent circuit models is proposed and substrate noise analyses by circuit simulation are discussed. II. SUBSTRATE NOISE MEASUREMENT WITH HIGH TEMPORAL RESOLUTION A. Noise Source and Detector Circuit Design A transition-controllable noise source (TCNS) is shown in Fig. 1. The circuit has a multiphase clock (Ck[0:10]) generator, which consists of odd delay elements in series, and a matrix of noise source blocks. The delay element has bias voltages and for regulating rise and fall delay, respectively. Inverse or noninverse transition among the adjacent noise source blocks are selective. The number of noise source blocks to be activated by Ck[0:10] can be 0–15, which is set by address signals x[0:3]

with weights. Hence, the circuit can generate substrate noises with controlled transitions in size, interstage delay and direction. The noise source block includes 30 inverters operating in parallel. Each inverter has a 50-fF load capacitor against the substrate, corresponding to two-gate input capacitances and 400 m AL1 wires. Gate widths are chosen to have a switching time of 200 ps for both rise and fall transitions while driving the load capacitor. The minimum gate length is used. Multiple drivers from the delay element to the inverters shape the clock signal negligible. and make the delay time dependence of Two substrate noise measurement techniques have been developed (Fig. 2). Both use a comparator based equivalent sampling technique developed by Fukuda et al. [13]. The differential latch comparator (LC) shown in Fig. 3(a) has been chosen for the substrate noise detector circuits in our design because a high temporal resolution can be expected due to the large gain in positive feedback. In the first method shown in Fig. 2(a), substrate voltage change is traced as threshold voltage shifts in the latch is measured as a comparator. The shift represented as difference between a static threshold voltage adjusted at with a conventional offset canceling technique and a dynamic determined when amplifying a small threshold voltage voltage difference at the differential input. Here, sensitivity to the substrate potential arises mainly from body coefficient mismatches among MOSFET’s in the cross-coupled latch of the comparator, where common-mode rejection capability expected from the differential and symmetric design is degraded. This circuit is named the LC detector. follows to (1), where input voltage Determination of increases with a step of , and probability , which is defined at as an average of test outputs, is measured at each step. the largest slope in a meta-stable region is a good approximation of at

(1)

Fig. 3(b) shows a timing diagram. Clock pulses are for the comparator, where determines a test point at , separates time zones of the decision from that of an adjustment, and latches offset canceling for the static stimulates the multiphase clock generator of the the output. noise source. with a 200-ns pulse width A test period is 2000 ns, where is located sufficiently within the decision zone and the sub. Thus, strate is expected to be stable outside the vicinity of the comparator only senses the substrate voltage change at just . is moved backward with a step of relative to , is determined according to (1) and the test is iterated until in every time step. Resolutions of with V and 100 ps are achieved. The other method shown in Fig. 2(b) is a direct probing technique. A -channel source follower (SF) isolated from the substrate by an -well is used as a front-end level shifter for the -contact probe. The latch substrate potential picked up at a comparator serves as a back-end voltage reader. The most apto is determined according to proximate voltage in

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NAGATA et al.: MEASUREMENTS AND ANALYSES OF SUBSTRATE NOISE WAVEFORM IN MIXED-SIGNAL IC ENVIRONMENT

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(a)

Fig. 3. Latch comparator. (a) Circuit schematic. (b) Timing diagram.

(1) at each time step, as with the first method. This combination is called the SF LC detector. Mutual evaluation of substrate noise waveforms measured by the two techniques can improve data reliability. Large bandwidth can be expected for the LC detector because of very small input capacitance in the back terminals of MOSFET’s. However, nonlinear sensitivity is disadvantageous. On the other hand, using the SF LC detector’s source follower results in highly linear sensitivity within a bandwidth of several GHz in a typical design. Note that the SF LC detector alone enables absolute evaluation, including consideration of polarity. We have developed two test chips in a 0.4- m CMOS, -type bulk substrate with a single -well, triple-metal double-poly-Si technology. Circuits are designed with 3.3-V supply voltage. Fig. 4 shows chip microphotographs. While both chips (A,B) have the same TCNS and LC detector, Chip B additionally has the SF LC detector. These chips differ in the distance between the detectors and the noise source, which are placed approximately 750 m apart in Chip A and 300 m apart in Chip B. -contact probe of SF LC is located behind the latch The comparator and is roughly 500 m from the noise source. A symmetric axis of LC faces TCNS so as to eliminate asymmetry in the noise intensity due to the disparity in distance. Exclusive pairs of power supply and return wirings with dedicated bond pads are provided for the noise source matrix in TCNS, for the clock generators/drivers in TCNS and LC detectors, and for the other analog parts. The analog return wirings are isolated from the substrate. Another chip for testing the SF LC detector is fabricated with a 0.6- m CMOS technology, where an external input terminal is provided to the source follower. A mixed-signal LSI test system (HP9494) is used for the substrate noise measurement because of such advantages as integrated functions for test pattern generation and data acquisition with precisely controlled synchronization, programmable edge timing, programmable pin-to-module assignments, and a C-language based programming interface. Application programs for automatic measurement executions that have been developed for

(b) Fig. 4. Microphotographs of 0.4-m CMOS test chips. (a) Chip A. (b) Chip B.

both detectors include control of the comparator clocking, noise . source stimulation, and data processing for extracting Chips are packaged in ceramic 120-pin QFP’s. device under test (DUT) boards for electrical connection to the LSI tester are provided for each of the chips. Each of the power supply/return pairs is connected to an individual dc resource of the tester, and all of the return paths are connected to ground plates of the DUT board. In particular, isolated power sources are assigned to the pair for the noise source matrix and the pair for the analog parts of the detectors in order to avoid intersupply couplings in a measurement system. Both sides of the boards are covered with copper thin films patterned but not stripped off in order to form a large ground plate, where a QFP socket, 100-nF ceramic and 10- F electrolytic shunt capacitors on every supply/return pair, and some monitor terminals are soldered. B. Measurement Results First, the performance of the SF LC detector was verified. Fig. 5 shows sensing results of external sine waves up to 100 MHz with 10-mV amplitude centered at 0.0 V by the SF LC detector in the 0.6- m CMOS test chip with reso200 V and 100 ps. The detector is lutions of operated in the same way as in the substrate noise measurement. Uncertainty in reproduced waveforms can be reduced to the order of 100 V by averaging. Linear sensitivity was confirmed as shown in Fig. 6. Inputs are 100-MHz sine waves centered at 0.0 V with 6-dB increments in the amplitude where 0 dB corresponds to 10 mV. The detector can be calibrated by the measured gain of 3.7 dB over a 24-dB input range in order

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Fig. 5. Traces of external sine waves by SF LC detector in 0.6-m CMOS.

Fig. 8. Substrate noise waveforms for fall transitions in Chip B with the number of active noise source blocks as a parameter. Arrows indicate the subpeaks corresponding to the noise source block operation driven by Ck[0:10]. (a) Measured by LC detector. (b) Measured by SF LC detector.

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Fig. 6.

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Linear sensitivity of SF LC detector in 0.6-m CMOS.

Fig. 9. Substrate noise waveforms for rise transitions measured by LC detector in Chip A. Interstage delay increases from (a) to (d).

Fig. 7. Substrate noise waveforms for rise transitions in Chip B with the number of active noise source blocks as a parameter. (a) Measured by LC detector. (b) Measured by SF LC detector.

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to realize an absolute substrate noise evaluation. However, the calibration is not applied for the measured results reported here because unfortunately the substrate noise test chips shown in Fig. 4 use a different CMOS process. Simulated gain and 3-dB bandwidth for the SF LC detector in a 0.4- m CMOS 1.9 V are 1.3 dB and 2.4 technology that is biased at GHz, respectively. Figs. 7 and 8 are measured substrate noise waveforms for rise and fall transitions in TCNS in Chip B, respectively. Eleven subpeaks that coincide with the noise source block action driven by the 11 noninverse phase clocks Ck[0:10] are clearly observed. Subpeak amplitudes increase with the number of active noise

source blocks. Note that all of the subpeaks show positive increase for both rise and fall transitions. The mechanisms behind these results are discussed in a later section. Traces obtained by the LC and the SF LC detectors are very consistent, which justifies these measurement techniques. Direct coupling of LC to SF inside the chip prevents bandwidth degradation since SF is segregated from parasitic passive elements in assembly and in probes of measurement equipment. However, slight bluntness is seen in the traces by the SF LC detector due to an unavoidable bandwidth limitation in the source follower. Fig. 9 shows change in the substrate noise waveforms for rising transitions while increasing the interstage rise delay from approximately 1.5 ns to 2.5 ns [Fig. 9(a)–(d)], by adjusting while 0.0 V. rises at 2 ns and then 15 noise source from the blocks each are activated by noninverse Ck[0:10]. clock generator in TCNS is monitored for estimating the interstage delay ( ) prior to the waveform measurements, and an is disabled during the measurements to output driver for prevent interference with output load driving current. Intensive peaks followed by slow large ringing appear in Fig. 9(a). The peaks start to split into subpeaks and the ringing decreases in Fig. 9(b). Finally, the subpeaks corresponding

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Fig. 10. Substrate noise waveforms for inverse transitions measured by LC detector in Chip A. Rise-to-fall delay increases from (a) to (b) while fall-to-rise delay is minimized.

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Fig. 12. Ringing peak amplitude V versus =T . Points (a e) correspond to labeled substrate noise waveforms in the inset. Waveforms right after the noise source operations are obtained by SF LC detector in Chip B.

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Fig. 11. Subpeak interval T and with T at dc level versus bias voltage V regulating interstage rise delay, measured by LC detector in Chip A. T estimated from P , simulated switching time T are also shown. (a) Rise transitions. (b) Inverse transitons.

to the 11 delayed edges become clear in Fig. 9(d). Here, the largest peaks in the supply current from Fig. 9(a) to Fig. 9(d) are induced in Fig. 9(a), which leads to strong interference between the ringing and the subpeaks during the noise source at work and also the subsequent ringing. As the current reduces, the ringing is suppressed and the subpeaks become distinctive. Amplitude modulation in Fig. 9(d) results from beating between the subpeaks and fast ringing. Obviously, these processes indicate the effect of inductances that are parasitic to the supply/return paths. Fig. 10 shows substrate noise waveforms for inverse transitions. The delay time from rise to fall transitions is larger in Fig. 10(b) than in Fig. 10(a), while that from fall to rise transi0.0 V) and estimated at about 800 ps tions is minimized ( by simulation. Note that each of the subpeaks includes substrate voltage changes originating from the fall and the next rise tranis defined as the interval between these pairs and is sitions. approximately 2.5 ns in Fig. 10(a) and 6.0 ns in Fig. 10(b). and width at Fig. 11 summarizes the subpeak interval 0 V extracted from measured substrate noise waveand estimated by forms. Obvious agreement between proves the correspondence of the subpeaks to monitoring is always more the noise source blocks. The graph shows that , although all than a few times larger than the switching time of the state transitions involved in each subpeak are completed at the same time among parallel inverters in the noise source is 210 ps/170 blocks belonging to Ck[i]. Here, simulated is neglips for rise/fall transitions and its dependence on becomes larger for the gible, as was mentioned. Moreover, inverse transition with the minimum delay time from the fall to rise transitions. This is because each of the subpeaks merges changes in substrate voltage through successive transitions, as

shown in Fig. 10. for large indicates that each substrate voltage change arising from the corresponding noise increases with source block becomes independent, while for small due to interference among adjacent subpeaks. Fully independent subpeaks obtained with a considerably large interof 2.5 ns, which is on the order of ten times stage delay have , as shown in Figs. 7 and 8. larger than Another significant component of the substrate noise is the ringing, as shown in Fig. 9(a). Rapid change in the supply current leads to the ringing, generally at the beginning and/or at the end of a processing series in a digital block. Fig. 12 shows the versus obtained from waveringing peak amplitude forms given in the inset taken right after completing the state transitions in all of the noise source blocks driven by Ck[0:10]. in the supply current at Since the ringing arises from large has a strong relation to . There the end of the operation, is little change in ringing frequency among these waveforms, where , are since it is inherently determined from the components that are parasitic to the supply/return paths. For these measurements, the LC detector in Chip A is used in Figs. 9–11, and the SF LC detector in Chip B is used in Fig. 12. 100 V and 100 ps in Figs. 7–12. Resolutions are Observed features of the substrate noise are: 1) principal components in the substrate noise are subpeaks and ringing; 2) subpeaks reflect the logical transition activity and show relaxation processes with a time constant on the nanosecond order; and 3) subpeaks have positive amplitude unrelated to the direction of included state transitions. These results confirm that voltage bounce on the return path appears directly in the substrate noise. III. SUBSTRATE NOISE ANALYSES A. Analyses by Equivalent Circuit Models of Substrate Noise Injection Fig. 13 shows simplified equivalent circuits of a logic element Fig. 13(a) and a digital functional block Fig. 13(c). Switching action to charge or discharge load capacitance determines logical output. Here, selects a logical state from a truth table inputs. Switches are realized by -MOSFET’s with for channel resistance in CMOS technology. The load capacitance

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Fig. 14. Spatial distribution of parasitic capacitance. C , C , and C are collectives of the capacitances in logic element groups switching in rise, switching in fall, and remaining in current states, respectively.

Fig. 13. Equivalent circuits for substrate noise simulation. (a) A logic element and (b) its symbol. (c) A digital block.

includes output capacitances , formed by S/D diffu, in the following sions and a total input capacitance logic elements where gate-to-channel and interconnect capacitances are major components. Here, these capacitors parasitic to -MOSFET’s and to N-MOSFET’s are denoted by subscripts “ ” and “ ,” respectively. Other dominant capacitors are , which includes on-chip decoupling capacitors and parasitic components in packages and wires due to assembly, and well . capacitance Supply(Vdd) and return(Gnd) routes append parasitic and , respectively, to the circuit. Since impedance local impedance on Vdd/Gnd within the digital block is negligible among packed logic elements, these are block-to-block or chip-to-supply lumped impedances. Here, the -substrate and -wells are tied to Gnd and Vdd, respectively. For modeling substrate noise generation, a large digital block is partitioned into a set of logic element groups switching in rise, switching in fall, and remaining in current states, as shown are collectives of parasitic capaciin Fig. 14. , , and tances included in those groups and distributed spatially inside the digital block. These are defined according to the following equations:

(2)

(3)

(4) as the total number of logic Here, we introduce a constant as the numelements in the block, and variables bers of active elements switching in the rise/fall directions, and as those of stable elements in the H/L state. These are not instantaneous values at but integrated values around over a period of about , which is a time constant intrinsic to the circuit.

For logic operations during , charge transfer needs to take place. A set of of fast logic state transitions is initiated by rapid charge redis). These transitribution among the capacitances ( , , between tions are then completed by charge transfer of all of the distributed capacitances and an external supply with a time constant given roughly by the product of and . Here, is approximately time-invariant, assuming a steady logic activity. as a local distributed charge The former process uses . Here, is reservoir and guarantees the switching time large enough to dominate all of the parasitic capacitances and . For example, a gate-block stores 250 pF in a with a 20% activation ratio results in about 0.4- m CMOS technology. The current due to the charge redistribution is a minor contributor to the substrate noise. Thus, it can be conceived that the sub. A part strate noise amplitude shows a weak dependence on of the current injected to the substrate through capacitive coupling at S/D diffusions and interconnecting wires is immediately through the neighboring substrate contacts collected to and, thus, does not spread widely in the substrate. Other parts, including a capacitively coupled current at the gate-to-channel capacitance and a short circuit current due to the finite switching -MOSFET’s, flow directly in highly conductive time in . metallic wirings to On the other hand, supply currents have slow changes due to the latter process and cause supply/return bounces, including the broad subpeaks and ringing components from flowing through and . Since the substrate surface is tightly coupled to the return paths through distributed substrate contacts, the return bounce leaks to the substrate and appears as the substrate noise. These microscopic views are supported by the measured substrate noise waveforms. First, since the return current always flows toward the system after the charge redistribution, the substrate ground via noise has positive amplitude regardless of the composition ratio of rise-to-fall transitions as long as inductive interaction such as ringing is negligible, as shown in Figs. 7 and 8. Second, if capacitances being discharged are considerably larger than those being charged, most of the charge transfers finish locally by short circuit currents of the discharging capacin itors, and smaller supply current is required. for rising transition, and in for falling transition, are possible cases. This imbalance happens in TCNS since the noise source inverters have 50 fF capacitances against the substrate. As a result, the substrate noise amplitudes for the

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falling transitions are smaller than those for the rising transitions. We can say that such strongly biased distribution of the parasitic capacitance does not occur in ordinary integrated circuits. B. Simulation Results Fig. 15 gives SPICE simulation results for TCNS working 2.2 ns ( 1.8 V, and in the rise transitions with 0.0 V), where waveforms corresponding to the first three and of 1 without stages in Ck[0:10] are shown. any inductance are placed between TCNS and external power supplies. Analyses with a full transistor description of TCNS and those with an equivalent circuit description based on Fig. 13 show ) at the noise source consistent results for the node voltage ( inverter outputs in each of the noise source blocks that are driven one after another by Ck[0:10]. There are also consistent results ) after . The supply current for the substrate voltage ( ) flowing in and currents inside each of the noise ( ) are shown in Fig. 15(c), where the full source blocks ( result transistor description is used. Very sharp peaks in from the rapid charge redistribution that realizes the approxi. On the other mately 200-ps gate switching time shown in due to the slow charge hand, broad and reduced peaks in , which has a transfer from the external supply determine width that is a few times larger than the switching time. Fig. 16 shows simulated substrate noise waveforms for the rise transitions with different interstage delay. The test circuit includes TCNS with the full transistor description, passive components parasitic to the Vdd/Gnd paths, and decoupling. Here, the extracted value of by measurement is 59 nH. This includes inductances parasitic to the bonding wires, package leads, and socket leads, as well as wirings on the DUT board of the measurement system. The tendency in the waveforms where the subpeaks become clear for the larger interstage delay is consistent with the measured waveforms shown in Figs. 9 and 7. Detailed structure differs due mainly to simplification of parasitic circuit networks, however, the test circuit can serve as a tester for optimizing the decoupling circuit design. These simulation results qualitatively prove the substrate noise generation process discussed in the previous section. Quantitative estimation becomes possible if a substrate model with an appropriate resistive mesh is intermediate between digital and analog circuits, where decay due to the distance, suppression by guard banding, and geometrical effects due to substrate contact arrangements can be properly evaluated. IV. CONCLUSION A transition-controllable noise source is developed in a 0.4- m CMOS, -substrate -well technology. This noise source can generate substrate noises with controlled transitions in size, interstage delay and direction. Substrate noise measurements of 100 ps, 100- V resolution are performed by indirect sensing that uses the threshold voltage shift in a latch comparator and by direct probing that uses a PMOS source follower.

Fig. 15. SPICE simulation results with a full transistor description and with the equivalent circuits of TCNS. (a) Node voltages V ; i at noise source inverter outputs in each stage i. (b) Substrate voltage V . (c) Supply current I flowing in Z and currents inside noise source blocks I .

Fig. 16. Substrate noise waveforms with different interstage delay simulated by SPICE. (a) Simulated circuits including passive components parasitic to supply/return paths. Full transistor description of TCNS is used. (b) Simulated waveforms for different interstage delays.

Measured waveforms indicate that the voltage bounce on the return path leaks to the substrate and appears as the substrate noise, where the dominant components are subpeaks reflecting logic transition frequencies, which have a time constant that is more than ten times larger than the switching time, and slow ringing. Analyses with equivalent circuits confirm that the bounce results from the charge transfer between the parasitic capacitance of all of the digital circuits and an external supply, operating through supply/return parasitic impedance. Ringing must be considered for digital designs with intermittent processing, such as those in portable electronics, since it appears at the beginning and at the end of a series of logic transitions. These results can be the basis of reliable substrate noise modeling methodologies that target chip-level verification. Precise

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and compact supply current models incorporating the charge redistribution effect and continuous re-charging process of the entire set of logic capacitances will play essential roles in future developments.

ACKNOWLEDGMENT The authors would like to thank Dr. T. Kozawa, Dr. K. Mashiko, Dr. T. Iida, Dr. H. Ishikawa, and Dr. M. Yotsuyanagi for helpful discussions. The chips were fabricated by Rohm Corporation and Toppan Printing Corporation through VLSI Design and Education Center (VDEC), the University of Tokyo, and also by Ricoh Corporation

REFERENCES [1] T. A. Johnson, R. W. Knepper, V. Marcello, and W. Wang, “Chip substrate resistance modeling technique for integrated circuit design,” IEEE Trans. Computer-Aided Design, vol. CAD-3, pp. 126–134, Apr. 1984. [2] N. K. Verghese, T. J. Schmerbeck, and D. J. Allstot, Simulation Techniques and Solutions for Mixed-Signal Coupling in Integrated Circuits. Norwell, MA: Kluwer Academic, 1995. [3] I. L. Wemple and A. T. Yang, “Integrated circuit substrate coupling models based on voronoi tessellation,” IEEE Trans. Computer-Aided Design, pp. 1459–1469, Dec. 1995. [4] N. K. Verghese, D. J. Allstot, and M. A. Wolfe, “Verification techniques for substrate coupling and their application to mixed-signal IC design,” IEEE J. Solid-State Circuits, vol. 31, pp. 354–365, Mar. 1996. [5] R. Gharpurey and R. G. Meyer, “Modeling and analysis of substrate coupling in integrated circuits,” IEEE J. Solid-State Circuits, vol. 31, pp. 344–353, Mar. 1996. [6] B. R. Stanisic, N. K. Verghese, R. A. Rutenbar, L. R. Carley, and D. J. Allstot, “Addressing substrate coupling in mixed-mode IC’s: Simulation and power distribution synthesis,” IEEE J. Solid-State Circuits, vol. 29, pp. 226–238, Mar. 1994. [7] L. T. Pillage and R. A. Rohler, “Asymptotic waveform evaluation for timing analysis,” IEEE Trans. Computer-Aided Design, vol. 9, pp. 352–366, Apr. 1993. [8] S. Mitra, R. A. Rutenbar, L. R. Carley, and D. J. Allstot, “A methodology for rapid estimation of substrate-coupled switching noise,” in Proc. IEEE Custom-Integrated Circuits Conf., May 1995, pp. 129–132. [9] M. K. Mayes and S. W. Chin, All verilog mixed-signal simulator with analog behavioral and noise models, in Dig. Tech. Papers, Symp. on VLSI Circuits, pp. 186–187, June 1996. [10] M. Nagata and A. Iwata, A macroscopic substrate noise model for full chip mixed-signal design verification, in Dig. Tech. Papers, Symp. on VLSI Circuits, pp. 37–38, June 1997. , “Substrate noise simulation techniques for analog-digital mixed [11] LSI design,” IEICE Trans. Fundamentals, vol. E82-A, no. 2, pp. 271–278, Feb. 1999. [12] D. K. Su, M. J. Loinaz, S. Masui, and B. A. Wooley, “Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits,” IEEE J. Solid-State Circuits, vol. 28, pp. 420–430, Apr. 1993. [13] K. M. Fukuda, T. Anbo, T. Tsukada, T. Matsuura, and M. Hotta, “Voltage-comparator-based measurement of equivalently sampled substrate noise waveforms in mixed-signal integrated circuits,” IEEE J. Solid-State Circuits, vol. 31, pp. 726–731, May 1996.

Makoto Nagata (M’95–A’96) received the B.S. and M.S. degrees in physics from Gakushuin University, Tokyo, Japan, in 1991 and 1993, respectively. From 1994 to 1996, he was a Research Associate at Research Center for Integrated Systems, Hiroshima University, Higashi-Hiroshima, Japan,. He is currently a Research Associate of the department of Electrical Engineering, Hiroshima University. His research interests focus on mixed-signal LSI design techniques. Substrate crosstalk modeling and reduction methodologies, circuit modeling techniques in Analog HDL, and development of merged analog-digital PWM based time domain signal processing architectures are included. He is a member of the IEICE.

Jin Nagai was born in Hiroshima, Japan, on February 28. He is presently with the Department of Engineering, University of Hiroshima, Higashi-Hiroshima, Japan, and working toward the B.E. degree. His research interests are measurements of substrate Noise in AD mixed LSI’s.

Takashi Morie received the B.S. and M.S. degrees in physics from Osaka University, Osaka, Japan, and the Dr.Eng. degree from Hokkaido University, Hokkaido, Japan, in 1979, 1981, and 1996, respectively. From 1981 to 1997, he was a member of the Research Staff at Nippon Telegraph and Telephone Corporation (NTT). Since 1997, he has been Associate Professor at the Faculty of Engineering, Hiroshima University, Higashi-Hiroshima, Japan. His main interest is in the area of VLSI implementation of neural networks, analog-digital mixed/merged circuits, and new functional devices. Dr. Morie is a member of the IEICE of Japan, the Japan Society of Applied Physics, and the Japanese Neural Network Society.

Atsushi Iwata (M’87) received the B.E., M.S., and Ph.D. degrees in electronics engineering from Nagoya University, Nagoya, Japan, in 1968, 1970, and 1994 respectively. From 1970 to 1993, he was at the Electrical Communications Laboratories, Nippon Telegraph and Telephone Corporation (NTT). Since 1994, he has been a Professor of Electrical Engineering at Hiroshima University, Higashi-Hiroshima, Japan. His research is in the field of integrated circuit design where his interest have included, circuit architecture and design techniques for analog-digital mixed LSI’s, analog-to-digital converters, image processors, and bio-inspired intelligent processing LSI’s. Dr. Iwata received an Outstanding Panelist Award for the 1990 International Solid-State Circuits Conference. He is a member of IEICE and the Japanese Neural Network Society. He was the Program Chairman for the 1995 Symposium on VLSI Circuits. He has been the Chairman for the 1999 Symposium on VLSI Circuits, and an Associate Editor of IEEE JOURNAL OF SOLID STATE CIRCUITS from 1996.

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