M Level Controller

DESIGN AND IMPLEMENTATION OF LEVEL CONTROLLER USING VHDL TOOL

AIM: The aim of the project is to design a Level Controller using VHDL software tools and implement it in programmable IC PAL/FPGA. THEORY: The Water Level Controller is used to control the level of water or any liquid in a container. The level controller generates the sequence of control signals that can be used to control the level of liquid according to user set inputs. HARDWARE: The hardware of Level Controller consists of SPDT switch settings, PAL C22V10 / FPGA as Level Controller, clock generator and buffer.

LEVEL SENSOR

CONTROL SWITCHES

SIGNAL CONDITI -ONING CIRCUIT

BUFFER

PAL C22V10 (or) FPGA LEVEL CONTROLL -ER

OUTPUT RELAYS BUFFER

CLOCK GENERATOR

Figure: Block diagram of Level Controller SOFTWARE: Using VHDL software tool, a digital system can be designed and simulated. Also the Timings of various signals can be verified. Then the system can be implemented in PAL C22V10 using WARP-R4 or can implemented in ALTERA/ATMEL FPGA using MAX plus II/IDS 6.0. APPLICATIONS: The Level Controller are popularly used in  Water Tank  Reservoir