List Of Figures

List of figures

LIST OF FIGURES Fig. no

Figure

Page no

2.1

Monolithic Shared-bus architecture

06

2.2

Split shared-bus architecture

06

2.3a

Bus structure

08

2.3b

Data propagation in request phase

08

2.3c

Data propagation in response phase

08

2.4

Structure of a 3-segment split bus arbiter

10

2.5

Partial logic of an arbitration agent

11

2.6

Segmented bus structure

12

2.7

Segment components with signals

13

2.8

Control flow in Local Arbiter

14

2.9

A typical AMBA AHB-based system

17

2.10

Multiplexer interconnection

18

2.11

Simple transfer

19

2.12

Transfer with wait states

20

2.13

AHB bus Arbiter Interface

22

2.14

Core-Connect Based System-On-a-Chip

23

2.15

Example of PLB interconnections

25

2.16

DCR Bus Structure

27

3.1

SAMBA Bus

29

3.2

Multiple Bus access with single arbitration

30

3.3

Logic operation in request phase of a forward access Controller

3.4 4.1.

31

Logic operation in response phase of a backward access Controller

32

Bus using By-pass technique

35

3

List of figures

4.2.

Bus using Demultiplexers

37

4.3a

Before the re-mapping

39

4.3b

During the re-mapping

39

4.3c

after component re-mapping

40

5.1

Avarage communication latency Vs Communication Distance (d)

52

5.2

Avarage communication latency Vs Number of modules

53

5.3

Expected bandwidth characteristics

54

4