Libero Ide - Session 1
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Libero™ Integrated Design Environment Actel Corporation Mountain View, CA – USA
Outline Session 1: Introduction to Actel products Libero IDE overview and design flow Design entry Session 2: Functional simulation Synthesis Session 3: Place & Route Session 4: Post-Layout simulation Programming
Libero™ IDE
© 2005 Actel Corp.
July, 2005
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1
Introduction to Actel Products
Actel Commercial Product Spectrum Markets Full Featured FPGA
Axcelerator Axcelerator >500MHz >500MHz
PLUS ProASIC ProASICPLUS
150MHz 150MHz
Economy FPGA
ProASIC ProASIC 100 100 MHZ MHZ
SX-A SX-A 250 250 MHz MHz
CPLD Equivalent
eX eX 250 250 MHz MHz
3,000
10,000
100,000
1M
2M
Density Libero™ IDE
© 2005 Actel Corp.
July, 2005
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2
FPGA Technologies Compared
SRAM
Flash
Antifuse
1T 6T Best of Both Worlds Reprogrammable & Nonvolatile
Reprogrammable
Libero™ IDE
© 2005 Actel Corp.
Nonvolatile
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Flash Product Offering Benefits of flash FPGA technology Lowest power in its class In-system programmable Non-volatile Single-chip Lowest system cost
Product Product
KKGates Gates
Max MaxI/O I/O
Leading Leadingfeatures features
ProASIC ProASIC
475 475
440 440
ISP, ISP,2P-RAM/FIFO, 2P-RAM/FIFO,FlashLock, FlashLock,Mixed Mixed2.5V/3.3 2.5V/3.3I/O I/O
712 712
ISP, ISP,2P-RAM/FIFO, 2P-RAM/FIFO,PLLs, PLLs,LVPECL, LVPECL,FlashLock FlashLock
PLUS ProASIC 1000 ProASICPLUS 1000
Libero™ IDE
© 2005 Actel Corp.
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Antifuse Product Offering Benefits of antifuse FPGA technology High performance
Secure FuseLock Technology
Low power
Live at power-up
Single-chip
Cost effective
High utilization/100% pin locking
Firm error resistant
Product Product
KKGates Gates Max MaxI/O I/O Leading Leadingfeatures features
SX-A SX-A
108 108
360 360
350MHz, 350MHz,64/66 64/66PCI, PCI,2.5/3.3/5V 2.5/3.3/5VHot HotSwap SwapI/O I/O
eX eX
12 12
130 130
Single-chip Single-chipFPGA FPGAoffered offeredat atCPLD CPLDdensities densities
MX MX
54 54
202 202
Best Best55volt voltsolution, solution,Embedded Embeddedblock blockRAM RAM
RTSX-S RTSX-S
108 108
205 205
SEU SEUimmune immunewith withbuilt-in built-inTMR TMR
Axcelerator Axcelerator
2000 2000
684 684
500MHz 500MHzcore/FIFO, core/FIFO,1GHz 1GHzPLL, PLL,LVDS LVDSI/O I/O
Libero™ IDE
© 2005 Actel Corp.
July, 2005
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Libero IDE Overview and Design Flow
4
Libero IDE Overview Complete Toolset for Actel FPGA Development Project Manager ViewDraw Schematic Capture Synplify Synthesis Testbench Generation Mentor ModelSim Simulation PALACE Physical Synthesis (Libero Platinum) Actel Designer Design Implementation Compile, Place & Route Timing and Physical Constraints Timing Analysis Power Analysis Back Annotation Programming File Generation
FlashPro Programming Software Silicon Explorer Debug Software Libero™ IDE
© 2005 Actel Corp.
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Libero Tool Suite Design Implementation
Design Verification
Physical Implementation
Synplify
SynaptiCAD
PALACE •Physical Synthesis
•Integrated Design Environment
• Synthesis
• Stimulus
ViewDraw AE
ModelSim
Actel Designer
•Place & Route
Libero™ IDE
•Schematic Capture
•Simulation
Actel
Actel
• ACTgen Macro builder
• Silicon Explorer Debugger
© 2005 Actel Corp.
FlashPro
•Programming
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5
Libero Project Manager Features Centrally Manages and Integrates Files and Tools Coordinates Project Information between Tools e.g., Family Is Selected Once and Communicated to All Tools
Provides Seamless Piping of Internal Design Files among Tools From within Libero’s Project Manager, User Can Invoke Tools for: Design Entry Stimulus Generation Simulation Synthesis Design Implementation and Static Timing Analysis
Libero™ IDE
© 2005 Actel Corp.
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Libero IDE Project Manager Design Explorer Window
Design Hierarchy Tab Displays Hierarchical Representation of Source Files in Project Libero Continuously Analyzes
and Updates Hierarchy
File Manager Tab Displays All Files in Project Grouped by Type
Language-Sensitive HDL Editor
Verilog 95 or VHDL 93
Design Explorer Window
HDL pane
Tools Can Be Launched from Design Flow Window or Process Window Log Windows Provide Status and Error Messages
Log Window Error Manager Status Bar
Libero™ IDE
© 2005 Actel Corp.
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Libero IDE Design Flow Window
Flow Window Displayed in HDL Pane
Tabs Switch between Flow Window and HDL Window
Libero™ IDE
© 2005 Actel Corp.
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Libero IDE Design Flow Window Step-by-Step design flow decreases design development time Current state of design
Design Flow Window Displays: Tools Files Transitions Current State Tool Tips
Interactive Blocks Activates Tools View Files
Display changes dynamically based on target family
Libero™ IDE
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File Status of Displayed Items Group of Files Can Be … … Missing If ANY Are Missing, Block Is Shadowed Out
… Available and Current Green Check Mark Is Shown
… Available, but Not Current If at Least One is Not Current, Warning Icon Is Displayed
Synthesis Incomplete Libero™ IDE
Synthesis Complete
Source Modified – EDIF Netlist not current
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Tool States Disabled => Button Is Shadowed White => Available, but Not Yet Used Green => Completed Successfully Red => Error in Running Tool
Synthesis Succeeded
Libero™ IDE
© 2005 Actel Corp.
Synthesis Failed
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Libero IDE View Options Displayed Windows Turned On or Off Using Libero “View” Menu
Libero™ IDE
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Libero Log Window Error Manager Error Manager Consists of 4 Tabs in Log Window: All: Displays All Messages Errors: Displays Error Messages Warnings: Displays Warning Messages Info: Displays Information Messages
Default Colors: Red => Errors Blue => Hyperlinks Light Blue => Warnings
Right Mouse Click!
Click in window to clear or copy text
Icon appears next to each message
Libero error manager tabs Libero™ IDE
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Libero Software Updates Manually Check for Software Updates from Help Menu Configure Libero to Automatically Check for Software Updates from
Preferences Tab (File > Preferences)
Libero™ IDE
© 2005 Actel Corp.
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Libero IDE New Project Wizard Menu-Driven Wizard
Use Browse button to change project location
File > New Project
Status Guide Shows Current State All Fields Must Be Filled in to
Continue
HDL Type Must Be Consistent with License Next Button Goes to Next Wizard Screen Finish Button Finishes/Closes Wizard after Making Changes. Saves All Selections.
Libero™ IDE
© 2005 Actel Corp.
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Libero IDE New Project Wizard: Select Device Select Family After Family Is Selected, Devices from that Family Are Displayed After Device Is Selected, Available Packages for that Device Are Displayed
Libero™ IDE
© 2005 Actel Corp.
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Libero IDE New Project Wizard: Select Tools Synthesis
Vendor (e.g. Synplify) Version
Physical Synthesis
PALACE Version
Testbench Generation
WaveFormer Lite Select Version
Simulation
ModelSim Select Version
Support for Mentor Graphic’s LeonardoSpectrum and Precision
Standard Tools Direct from Mentor
Licensing and Technical Support Directly from Mentor
No Actel OEM Versions
Libero™ IDE
© 2005 Actel Corp.
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Libero IDE New Project Wizard: Add Files Add Existing Design Files to Project Schematics, Symbols, HDL (VHDL or Verilog), Stimulus (VHDL or
Verilog), ACTgen Macros or EDIF Netlists
Browse to file location
Select file type
Libero™ IDE
© 2005 Actel Corp.
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Libero IDE New Project Wizard: Finish Project Information Listed in Dialog Box Click “Finish” to Complete Project Creation or “Back” to Make
Corrections or Additions
Project summary shown in window
Libero™ IDE
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Organization of Libero Project Files Default folder for Libero projects
Libero project file
Libero™ IDE
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Libero IDE Project Startup Default Operation Upon Launch of Libero, Most Recent
Project Is Opened If No Project in Most Recently Used
List, Libero Launches the New Project Wizard
Default Controlled in Startup Properties Choose “Preferences” under “File”
Menu Choose “Startup” Tab Check or Uncheck “Open the most
recently used project at startup”
Libero™ IDE
© 2005 Actel Corp.
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Libero Project Manager: Design Implementations Create Project Variations Save Different Project Views for Comparison Requires .adb file, Back-annotated File, Programming/Debugging
File, or Post-layout Simulation Folder
Libero™ IDE
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Libero Project Manager: Design Implementations Add, Rename or remove design implementations
Libero™ IDE
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Libero Project Manager: Design Implementations Implementations Making Changes in Current View Can Change State of Project Pre-Synthesis Post-Synthesis Post-Physical Synthesis Affects All Other Views
Changing Implementation Files for Current View Does Not Affect
Other Views
Libero™ IDE
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Importing Files File -> Import Files Existing Design Files Can Be Imported into Libero Project Schematics, Symbols, HDL (VHDL or Verilog), Stimulus (VHDL or Verilog),
ACTgen Macros, EDIF Netlists, SDC Files, Constraint Files, Tool Profiles Constraint Files NOT Automatically Sent to External Tools
Select file type from pull-down menu
Libero™ IDE
Schematics (*.[1-9]*) Symbols (*[1-9]*) Vhdl Sources (*.vhd, *.vhdl) Vhdl Package Files (*.vhd, *.vhdl) ACTgen Macros (*.gen) Stimulus Files (*.vhd, *.vhdl) Edif Netlists (*.edn) SDC file (*.sdc) Gatefield Constraint files (*.gcf) Tool Profiles (*.ini)
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Import Files: File Manager Tab Files Can Also Be Imported from File Manager Tab Click on File Type and Select Import
Right Mouse Click!
Libero™ IDE
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Deleting Files from Libero Project Files Can Be Deleted from Project and from HDD Files Deleted from HDD Cannot Be Recovered!
Right Mouse Click!
Libero™ IDE
© 2005 Actel Corp.
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Design Hierarchy Tab: Block Properties Block Properties Dialog Box Displays File Path, Date Created and Last Modified Date
Right Mouse Click!
Libero™ IDE
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Libero Project Manager Include Modules for Simulation Libero Only Passes Top-level Source-related Modules to Simulation If Other Source Modules Are Required for Simulation, Check Box on File Properties
Check to include file in simulation
Libero™ IDE
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Unknown Hierarchy Libero Displays Files in “Default Configuration” Tree Missing Files Indicated with “?” When Libero Cannot Determine Hierarchy, Files Are Shown with “X” under Unknown Hierarchy on Design Hierarchy Tab Files also Shown with “X” on File
Manager Tab Examine these Files to Correct Problem
or Remove File from Project
Libero™ IDE
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Package Files Compile Order Package Files Displayed on Libero IDE File Manager Tab VHDL Packages Verilog Include Files
Use Package Files Order Window to Indicate if Packages Are for Simulation, Synthesis or Both and to Set Compile Order Use Up or Down Arrows to Change
Compile Order
Check Boxes to Compile Packages
for Simulation, Synthesis, or Both
Select Options => Package Files Organization, or Right Click in Design Hierarchy Window
Libero™ IDE
© 2005 Actel Corp.
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Libero Project Manager Find Module To find Module in a Hierarchy, click Find Module Icon on Tool bar, or Click Edit/Find Module
Libero selects and displays the found module
Libero™ IDE
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Find in Files Edit => Find in Files, or Toolbar Icons Search for Files, Words, etc Specify by File Types Specify where to Search Match Whole Word Match Case Regular Expression
Results Shown in “Find in Files” Tab in Log Window
Libero™ IDE
© 2005 Actel Corp.
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Find in Files Cross Probing Selecting File Name Presented in Find in Files Log Window … … Opens Selected File in Libero Text Editor … Highlights Match
Libero™ IDE
© 2005 Actel Corp.
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Libero IDE Project Settings Users can change device and specify simulation and programming options Options > Project Settings
Device - change FPGA die or package Simulation - specify simulation options “Compile VHLD Package Files”
option is on by default
Programming – specify location of programming file and software
Libero™ IDE
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OEM Tools Support Tool Profiles Create or Edit Tool Profile for Project Options > Profiles Select Third-Party Tools & Versions Synthesis Vendor (e.g. Synplify) Version
Physical Synthesis PALACE Version
Simulation ModelSim Select Version
Testbench Generation WaveFormer Lite Select Version
Name Profile and Save Edit or Add Profiles As Needed
Libero™ IDE
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Add / Edit Tool Profiles Add/Edit Profile Requires … Name of Profile … Choosing Tool From Drop-down Menu Choose Version
… Choosing Tool Location Browse for Location Specify Location
Libero™ IDE
© 2005 Actel Corp.
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Profile Conflict Occurs when Current Profile Settings Are Different from those of Previous Project that is Opened May Have Newer Version
Selected when Opening Project Created with an Older Version
Libero™ IDE
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Libero IDE Other Features Save Project to Different Name “Save-As” Enables Saving Project
with Different Name and/or in Different Location
Text Editor Selection Use Libero IDE Text Editor or
External Text Editor File > Preferences Text Editor Tab
Drag-Drop Dragging and Dropping Libero .prj
File in Libero Window Opens Project File
Enter location of external text editor if selected Libero™ IDE
© 2005 Actel Corp.
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Libero IDE Online Help HTML-based Help System Help Available for Error Messages,
Specific Screens and Menus Expanded Content
Hyperlinks to Application Notes and
Actel Web Pages Help Menu Provides Direct Access to All Libero PDF Reference Manuals
Libero™ IDE
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Design Entry
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Design Entry Libero Supported Design Flows Structural Schematic Flow Mixed-Mode Flow HDL Flow
ACTgen Macro Builder ViewDraw Overview Schematic Design Entry Tool
Libero™ IDE
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Libero Design Flows
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Libero Design Flows Structural Schematic Flow Contains only Actel ViewDraw Library Components or Mix of Actel
ViewDraw Library Components and Structural HDL Top Level Must Be Schematic! Synthesis Optional before Layout
Mixed-Mode Flow Schematic and RTL Blocks May also Contain Structural HDL Blocks
Top Level Must Be Schematic! Synthesis Required before Layout
HDL Flow VHDL or Verilog (not both) May Contain Structural Blocks
Libero™ IDE
© 2005 Actel Corp.
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ACTgen Macro Builder
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ACTgen Macro Builder
Create Macro Functions from User’s Parameters
Optimized for Actel Architecture
Rule-based Generation Guarantees Functional Accuracy
Outputs:
Libero™ IDE
High Speed Small Area
© 2005 Actel Corp.
VHDL - Behavioral and Structural Verilog Behavioral and Structural
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Using ACTgen within Libero ACTgen Macros Can Be Used in … … Structural Schematic flow … Mixed-mode Flow … HDL Flow
Steps: Launch ACTgen from Libero IDE Project Manager Create HDL Structural Implementation VHDL or Verilog
HDL Flow Instantiate Macro in Top-level RTL
Structural Schematic and Mixed-mode Flows Create ViewDraw Symbol from Libero instantiate Symbol in Schematic
Libero™ IDE
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Launching ACTgen from Libero ACTgen icon
Libero™ IDE
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ACTgen User Interface
Version #
Core details
Shows Categories Based on Selected Family View by category or alphabetically
Version of selected or configured core
View selected and configured cores for project Libero™ IDE
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ACTgen Alphabetical Browse
Libero™ IDE
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ACTgen Browse by Family
Libero™ IDE
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ACTgen Counter Example
1. Choose Function
2. Select type and variation
Libero™ IDE
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ACTgen Counter Example
3. Enter width
4. Complete the rest of the description
Optional Fan-In Control 5. Click Generate Libero™ IDE
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ACTgen Buffering Control Users Can Control Buffering in ACTgen Macros Control Net Loading or
Eliminate Buffering
Libero™ IDE
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Component Generation
Macro name Output format Generate behavioral VHDL or Verilog
Files appear on Libero File Manager tab
Libero™ IDE
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Structural Schematic Designs
Structural Schematic Design Flow Design Capture
Generate Structural Netlist
Pre-Layout Simulation
Place & Route
Post-P&R Simulation
Libero™ IDE
© 2005 Actel Corp.
Programming
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Design Capture Design Capture
Generate Structural Netlist
Pre-Layout Simulation
Place & Route
Post-P&R Simulation
Libero™ IDE
Programming
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ViewDraw Overview Schematic Design Entry Tool
32
ViewDraw Features Powerful Editing Capabilities Simple, Push-Button GUI Enables Rapid Design Input Infinite Undo/Redo Dynamic Pan and Autoscroll Automatic Connection of Abutting Pins Rubber Banding of Connected Nets with Dynamic Redraw
Flexible and Customizable Designers can Add, Delete, or Reorder Items in Menu System Commands Can Also Be Entered via Function Keys or CLI Selectable Display Styles for Lines, Fill Patterns, Bus Widths
Libero™ IDE
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ViewDraw Additional Features ViewDraw AE can read EPD 2.0 and 3.0 Generated schematics Schematic files Outputs in ViewDraw format
ViewDraw can now co-exist/co-install with ePD Customers can switch back and forth between ViewDraw and ePD
tools easily
Libero™ IDE
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Invoking ViewDraw Launch ViewDraw from Libero. Create Schematic Save and Check Right Mouse Click!
Libero™ IDE
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ViewDraw Save+Check Command Window Insert Component
Zoom Functions
Net and Bus Connection
Push symbol or schematic
Drawing Tools
Libero™ IDE
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Inserting ViewDraw Components Add -> Component Enter component name
Select Directory • Project directory •Actel cells •ViewDraw builtin
Component appears here •Drag and drop into schematic Libero™ IDE
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Adding Schematic Border Built-in Library Contains Several Sheet Border Templates Templates Can Be Modified
Enter sheet name (asheet, bsheet, etc.)
Select built-in library Drag and drop into schematic
Libero™ IDE
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ViewDraw Border in Schematic
Libero™ IDE
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Customizing a Schematic Border Border Template Can Be Customized Open Border (File > Open) Select Symbol from “Type” Menu
Select built-in library
Select Symbol
Libero™ IDE
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Customizing a Schematic Border (cont.) Save File to New Name (File > Save Copy As) Border Saved in Project Library
Enter new sheet name
Visible on Libero File Manager Tab
Select project library
Select Symbol
Libero™ IDE
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Customizing a Schematic Border (cont.) Open Saved Border and Edit (File > Open) Add Lines, Arcs, Text, etc. as Necessary Modified border visible on File Manager tab
Libero™ IDE
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Adding Schematic Components Add > Component from ViewDraw Menu Add ACTgen Macros, Custom Macros or Actel Basic Cells Select VCC or GND from ‘actelcells’
Enter cell name
Select cell library Drag and drop into schematic
Libero™ IDE
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Drawing Wires and Busses Adding a Net To Add Net: Choose Add > Net (or Add > Bus) Alternate: Click Wire (
) or Bus (
) Icon on Toolbar
Specify Net Origination Point and Depress Left Mouse Button Drag Mouse to Form Net (or Bus), specifying Points along Net
by Clicking Right Mouse Button Click Right Mouse Button to Insert Vertex in Net Release Left Mouse Button to Specify Ending Point for Net
Libero™ IDE
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Adding I/O Cells Add I/O Cells to Top-level Design Schematic Schematic-only Designs or Structural Schematic Designs Macros Contained in “actelcells” Component Library
I/O Cells Must Have Dangling Hierarchical Connector Attached to Pad Side Label Dangling Connector
I/O Macros Can Be Buried in Hierarchy
Add and label this net
Libero™ IDE
Add and label this net
Add and label this net
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Hierarchical Connectors Use Hierarchical Connectors from ViewDraw Built-in Library for All Designs Add just like Any Other Component Same Connector for Wire or Bus Called ‘in’, ‘out’, or ‘bi’ in Built-in Library
Label Net or Bus Next to Connector
add label to net Libero™ IDE
add label to bus © 2005 Actel Corp.
add label to net
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ViewDraw Attributes A Limited Number of Attributes Can Be Entered into Schematic and Passed to Designer $Array Attribute Creates Arrays of Cells in Schematic Useful for I/O Buffers
Double-click Cell, Enter on Attribute Tab
Libero™ IDE
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Design Rule Checking
At Design Entry Completion , Save and Check Design
Click Save Check Icon Use Tools > Schematic Checker
Viewdraw Status Bar:
Libero™ IDE
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Design Entry Completion Files in Implementation Are Displayed on Libero Design Hierarchy and File Manager Tabs
Schematic
Libero™ IDE
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ViewDraw File Structure on HDD Schematic Files Saved in “sch” Folder Symbol Files Saved in “sym” Folder Wire Files Saved in “wir” Folder Files Visible on Libero File Manager Tab
Libero™ IDE
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Opening Existing Schematics
Right Mouse Click!
Libero™ IDE
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Completed Schematic
Input buffers
Actel library components
Output buffer
Hierarchical
Hierarchical
connectors
connector
Libero™ IDE
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Libero Schematic Checker (Optional) Schematic Connectivity Checker in Libero Checks for Errors Not Included in ViewDraw Save + Check Optional Step Available from File Manager Tab
Right Mouse Click!
Libero™ IDE
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Structural Schematic Flow Using ACTgen Macros Launch ACTgen from Libero Project Manager Create HDL Structural Implementation VHDL or Verilog
Create ViewDraw Symbol from Libero and Instantiate Symbol in
Schematic Symbol Visible on File Manager Tab
Symbol
Right Mouse Click!
Libero™ IDE
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Mixed-Mode Designs
Mixed-Mode Design Flow
Design Capture
Simulation
Synthesis
Post-Synthesis Simulation
Place & Route
Post-P&R Simulation
Libero™ IDE
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Programming
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Design Capture
Design Capture
Simulation
Synthesis
Post-Synthesis Simulation
Place & Route
Post-P&R Simulation
Libero™ IDE
Programming
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Mixed Mode Design Entry Mixed Mode => RTL Blocks within Schematic HDL Blocks Can Be Structural or Behavioral RTL RTL Blocks Can Be VHDL or Verilog (But Not Both)
Top Level Must Be Schematic
Procedure Create HDL Blocks RTL Blocks - Use HDL Editor or Import Existing Design Files Structural Blocks - Use HDL Editor or ACTgen
Create ViewDraw Symbols for HDL Blocks Done Automatically from Libero Design Flow Manager
Instantiate Blocks in Schematics and Make Interconnects Use Hierarchical Connectors from ViewDraw “built-in” Library for HDL
Ports in Schematic
Libero™ IDE
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RTL or ACTgen in Mixed-Mode Flow Create RTL from Libero HDL Editor or Import File
OR Create HDL Structural Implementation using ACTgen VHDL or Verilog
Create ViewDraw Symbol from Libero Instantiate Symbol in
Schematic Symbol Appears on File Manager Tab
Symbol
Right Mouse Click!
Libero™ IDE
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Mixed Mode Schematic
Libero™ IDE
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Synthesize Optional for Pure Schematic or Structural Schematic Flows All HDL Blocks Are Structural VHDL or Verilog (e.g., ACTgen Blocks)
Required for Mixed-mode Designs Designs Containing RTL Blocks
Libero Launches Synplicity to Insert Pads and Optimize Design Hierarchical Connectors Must Be Used Structural Schematics with All Pads Instantiated Can Go Directly to
Designer Tool
Synthesize
Libero™ IDE
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HDL Designs
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HDL Design Flow
Design Capture
Simulation
Synthesis
Post-Synthesis Simulation
Place & Route
Post-P&R Simulation
Libero™ IDE
Programming
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Design Capture
Design Capture
Simulation
Synthesis
Post-Synthesis Simulation
Place & Route
Post-P&R Simulation
Libero™ IDE
© 2005 Actel Corp.
Programming
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Creating New HDL Macros
Libero™ IDE
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HDL Editor
Libero™ IDE
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HDL Editor Block Comments Comment and Uncomment Command Allows Users to Comment or Uncomment Sections of VHDL or Verilog Code
Libero™ IDE
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HDL Editor Detect Changes If File Is Open in Libero HDL Editor and Modified by another Text Editor, Warning Is Issued
Warning message in Libero log window
Libero™ IDE
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Libero HDL Syntax Checker HDL Syntax Checker Available from File Manager Tab Checks for Errors in HDL Blocks Errors Indicated in Libero Log Window Optional Step
Right Mouse Click!
Libero™ IDE
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Project Manager with Saved Files...
VHDL file
Libero™ IDE
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Functional Simulation
Design Capture
Simulation
Synthesis
Post-Synthesis Simulation
Place & Route
Post-P&R Simulation
Libero™ IDE
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Programming
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Simulation Flow For Each Block You Want to Simulate . . .
Generate stimulus
Export Testbench
View Waveforms
Associate Stimulus
Invoke simulator
Compile and Run the simulation
Libero™ IDE
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Invoking WaveFormer Lite
Right Mouse Click!
or
Double Click!
Libero™ IDE
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WaveFormer Lite Features Allows Convenient Test Stimulus Specification via GUI User Specifies Stimulus by Drawing Waveforms Supports Copy / Paste / Append Operations
Significantly Reduces TestBench Creation Time Automatically Converts Graphical Stimulus Files into HDL
TestBenches Can Generate: VHDL Testbench (*.vhd) Verilog Testbench (*.v)
Users Can Annotate Waveform For Design Documentation
Libero™ IDE
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Drawing the Stimulus WaveFormer Lite Diagram Window Bus value controls Signal level controls
Zoom controls
Cursor location inputs
Libero™ IDE
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Creating Clocks Clock name
Double Click!
Clock frequency
Clock duty cycle
Start high or low Libero™ IDE
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Creating Clocks
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Drawing Signals State button toggles automatically Select “low” state button
Align courser and click! Use zoom controls to make viewing easier Libero™ IDE
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Drawing Signals Edge Placement
Enter time for edge placement
Libero™ IDE
Double click at end of signal
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Editing Signals
Libero™ IDE
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Drawing Busses Double click “VAL” state button
Double Click!
Libero™ IDE
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Editing Signals Appending and Inserting
Copy of waveform is inserted!
Libero™ IDE
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Copying to a Different Signal Signal Can Be Copied
Copy of waveform is inserted!
Libero™ IDE
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Reactive Test Bench: Stimulus and Expected Response Draw stimulus waveforms on the input ports of the model under test. Draw expected response waveforms on the output ports of the model under test
Libero™ IDE
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Reactive Test Bench: Samples Samples Verify MUT Output Sample constructs can monitor and perform actions based on the
data sampled Sample can work at a single point or over a windowed area Sample can perform relative to the beginning of the transaction or
relative to another event in the diagram.
Libero™ IDE
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Reactive Test Bench: Control & Looping Markers used for Control & Looping Sections of Transactions Specify the end of the transaction Create loops using for, while, and repeat loop markers Insert HDL code
Libero™ IDE
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Reactive Test Bench: Variables Variables Parameterize State Values Variables can drive values on stimulus waveforms Variables can store values on expected waveforms Waveform states can be expressed as conditional expressions
using variables
Libero™ IDE
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Reactive Test Bench: Delays Delays Parameterize Time Values Delays represent the time between two edges in the diagram Specify min and max values
Delay values can be time or cycle-based Conditionally control when edges occur
Libero™ IDE
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60
Reactive Test Bench: Help Resources Online Manual: Under the Help menu choose Reactive Test Bench Generation to open the help PDF Manual: Under the SynaptiCAD install directory there is a subdirectory called Help with Reactive_test bench_Generation_Option.pdf SynaptiCAD’s website: www.syncad.com
Libero™ IDE
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Saving Stimulus Save Stimulus File > Save File Name May Contain Name of Top-level Module Stimulus Appears on Libero File Manager Tab
Libero™ IDE
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Generating the Testbench Select Export from WaveFormer Lite Menu WaveFormer Lite Has Many Export Options Recommendations VHDL Testbench - Select “VHDL with Top Level Testbench” Verilog Testbench - Select “Verilog with Top Level Testbench”
Libero™ IDE
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Waveform and Testbench
Stimulus and testbench appear on File Manager tab in Libero
stimulus testbench
Libero™ IDE
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ModelSim AE
Libero™ IDE
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ModelSim AE Same Functionality as ModelSim PE Windows 98, Win NT, Win 2000 or Win XP
Node-Locked VHDL or Verilog
Reduced Performance No Co-simulation (VHDL and Verilog) Capability Limited to Simulation of Actel’s Gate-level Libraries Supported through Actel
Libero™ IDE
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ModelSim User Interface
TCL/TK User Interface TCL Scripting Source Level Debug Debug Windows
Waveform Display
Data linked to cursor
Libero™ IDE
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ModelSim Windows There Are Nine Windows
Main, Structure, Source, Signals, Process, Variables, Dataflow, Wave, & List Windows
Additional Window Features
Drag & Drop HDL Items Can Be Dragged from Dataflow, List, Signals, Source,
Structure, Variables, and Wave Windows … … And Dropped into either List or Wave Window
Libero™ IDE
Automatic Window Updating
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ModelSim Main Window Menu Bar
Tool Bar (Break, Run, Cont, Step, and Step Over)
Design Hierarchy
Status Bar (current time,
TCL Interpreter
delta time step, environment)
Libero™ IDE
ModelSim> prompt before design is loaded. VSIM> prompt is displayed after design is loaded © 2005 Actel Corp.
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Structure Window Hierarchical View of Design Structure VHDL (Squares) – Package, Component Instantiation, Generate and Block Statements Verilog (Circles) – Module Instantiation, Named fork, Named begin, task, and function
Instantiation Label, entity/module, architecture
Becomes Current Region for Source and Signals Window, Updates Process and Variables Window
Libero™ IDE
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Signals Window Follows Structure Window Shows Names and Values of HDL Items in Current Region of
Structure Window
Items Can Be Sorted in Ascending, Descending or Declaration Order Hierarchy (+) Expandable VHDL Items - Signals Verilog Items - Nets, Register Variables Named Events
“Drag & Drop” Wave & List windows
Force Apply Stimulus Filter Signal Types (input,output etc) Find HDL Items
Libero™ IDE
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Source Window Selected from Structure Window
Color-coded Comments, Keywords, Strings, Numbers, Executable Lines, Identifiers, System Tasks, Text
Full Edit Capability
Save, Compile and Restart
Drag and Drop Describe Examine
Libero™ IDE
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Wave Window Multiple Cursors Drag & Drop
Virtuals Multiple Panes
Zooming
Simulation Control
Libero™ IDE
Item formatting
Cursor Measurements
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Creating Busses in Wave Window Scalar Signals Can Be Combined into Vectors
Libero™ IDE
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Saving Wave Data Signals Added to Wave Window Can Be Saved for Future Simulation Runs File > Save Format from Wave Window
Libero™ IDE
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Saving Wave Data (cont.) Enter File Name in Save Format Dialog Box Enter Name on Libero Simulation Tab to Include Signals in Future
Simulation Runs
Enter file name
Libero™ IDE
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Wave Log Files (Datasets) Wave window waveforms can be saved as a Wave Log File (.wlf) for importing into other simulations. File > Save Dataset in Wave window
Libero™ IDE
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Wave Log Files (cont.) Enter file name in Save Dataset dialog box
Enter name
Libero™ IDE
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Opening Datasets Any number of Datasets can be opened for viewing or comparing to the current simulation File > Open > Dataset (Main Window) File > Open Dataset (Wave Window)
Libero™ IDE
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Opening Datasets (cont.) Click to browse for dataset
Select file and click open
Libero™ IDE
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Opening Datasets (cont.) Open dataset is displayed on a new tab in the ModelSim Main Window workspace.
Tab for dataset “gold” Libero™ IDE
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Adding Datasets to Wave Window Dataset signals can be added to the Wave window Select appropriate tab in workspace then use Structure and Signals
windows Visually compare simulation results
Libero™ IDE
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Adding Datasets to Wave Window (cont.)
Signals from dataset “gold”
Libero™ IDE
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Managing Datasets Multiple Datasets can be managed with the Dataset browser View > Datasets from Main Window
Options: Open, Close, Make Active, Rename
Libero™ IDE
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Process Window View Active
Displays All Processes Scheduled to Run during Current Simulation Cycle
View In Region
Displays any Processes that Exist in Region Selected in Structure Window
Process State
Ready, Wait, Done
Window Update Show Region in Structure Window Points to Source Lines Shows Variables in Process Displays Process in Dataflow
Libero™ IDE
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Variables Window Lists Names of HDL Items in Current Process VHDL - Constants, Generics and Variables Verilog - Register Variables
Tree Hierarchy - (+) Expandable, (-) Expanded Sort Ascending, Descending Declaration Order
Change Value of Selected HDL Item Find
Forward or Reverse Search
Drag & Drop
Libero™ IDE
Wave or List Windows or Log File
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DataFlow Window Explore physical connectivity of design Displays processes, signals,
nets and registers
Links to Main, Process,
Signals, Wave and Source windows
Find feature allows searching for signal, net or register names
Libero™ IDE
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Dataflow Window ModelSim AE Simulator The ModelSim AE simulator has a limited Dataflow functionality Only one process and it’s attached signals or one signal and it’s
attached processes are displayed Display net drivers or readers
Libero™ IDE
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Zoom control
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List Window Simulation Results in Tabular Format VHDL - Signals and Process Variables Verilog - Nets and Registers
“Drag & Drop” Find Function Trigger / Strobe Properties Write List
Tabular Event TSSI
Markers - Add, Delete or Goto
Libero™ IDE
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Saving Tabular Output
Drag & Drop!
Libero™ IDE
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Advancing Simulation Time Three Methods At VSIM prompt: VSIM 12> run 100 ms In Main Window Tool Bar:
Restart
Run
Run Length
Run -all
Step
Continue Run
Break
Step Over
In Wave Window Tool Bar:
Run
Run -all
Continue Run Libero™ IDE
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Re-running Simulation Restart to Zero Force Restart at VSIM Prompt VSIM 12> restart –f
In Main Window Run > Restart or Restart Button Displays Restart Dialog
Keep Current
Libero™ IDE
Listed Signals Waved Signals Breakpoints Logged Signals Virtual Signals
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ModelSim Macro Files ModelSim Commands Can Be Saved in Macro File The ‘do’ Command Executes Commands Macro File Can Have any Name and Extension
Syntax: do [<parameter_value>]
Example: do run.do This Command Executes File run.do
vlib presynth vmap presynth ./presynth vcom -93 -work presynth D:/Actelprj/count32/hdl/count32.vhd vcom -93 -work presynth D:/Actelprj/count32/stimulus/count32.vhd vsim presynth.testbench add wave /testbench/* run 1000ns Libero™ IDE
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Libero Simulation Options Simulation Options Can Be Set from Simulation Tab under Options Results Saved in run.do File
Specify simulation run time
Use Automatic Do File allows Libero to automatically set up the simulation for the user Include Do file allows Libero to include user-defined script. User can enter name of script file Select min, typ, max simulation conditions for post-layout simulation Default resolution based on family choice 1ps for 500K, APA, 54SXA, AX 1ns for all other families Libero™ IDE
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Invoking ModelSim Pre- or Post-Synthesis
Click “Simulation” Design Flow Window or …
Right Mouse Click!
Double Click!
Libero™ IDE
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Associating Stimulus Right Mouse Click!
Libero™ IDE
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Hierarchical Testbench Support Libero Allows Users to Specify List of Stimulus Files for Simulation No Stimulus File Selected by Default Libero Remembers Stimulus Association for Any Block
Libero™ IDE
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Pre-Synthesis Simulation ModelSim Automatically Compiles Design and Runs Simulation for 1 µS (External) Signals from
Testbench Automatically Added to Wave Window Additional (Internal) Signals Can Be Added by User
Libero™ IDE
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Libero Simulation files on HDD
Libero™ IDE
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Simulating Designs Summary Capture Design Generate RTL Netlist (VHDL or Verilog)
OR Create Schematic May Include RTL blocks Structural VHDL or Verilog Netlist Automatically
Created before Simulation
Create Testbench Use WaveFormer Lite, or Text Editor
Associate Stimulus Run Pre-Synthesis Simulation
Libero™ IDE
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Synthesis
Design Capture
Simulation
Synthesis
Post-Synthesis Simulation
Place & Route
Post-P&R Simulation
Libero™ IDE
Programming
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Invoking Synplicity Click “Synthesis” in Design Flow Window or ..
Right Mouse Click!
or Double Click!
Libero™ IDE
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Synplify Interface Add constraint files or VHDL packages
Libero automatically lists files lowest levels first, top last
Change target and result file
Libero™ IDE
Global synthesis constraints
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Result File Synplicity Produces an EDIF Netlist <design>.edn
Libero Automatically Produces Structural VHDL or Verilog Netlist <design>.vhd or <design>.v Results Appear on File Manager Tab under Synthesis Files
Libero™ IDE
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Setting the Target Options High fanout = slow, small designs Low fanout = fast, large designs Use defaults for first pass
By default, Synplify will insert Actel I/O macros on all the HDL I/O ports. When synthesizing lower-level blocks, this must be disabled.
Libero™ IDE
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Global Constraints Frequency Symbolic FSM Compiler Configure HDL Compiler Resource Sharing
Libero™ IDE
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Frequency Global clock frequency 0MHz means optimize for area
Libero™ IDE
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Symbolic FSM Compiler
When checked, it selects proper encoding for all state machines.
Encoding method can be set on individual state machines with syn_encoding directive in the HDL code
Libero™ IDE
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State Machine Encoding (VHDL) Options > Configure VHDL Compiler Sets the default encoding style for enumerated types Override encoding style on an individual basis using syn_encoding directive in constraint editor or the HDL source code # of states default encoding 1-4 sequential 5 - 24 one-hot > 24 gray
Libero™ IDE
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Resource Sharing When enabled, Synplify performs automatic sharing of operator resources, including adders, subtractors, incrementers, and decrementers.
if if (s (s == ‘0’) ‘0’) then then YY <= <= AA ++ B; B; else else YY <= <= CC ++ D; D; end end if; if; S
S
A
A
+ C
B Y C
+
+ D
D
Without resource sharing Libero™ IDE
Y
B
With resource sharing © 2005 Actel Corp.
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Performing Synthesis
Compile only or check syntax
Libero™ IDE
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View Log Synplify Log contains Plenty of Valuable Information:! Warnings and Errors Double-click and Jump to Code! Fanout Limit Extraction Information
Libero™ IDE
© 2005 Actel Corp.
(Found Counter, FSM, Adder, etc.) Net Loading Logic Buffering and Replication Information Resource Usage Critical Path Timing Analysis
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Reading the Log File: Errors
Double Click!
Libero™ IDE
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Constraint Editor Synplify facilitates constraint entry with a spreadsheetlike constraint editor. File->New Select Constraint File (Spreadsheet) Select Files of type Constraint Files
Press OK Extremely easy to use
Libero™ IDE
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Constraint Editor (Cont.) Constraint Editor supports a Drag and Drop interface. There are sheets for entering: Clock Frequency or Period Clock to Clock timing Input/Output Constraints Registers Constraints Multi-Cycle Paths False Paths Attributes
Libero™ IDE
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Synplicity Directives and Attributes
88
Synplicity Directives and Attributes Let You Direct Analysis, Optimization, and Mapping of Design during Synthesis Attributes Control Mapping Optimizations Attributes Can Be Entered in either .sdc Constraint File or HDL
Source Code Synplify Supports Limited Number of Attributes that Can Be Entered in
Attribute Pane Most Attributes Are Entered in your VHDL or Verilog Code
Directives Control Compiler Optimizations Directives Must Be Entered in HDL Source Code
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Actel Attribute and Directive Summary NAME
Type VALUE
alspreserve
A
syn_encoding
A
DESCRIPTION
Boolean sequential,
Prevents a net from being removed during Place and Route
onehot, gray, safe
Specifies the encoding style for state machines.
1/0
Controls the handling of hierarchy boundaries of a module
syn_hier
A
true/false 1/0
or component during optimization and mapping. Prevents the internal signal from being removed during
syn_keep
D
true/false
synthesis and optimization.
syn_maxfan
A
integer 1/0
Controls the maximum fanout of an instance, net, or port.
syn_noclkbuf
A
true/false 1/0
Turns off the automatic insertion of clock buffers. Prevents sequential optimization such as constant
syn_preserve
D
true/false
propagation, inverter push-through and FSM extraction. Specifies register design technique to apply to a module, architecture or register
syn_radhard level
A
syn_replicate
A
string 1/0 1/0
syn_sharing
D
true/false
Libero™ IDE
Disable register replication Enables/disables the resource sharing of operators inside a module during synthesis.
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alspreserve Actel-Specific Attribute Keeps Net from Being Collapsed in Designer (Back-end) Tools Must also Add syn_keep to Ensure Synplicity Retains Net Synplicity Adds alspreserve Attribute to EDIF Netlist
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alspreserve Syntax Verilog Syntax object /* synthesis alspreserve = 1 */ ; Example: module foo ( in, out); input [6:0] in; output out; wire out; wire or_out1 /* synthesis syn_keep=1 alspreserve=1 */; wire and_out1; wire and_out2; wire and_out3 /* synthesis syn_keep=1 alspreserve=1 */;
VHDL Syntax attribute alspreserve of object : signal is true ; Example: architecture comb of foo is signal and_out1, and_out2, and_out3, or_out1 : std_logic; attribute attribute attribute attribute attribute Libero™ IDE
syn_keep of and_out3 : signal is true; syn_keep of or_out1 : signal is true; alspreserve: boolean; alspreserve of and_out3 :signal is true; alspreserve of or_out1 : signal is true; © 2005 Actel Corp.
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90
syn_radhardlevel Example (cont.) SCOPE attribute tab:
Source files:
use C-module flip-flop for qA
Add to infer C-module flip-flops
Libero™ IDE
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syn_encoding Attribute Sets Encoding Style for State Machines Overrides Default Style
Default Style - Compiler Selects Encoding Style Based on Number of States as Follows: 1 - 4 States: 5 - 24 States: > 24 States:
Sequential One-hot Gray
syn_encoding Can Have the Following Values: onehot gray sequential safe
Libero™ IDE
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syn_maxfan Attribute Controls Maximum Fanout of Instance, Net, or Port Limit Specified by this Attribute May Be Treated as Hard or Soft Depending on Where It Was Specified Soft Limit May Not Be Honored if it Degrades Performance
You Can Apply syn_maxfan Attribute to Module, Register, Instance, Port, or Net For ProASIC and APA Designs Only – You Can also Apply to Module
or Entity
Libero™ IDE
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syn_maxfan Usage SCOPE Constraint Editor Usage
SDC File Syntax define_attribute { object } syn_maxfan { integer } Example – Limit Fanout for Signal clk to 200:
. . . define_attribute {clk} syn_maxfan {200}
. . . Libero™ IDE
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syn_maxfan Syntax
Verilog Syntax object /* synthesis syn_maxfan = "value" */ ; Example: module test (registered_data_out, clock, data_in); output [31:0] registered_data_out;
input clock;
input [31:0] data_in /* synthesis syn_maxfan=1000 */; reg [31:0] registered_data_out /* synthesis syn_maxfan=1000 */; // Other code
VHDL Syntax
attribute syn_maxfan of object : object_type is "value" ; Example: entity test is port(clock : in bit; data_in : in bit_vector(31 downto 0); registered_data_out: out bit_vector(31 downto 0)) attribute syn_maxfan : integer; attribute syn_maxfan of data_in : signal is 1000; -- Other code Libero™ IDE
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syn_replicate Attribute Prevents Replication of Register assign syn_replicate = 0 Turns Off Register Replication Cannot Force Tool to Replicate Works along with max_fanout Value Only Supported on Individual Register
When Will Synplify Replicate or Buffer? Generally Flip-flops Are Replicated to Achieve Fan-out Control For Combinatorial Cells, Buffers Are Added
Libero™ IDE
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syn_replicate Usage SCOPE Constraint Editor Usage
SDC File Syntax define_global_attribute syn_replicate 1=enables { 1 replication | 0 } Example - Disables All Replication in Design:
0 disables replication
. . . define_global_attribute syn_replicate {0}
. . . Libero™ IDE
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syn_replicate Usage (cont.) Verilog Syntax
1 enables replication
disables replication object /* synthesis syn_replicate = 1 | 0 0*/;
Example: module norep (Reset, Clk, Drive, OK, ADPad, IPad, ADOut);
. . . reg [31:0] IPad; reg DriveA /* synthesis syn_replicate = 0 */; assign ADPad = DriveA ? ADOut : 32'bz; always @(posedge Clk or negedge Reset) if (!Reset) begin DriveA <= 0; IPad else
<= 0;
end
begin
DriveA <= Drive & OK; IPad
<= ADPad;
end
endmodule Libero™ IDE
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syn_replicate Usage (cont.) VHDL Syntax attribute syn_replicate of object : object_type is true | false ; Example: entity norep is port ( Reset : in std_logic; Clk : in std_logic; Drive : in std_logic; OK : in std_logic; ADPad : inout std_logic_vector (31 downto 0); IPad : out std_logic_vector (31 downto 0); ADOut : in std_logic_vector (31 downto 0)); end norep; architecture archnorep of norep is signal DriveA : std_logic; attribute syn_replicate : boolean; attribute syn_replicate of DriveA : signal is false; begin -- Other code
Libero™ IDE
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syn_sharing Directive Enables/Disables Resource Sharing of Operators inside Module during Synthesis By Default, Directive Is Enabled (Value 1 for Verilog, true for
VHDL). If Resource Sharing Check Box in Project View is Disabled, You Can Still Enable Resource Sharing Using syn_sharing Directive
Libero™ IDE
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syn_sharing Usage Verilog Syntax object /* synthesis syn_sharing = 1 | 0 */ ;
Example: module my_design(out,in,clk_in) /* synthesis syn_sharing=0 */; // Other code
VHDL Syntax attribute syn_sharing of object : object_type is " true | false";
object can be architecture name Example: entity alu is port ( a, b : in std_logic_vector (7 downto 0); . . . ); end alu; architecture behave of alu is -- Turn on resource sharing for the architecture. attribute syn_sharing of behave : architecture is "true"; begin -- Other code Libero™ IDE
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Retiming Synplify Pro Retiming Is Feature in Synplify Pro ver 7.5.1 Helps Improve Performance of Sequential Circuits Moves Registers across Combinatorial Gates Also Called Register Balancing
Global Option – Can Be Turned On/Off in GUI Cannot Have this Option on per-Block Basis because it Optimizes Whole
Design
Advantages Improves Design Performance
Synplify 7.5.1 Pro GUI
No Need to Modify RTL Code # of Register Cycles Remains the Same
Impact May Result in Higher Utilization May Increase Difficulty in Routing Some Designs May Degrade in Performance!
Libero™ IDE
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Retiming (cont.) Retiming Moves Registers across Design to Achieve the Best Possible fmax Before Retiming Reg
15ns
Reg
5ns
Reg
Performance: 67MHz Limited by 15ns
Reg
8ns
Reg
Performance: 83MHz Limited by 12ns
After Retiming
Reg
Libero™ IDE
12ns
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Synplify and Synplify PRO for Actel Synplify for Actel Is Equivalent to Synplicity's Synplify Product. Limited to Actel Products Only Does Not include RAM Inferencing
Included in All Libero Products Synplify Pro AE has additional features beyond Synplify AE and requires a separate license from Actel Limited to Actel products only
Libero™ IDE
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Synplify® for Actel and Synplify Pro® Features Comparison
Libero™ IDE
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Synplicity Help Synplicity Has Complete On-line Manual Invoked from Help Pulldown or
by Pressing F1
Libero™ IDE
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Post-Synthesis Simulation
Design Capture
Simulation
Synthesis
Post-Synthesis Simulation
Place & Route
Post-P&R Simulation
Libero™ IDE
Programming
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Post-Synthesis Simulation Steps: Synthesize Design with Synplicity Generate EDIF Netlist from Synplicity Libero Automatically Creates Structural VHDL or Verilog Netlist
Run Post-synthesis Simulation on Structural Netlist
Libero™ IDE
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Post-Synthesis Simulation Click on “Simulation” in Design Flow window or…
Right Mouse Click!
or Double Click!
Libero™ IDE
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Post-Synthesis Simulation ModelSim automatically compiles structural netlist exported from Designer Runs simulation for 1 uS Structural library mapping
handled by Libero Pre-compiled libraries do not require compiling prior to simulation
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Place and Route
Design Capture
Simulation
Synthesis
Post-Synthesis Simulation
Place & Route
Post-P&R Simulation
Libero™ IDE
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Programming
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Open Design for Place & Route Click on “Place & Route” in Design Flow Window or… Right Mouse Click!
or Double Click!
Libero™ IDE
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Designer Interface
Designer Provides Graphical Flow Manager to Lead Designer through Design Flow Completed Tasks Highlighted Design Flow Steps Listed at Top User Tools Grouped Below
Designer Error Manager Tabs (same as Libero) Libero™ IDE
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Designer TCL Script Support Industry-standard Language Tool Command Language
Launch Multiple Tools from Single Script Launch Multiple Design Runs
Synthesis
TCL script
Designer
Simulator
Libero™ IDE
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Running Scripts within Designer In File Menu, Click Execute Script File Displays Execute Script Dialog Box
Enter name of script file Enter arguments to be passed to script file
Click Run to execute script
Tcl Scripts can be Executed from the Command Line: Example: d:\Libero\Designer\bin\designer script:my_script
Libero™ IDE
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Recording Scripts Designer Can Export Tcl Script File that Contains Commands Executed in Current Session Exported Tcl Script can be used to … … re-Execute Same Commands Interactively or in Batch … Become More Familiar with Tcl Syntax
Libero™ IDE
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Importing Source Files Multiple files can be imported at the same time Netlist import is done automatically by Libero
Import File types: File Type EDIF Verilog VHDL Actel ADL Netlist Criticality ProASIC Constraint File Physical Design Constraint File
Libero™ IDE
© 2005 Actel Corp.
Extension *.ed* *.v *.vhd *.adl *.crt *.gcf *.pdc
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Importing Auxiliary Files Optional step to import pin files, timing constraints, etc. Import Auxiliary files after compile completes Import File types: File Type Criticality PIN SDC Physical Design Constraint Value Change Dump Switching Activity Intermediate File/Format Design Constraint File
Libero™ IDE
© 2005 Actel Corp.
Extension *.crt *.pin *.sdc *.pdc *.vcd
*.saif *.dcf
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104
Entering Constraints in Designer Option 1 - Import Files in Designer Source or Auxiliary Files
Option 2 - Import Files in TCL Script Option 3 - Set All Constraints Directly in Designer Physical - PinEdit Timing - Timer
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Constraint File Types Physical Pin Locations SX-A, SX-S - .pin File APA - .gcf File Axcelerator - .pdc File
All I/O Attributes Axcelerator - .pdc File
Timing All Constraints APA - .sdc File Antifuse – .sdc File
Libero™ IDE
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Designer File Auditing Designer Audits Source Files to Ensure Imported Files Are Current All Imported Source Files Are Date-
and Time-stamped Designer Notifies You if File Is Changed
Audit Settings Can Be Changed (File > Audit Settings) Enable / Disable Auditing
Move File to New Location
Associate File with Current Date
and Time
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Importing Files into Designer Summary Import the Following Source Files EDIF, VHDL, Verilog Netlists PDC, SDC, and GCF Files Source Files Are Audited per User Settings
Import the Following Auxiliary Files DCF, SDC, PDC, VCD, and SAIF Files
Libero™ IDE
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106
Designer Compile Reads Netlist Compiles Design into Actel Database (ADB) File Runs Combiner Performs Design Rule Checking Checks for Netlist Errors (Bad Connections and Fanout Problems) Removes Unused Logic (gobble) Verifies that Design fits into Selected Device
Libero™ IDE
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Compile Wizard Select: Die Package Speed Grade Die Voltage
Select Restrict Pin Usage Reserve JTAG Pins Reserve ActionProbe Pins
Select Ambient Temperature Commercial (0 - 70ºC) Industrial (-45 - 85ºC) Military (-55 - 125ºC) Custom
Select Voltage Range Libero™ IDE
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107
Radiation Derating Radiation Derating for SX-S Users Can Now Add Radiation
Exposure Level in Device Selection Wizard for Radiation Derated Timing
Libero™ IDE
© 2005 Actel Corp.
July, 2005
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Flash Netlist Optimization
108
Netlist Optimization Constraints Flash Designs Attempts to Remove All Cells from Netlist that Have No Effect on Circuit’s Functional Behavior Reduces Overall Size of Design Produces Faster Place and Route Times Takes Advantage of Inverted Inputs of Logic Tiles
By Default All Optimizations Are Performed on Netlist Original Netlist Preserved Removed Cells Back-annotated with 0ns Delay in Timer
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dont_optimize Flash Designs Turns Off All Netlist Optimizations When Followed by One or More Netlist Optimization Options, this Statement Turns off Named Option(s). Syntax dont_optimize {inverter buffer clocktree resettree const dangling};
Example: dont_optimize buffer inverter;
Libero™ IDE
© 2005 Actel Corp.
Disables buffer and inverter optimization
109
optimize Flash Designs Turns On All Netlist Optimizations When Followed by One or More Netlist Optimization Options, this Statement Turns On Named Optimization Option(s) Syntax optimize {inverter buffer clocktree resettree const dangling};
Example: optimize buffer inverter;
Libero™ IDE
Enables buffer and inverter optimization
© 2005 Actel Corp.
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Netlist Optimization Constraints Options buffer - Removes All Buffers Provided Maximum Fanout Not
Exceeded inverter - Removes All Inverters Provided Maximum Fanout Not Exceeded clocktree - Removes All Inverters and Buffers in Nets Connected to Clock Inputs on All Flip-Flop Cell Types resettree - Removes All Inverters and Buffers in Nets Connected to Reset Inputs on All Flip-Flop Cell Types const - Replaces All Logical Elements with One or More Constant Inputs (Connected to Logical “1” or “0”) by Simplified Logic Function If Replacement Logic Function Is Inverter or Buffer, that Element Is
Removed
dangling - Recursively Removes All Cells Driving Unconnected Nets
Libero™ IDE
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110
set_max_fanout May Retain Buffers and Inverters in Netlist Removes All Buffers and Inverters whose Elimination Does Not
Exceed Specified Fanout
Use this Constraint if Design Has High-Fanout Net in Critical Paths Syntax set_max_fanout; Global Command
set_max_fanout Net_name; Single Net or Set of Nets (*)
set_max_fanout Block_name; All Nets of Block Block_name
Libero™ IDE
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dont_touch Selectively Disables Optimization of Named Hierarchical Instances Wildcard (*) Isolates All Sub-Blocks Under Named Block Syntax dont_touch hier_net_name [, hier_net_name];
Example optimize buffer inverter; dont_touch /U1/myblock/*;
Enables Only Buffer and Inverter Optimization Types. Optimizes All Instances except those Contained in Block /U1/myblock. Libero™ IDE
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Import Log Flash Designs Import Log Written after Compile Step in Designer Created under.dtf directory
What it Reveals Promoted Globals Distribution of Fanout Device Utilization (RAMs, PLLs, IOs, Global Routes, Logic) Internal and External Nets (Min, Average and Max fanout) High Fanout Net Candidates to be Mapped to Spines Internal Clocks
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Designer Import Log Flash Designs . . . Compile Output: NOTE [removed_pwr_gnd_cells]: Removed 2 power/ground cells from the design.
Removed cells
Optimizing Netlist.
Promoting nets to globals.
Following nets are possible candidates for Globals/Spines : Fanout
Type
Driver
Name
48
CLK_NET
CLK_pad/MUXTILE
CLK_c
48
SET/RESET_NET
RESET_pad/MUXTILE
RESET_c
Following nets are assigned to global resources: Fanout
Name
48
CLK_c
48
RESET_c
Nets assigned to global resources
. . . Libero™ IDE
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Designer Import Log (cont.) . . . I/O
Cells:
Core cells: | Instances |
Input. IOs: Bidir
2
IOs:
0
Output IOs:
16
Global IOs:
2
Internal Global:
0
IOs:
Tiles
Logic
|
81
|
185 |
81
Storage
|
48
|
384 |
48
RAM/FIFO
|
0
|
0 |
0
|
|
|
----------------------Total
Gates |
----------|-----------|--------|-------
----------|-----------|--------|-------
20
Total
|
129
|
569 |
129
Actual number of tiles used Nets
| Count
| Average Fanout | Max. Fanout
---------------|--------|----------------|-----------Global
|
2
|
48.0
|
48
External
|
18
|
2.9
|
20
Internal
|
113
|
1.9
|
16
Net statistics
---------------|--------|----------------|-----------Total
|
133
|
2.7
|
48
. . . Libero™ IDE
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Identifying Removed Cells Flash Designs While Compile or Layout Is Running, Temporary File Named deleted_blocks Is Created under.dtf Directory Lists All Deleted Cells This File Automatically Removed after Layout Is Finished Save File before Layout Completes or Run Place Option without Route
Libero™ IDE
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113
Netlist Optimization Example Flash Designs -- example to test APA optimization library ieee; use ieee.std_logic_1164.all; entity test is port (A, B, presetn, resetn, clk: in std_logic; out1, out2, Q1, Q2: out std_logic); end test; architecture RTL of test is begin process (clk, resetn) begin if (resetn = '0') then Q1 <= '0'; elsif (clk 'event and clk = '0') then end if; end process;
Q1 <= A;
process (clk, resetn, presetn) begin if (resetn = '0') then Q2 <= '0'; elsif (presetn = '0') then Q2 <= '1'; elsif (clk 'event and clk = '0') then Q2 <= B; end if; end process;
Deleted blocks
out1 <= A and not B; out2 <= not A xor not B; end RTL;
Libero™ IDE
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Successful Compile Compile Button Turns Green if Compile Completes Successfully Errors Indicated in
Designer Log Window
Libero™ IDE
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114
MultiView Navigator
MultiView Navigator MultiView Navigator Includes the Following Tools: PinEditor, I/O Attribute Editor, NetlistViewer, and ChipPlanner
Allows Cross-probing Among Different Designer Tools
Libero™ IDE
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MultiView Navigator Zoom Controls
Toolbar Icons
Design Window
Working Area
Log Window
World View Window Libero™ IDE
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MultiView Navigator Windows Design Window View Design as Logical Blocks, Physical Elements, Ports, Nets, and
Regions
World View Window Shows Position of Current Viewing Window Relative to Chip
Working Area Shows Current Active Tools Tile or Cascade Active Tools
Log Window Keeps Running Log of Activity Output – Shows All Messages Errors – Shows Error Messages Warnings – Shows Warning Messages Info – Shows Informational Messages Find Window – Keeps Result of Find Function for Later Usage
Libero™ IDE
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MultiView Navigator Features Message Bar Hierarchical Error / Info Message Display Summary Line Shown in New Message Bar Expands on Demand to Show More Details Copy / Clear Messages Most Messages Transitory (Removes Clutter) Reduced Number of Tabs (Removes Clutter)
Ongoing Effort to Improve Message Content
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MultiView Navigator Toolbar File -> Commit – Writes any Changes Made in Editors to Design Prelayout Check – Verifies Placement Changes in Editors Are
Legal
Edit -> Undo/Redo – Allows User to Undo a Mistake or Redo an
Accidental Undo
Find – Enables Find Interface
Zoom Controls Zoom Region, Zoom In, Zoom Out, Zoom to Fit
Assignment Options Place, Unplace, Lock (Fix), Unlock (Unfix)
Tools Menu ChipPlanner, PinEditor, NetlistViewer, I/O Attribute Editor
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MultiView Navigator Prelayout Checker Infeasible Constraints Identified pre-Layout Automatically Runs when You Commit from MVN Users Can Run Using MVN Command Tools->DRC
Enhanced Checks Overlapping Region Checks Resource Overbooking I/O Technology Checks
Libero™ IDE
© 2005 Actel Corp.
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235
MultiView Navigator Find / Search Search for Instances, Nets or Ports Wildcard (*) Matching Advanced Options - Choice of Log Window Pane for Search Results
Cross-probing from Find Tab to the other Four Windows
Libero™ IDE
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PinEditor
Pin Assignment Options I/O Locations Can Be Assigned as Follows: Automatically by Designer Software during Layout By Importing: . Gatefield Constraint File (.gcf) (ProASIC and ProASICPLUS)
Manually using PinEdit Tool in Designer Pin Assignments May Be Exported for Later Use
Libero™ IDE
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119
MultiView Navigator PinEditor Graphical Pin Location Editor Drag and Drop Placement of Pins Fix Pin Locations for Subsequent Place and Route Runs
Flip Display Enables Assignments as if Looking from Top or Bottom of Chip
Pinout Can Be Printed for Documentation
Libero™ IDE
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I/O Features Axcelerator I/O Bank Configuration Select Bank Select I/O Standards Incompatible Options
Disappear when Selecting I/O Standards Select Low-power Mode Select Input Delay
Libero™ IDE
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VREF Pins Axcelerator Assigning VREF Pins
Libero™ IDE
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Pin Assignment Recommendations Enter Design as Completely as Possible Don’t Worry about Functionality
Compile (Ignore Warnings) and Layout “Fix”All Pin Assignments Edit > Select All then Edit > Fix
Send Pin Report to PCB Layout Continue Working Out Bugs Future Layouts Will Honor “Fixed” Assignments
Libero™ IDE
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Exporting Pin Report Pin Report Can be Exported from Designer
Libero™ IDE
© 2005 Actel Corp.
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Exporting Pin Constraint File Pin Constraint File Can be Exported from Designer
File Type
PIN file Gatefield Constraint file Physical Design Constraint Libero™ IDE
© 2005 Actel Corp.
File Extension Family ACT1, ACT2, ACT3, MX, XL, DX, SX, SX-A, eX *.pin ProASIC, *.gcf ProASIC PLUS *.pdc Axcelerator July, 2005
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I/O Attribute Editor
MultiView Navigator I/O Attribute Editor Input/Output Attribute Editor Select (Varies by Family): I/O Standard I/O Threshold Slew Rate I/O Power-up State
Enter Load Capacitance Does Not Change SDF File
Generation
Spreadsheet-like Sort, Copy, Paste
Libero™ IDE
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123
MultiView Navigator I/O Attribute Editor (cont.)
Double click on column to sort display by that column
Hold down CTRL key to select multiple rows
With multiple rows selected, changing the value of a drop-down item with CTRL key pressed will change the value for all rows Libero™ IDE
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Netlist Viewer
124
MultiView Navigator Netlist Viewer Displays Netlist in Hierarchical Manner, Providing Logical View of Design Netlist Viewer Can Explore each Level of Hierarchy and Trace Signals
Open Netlist Viewer Libero™ IDE
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MultiView Navigator Netlist Viewer (cont.)
Schematic View Window – displays a graphical representation of the netlist
Search Window – shows results of searches
Libero™ IDE
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125
MultiView Navigator Netlist Viewer (cont.) Viewing Options Push, Pop, Jump to Top Go to First Page, Go to Last Page, Go to Next Page, Go to Last
Page Right-click on Net to Follow Net to Other Pages or Net Driver
Highlight, Highlight Append, un-Highlight, un-Highlight All Allows Page Splitting Allows User to Decide if All Elements on that Level Are Shown as
Single Page
Libero™ IDE
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MultiView Navigator Netlist Viewer View pre- and post-Optimized Netlists Pre-optimized Netlist Is Original Hierarchical Netlist Post-optimized Netlist is Flattened Reflects what other Tools Use (ChipEdit, PinEdit)
Libero™ IDE
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126
ChipPlanner
ChipPlanner Editing and Floorplanning ChipPlanner Capabilities: Editing Place, Unplace, or Move Logic and I/O View Macro Placements Made during Layout View Net Connections with Ratsnest or Route View View Architectural Boundaries View and Edit Silicon Features, such as I/O Banks View Placement and Routing of Paths when Used with Timer
Floorplanning Create and Assign Logic or Nets to Regions
Cross-probe with Silicon Explorer to Select Probes
Libero™ IDE
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127
ChipPlanner Terminology Region Defined sub-Portion of Die Shapes - Rectangular or Rectilinear (Union of Rectangles) Types: Empty - No Logic Can Be Put into this Region Inclusive - Assigned Logic Must Be Put into this Region Other Unassigned Logic Can Be Added to this Region by Layout
Exclusive - Only Assigned Logic Can Be Put into this Region Not Supported for APA or A500K
Assign Place Logic into Particular Region or Location
Lock Finalizes Allocation of Logic in Particular Location
Libero™ IDE
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ChipPlanner Editing and Floorplanning Drag Logic or I/O to Desired Location ChipPlanner Floorplanning Functions Create local clock region
Create Logic Region Create Empty Region
Create empty region
Delete region
Select Region Move Region
Assign / Unassign
Delete Region Resize Region
Create inclusive region
Assign/Unassign Logic to Region
Create exclusive region
Regions Can Span Logic, Memory Cells and I/O
Libero™ IDE
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128
ChipPlanner Empty Region Region > Create Empty No Logic Assigned to Empty Regions
Libero™ IDE
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ChipPlanner Inclusive Region Region > Create Inclusive Assigned Logic Put in Inclusive Region Other Logic May also Be Put in this Region
Libero™ IDE
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ChipPlanner Exclusive Region (Axcelerator) Region > Create Exclusive Only assigned logic placed in exclusive region
Libero™ IDE
© 2005 Actel Corp.
July, 2005
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ChipPlanner Local Clock Region (Flash) Region > Create Local Clock Assign net to a spine region graphically All logic connected with the net will be assigned to the spine region
Libero™ IDE
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130
ChipPLanner Region Color Control Individual Region Color Control Regions Have Different Default Colors Based on Types Can Change Each Region’s Default Color Region Colors Saved in .adb File Region Colors Reset to Defaults upon Recompile
Libero™ IDE
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ChipPlanner Region Properties Region > Properties Indicates:
Change region color
Region Type Region Width, Height and Origin Region Usage
Shows Region Default Color Default Color Can be Changed
Also Provides Access to Assignment Window
Region size and utilization
Libero™ IDE
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MultiView Navigator Region Color Control Example
Libero™ IDE
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ChipPlanner Logic Assignment Two Logic Assignment Methods Assignment Window (Region > Assign/Unassign Logic…) Provides Search and Selection Capability Also Available from Region Properties Dialog Box
Drag and Drop Logic into Region
Checkmark Indicates Assigned Logic
Libero™ IDE
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ChipPlanner Display Settings Users Can Show/Hide Object and Assign Color to Resource View > Display Settings
Libero™ IDE
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ChipPlanner Viewing Nets Select Net View Options from Nets Toolbar: Display No Nets Show nets
Display Input Nets
Hide nets
Show routes
Display Output Nets Display Input and Output Nets Display Ratsnest
Show inputs only Show Ratsnest Show outputs only
Display Routes Routes Option for APA and A500K Only
View Ratsnest Libero™ IDE
View Routes © 2005 Actel Corp.
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133
ChipPlanner Highlighting Nets Selected Nets Can Be Highlighted to Aid Analysis Select Net from Design Window Nets Tab or Search
Results Change Highlight Color from Toolbar or Edit Menu
Highlight Color Highlight Unhighlight All
Libero™ IDE
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ChipPlanner
ProASIC/ProASICPLUS Floorplanning Capabilities Define Rectangular Regions x/y Location Displayed During Region Resize Only Empty and Inclusive Regions Supported for APA and A500K
Assign Logic, Regular I/O and Regular Nets to Region Drag and Drop Assignments Selection Highlighting and Color Selection
Create Local Clock Region Multi-region Assignments Not Recommended Assigning Same Macro to Two Overlapping Regions is Legal However … NO Check to Ensure that Regions Overlap Layout May Fail
I/O Assignments View Spines Created through GCF View Routing Libero™ IDE
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Silicon Support
ProASIC/ProASICPLUS Multi-type Region Support Region Support for RAM LocalClock Regions Can Include RAM and I/O Controlled by Compile Option (Designer -> Options -> Compile) Need to Recompile after Modifying Option Default is ON for New Designs from Designer 6.0 on
Top1
RAM block
Top2
Top3 …
1) Core + memory 2) Core + memory + I/O i/o
spine core
i/o i/o i/o i/o i/o Libero™ IDE
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ChipPlanner Axcelerator Floorplanning Capabilities Define Rectangular Regions Empty, Exclusive and Inclusive Region Support for Axcelerator Modify Region types (Inclusive / Exclusive)
Assign Logic and Nets to Region I/O Assignments PLL and RAM
Assignments Drag and Drop
Assignments Multi-region Assignments NOT Recommended
Libero™ IDE
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Silicon Support Axcelerator LocalClock Region Support Created through PDC only PDC Syntax assign_local_clock –type routing_resource_type –net netname
[local_clock_region] [local_clock_region] … routing_resource_type is either hclk or rclk local_clock_region is Hierarchical Resource Name of Specific Clock Region Tile3b.colN-1 Tile 3A
3
Tile3C.Row0
2 Tile1C.RowN-1
1 A Libero™ IDE
B
C
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ChipPlanner Scripting Support ProASIC/ProASICPLUS Existing GCF Format and Capabilities GCF Enhancement to Support Partial I/O Regions
Axcelerator PDC Commands for Floorplanning Define and un-Define Region Rectangular Rectilinear (Currently Only Supported in PDC)
Region Types Empty Inclusive Exclusive (Axcelerator Only)
Assign and Unassign Resources Macros Nets
Reset Floorplan
Libero™ IDE
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MultiView Navigator LogicalCone Helps View Critical Portions of Netlist Identify Critical Paths using Timer Add this Logic to LogicalCone Incrementally Add / Remove Logic from Cone CrossProbe from / to LogicalCone All NetlistView Features available in LogicalCone New LogicalCone Tab in Hierarchy Window New LogicalCone Menu Accessible from NetlistViewer Can Simultaneously Create Multiple Cones Set of Macros Can Be Highlighted, then Added to Cone LogicalCone Data No Longer Valid after Recompile Applies to All Families Supported by MVN
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LogicalCone User Interface
Libero™ IDE
137
ChipEditor
ChipEditor Older Antifuse Families
ChipEditor icon Libero™ IDE
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ChipEditor Older Antifuse Families
Graphical Placement Editor Place Logic Modules and
I/O
ChipEdit Shows Routing Congestion with “Rats Nest” Views Gives More Control to Power User
Libero™ IDE
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ChipEditor Viewing Routing Rats Nest View Shows Connectivity Example – CLKBUF Connected to Several Registers
Libero™ IDE
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ChipEditor Viewing Routing (cont.) Minimum Spanning Tree Mode Shows Connectivity between Selected Macros
Libero™ IDE
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Timing Constraints and Analysis
140
Designer Timing Analysis Tools Timer Static Timing Analysis Tool Generates User-specified Measurements Click Timer Icon from Designer GUI
Timing Report Generates Standard Set of Measurements Report Can Be Printed or Saved to File
Libero™ IDE
© 2005 Actel Corp.
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Timer Select Timer in Graphical Flow Manager Functions: Define Clock Constraints
and Exceptions Define Path Constraints Define Global Stop Sets Define Global Pass Sets
Information Used to Generate Timing Reports Assist in Timing Verification
in Timer Constrain Timing-driven
Layout Engine
Libero™ IDE
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141
Timer Summary Tab Displays Maximum Frequency for Clock(s) in Design Clock Selected from Pull-down
Window Enter Clock Frequency Requirement
Select Clock
Libero™ IDE
Constraints Entered on Clock Tab
Used for Register-to-Register Constraints
© 2005 Actel Corp.
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Timer Clock Tab
Select Clock
Expand button opens expanded clock path window
Specify Global Clock Constraints Select Clock from Pull-
down Menu Enter Period and Duty
Cycle
Enter Clock Exceptions to Make Exceptions to Global Clock Constraints Useful for Multicycle Path
Definition Specify clock exceptions Libero™ IDE
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Timer Paths Tab Define Path Constraints for Signal Groups Default or User-defined
Four Default Groups: Inputs to Registers Registers to Registers Registers to Outputs Inputs to Outputs
Clock Selected from Pulldown Menu Additional Paths Can Be Defined Edit -> Add Set of Paths
Constraints for default groups entered on Summary tab Libero™ IDE
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Timer Breaks Tab Provides Mechanism for Forcing Paths to Be Don't Cares
Libero™ IDE
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Timer Preferences Select File -> Preferences Longest/Shortest Path(s) Maximum Number of Paths to Display
Expanded Path(s) in List Maximum Number of Expanded Paths
to Display
Show Longest – Maximum Delays Used for Setup Calculation Shortest – Minimum delay Used for Hold-time Calculation
Sort by Actual Delay Slack
Libero™ IDE
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Timer Preferences (cont.) Path Selection Critical Paths Only Shows Maximum Delay to any
End Terminal Only Paths Between Any Pair Shows All Paths Conforming to
Defined Filters
Break Path at Register Clk/G Pins Option - Include /
Exclude Clk / G pins in/from Path Starting/Ending Points Clr/Pre Pins Option – Include / Exclude Clr / Pre Pins in/from Path Starting/Ending Points Data Pins of Latches – Include / Exclude Latch Data Pins in/from Path Starting or Ending Points Libero™ IDE
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144
Using Timer for Static Timing Analysis Understanding Setup Check Understanding Hold Check User Defined Paths
Timer Measurements d2
d1
d3
d1: delay from clock pad to driving flip-flop d2: data path delay d3: delay from clock pad to destination flip-flop Data arrival time: d2 + d1 (longest)
Libero™ IDE
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145
Maximum Clock Frequency Same Edge of Clock
Clock edge indication Expand button opens expanded clock path window to display path used to calculate the maximum clock frequency Constraints can be entered summary tab Violations indicated with “X” Min clk period = d2(longest) + setup – d3(shortest) + d1 (longest) d1 and d3 are displayed in timer info window d2 is displayed in timer path tab and info window
Libero™ IDE
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Maximum Clock Frequency Calculation Same Edge of Clock Info Window Displays Clock Network Delays
Longest Datapath delay
Min Period 15.57 + 0.77 -0.85 + 0.87 = 16.36
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Maximum Clock Frequency Opposite Edges of Clock d2
d1
d3
Min clk period* / 2 = d2(longest) + setup – d3(shortest) + d1 (longest) d1 and d3 are displayed in timer info window d2 is displayed in timer path tab and info window *uses duty cycle entered on Clock tab
Libero™ IDE
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Maximum Clock Frequency Calculation Opposite Edges of Clock Timer Calculates Maximum Frequency when Opposite Edges Are Used Based on Duty Cycle
Min Period 3.53 + 0.77 -1.91 + 1.93 = 4.32 x 2 = 8.64
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147
Setup Check Data Must Be Stable and Valid for Specified Amount of Time before ‘Capture’ Clock Edge Key Point: FF1.Q Changes with FF1.clk. Setup Is Checked on Captured Data (NOT Launched Data)
FF1:CLK
FF3:CLK
Setup Time of FF3
Libero™ IDE
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Timer Setup Check Longest Delays Used for Setup Check Select Longest in Timer Preferences Dialog Box
Libero™ IDE
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Timer Setup Check (cont.) Info Window Displays Setup Check
Setup:
Setup violation = (tclk + d3 (shortest) – setup – (d2 (longest) + d1 (longest)) < 0) Negative indicates timing violation
40.00
(clock period)
+ 0.85
(d3 shortest)
- 0.77
(library setup time)
- 15.57
(d2 longest)
- 0.87
(d1 longest)
= 23.65 (MET)
Libero™ IDE
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Hold Check Data Should Arrive after Clock Edge of FF3 Hold Check Is Done on Launching Edge
F F 1 :C L K
F F 3 :C L K
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Timer Hold Check Shortest Delays Used for Hold Check Select Shortest in Timer Preferences Dialog Box Need to Recalculate Timer Delays
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Timer Hold Check (cont.) Info Window Displays Hold Check
Hold:
Hold time violation = (d2 (shortest) + d1 (shortest) – d3 (longest) < 0) Negative indicates timing violation
11.93
(d2 shortest)
+ 0.87
(d1 shortest)
- 0.85
(d3 longest)
= 11.95
(Met)
Libero™ IDE
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Clocks Tab Clock Exceptions
Libero™ IDE
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Timer Add Path Set Path Tab Displays Registerto-Register Delays (d2) Add Specific Path or Groups of Paths Select ‘From’ Filter Inpad or Register
Select ‘To’ Filter Outpad or Register
Select Path Use of Keywords Makes Process Easier
Libero™ IDE
© 2005 Actel Corp.
Advanced Tab
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Timer Constraining User Paths Enter constraints for User-defined Groups on Paths Tab Select Clock from Drop-down Menu Use Commit Command in File Menu to Save Constraints
Constraint id
Constraint for user defined group
User Path
Libero™ IDE
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Timing Analysis Timer Performs Static Timing Analysis Using either Pre-Layout (Estimated) or Post_Layout (Actual) Timing Data Shows Performance Relative to Constraints Entered Default Groups Show: Inputs to Register Register to Register, Register to Output Inputs to Outputs
Pre-Layout delay
Libero™ IDE
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152
Timing Analysis Failed Paths Paths which Fail to Meet Constraints Are Easily Identified Expand Path for Analysis Correct Failed Paths: Change Speed Grade Change Synthesis
Constraints Modify Design
Post-Layout delay Failed timing paths
Libero™ IDE
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Timer Minimum Delays Timer Displays Minimum Delays when “Shortest” is Selected in Preferences Minimum delay displayed
Libero™ IDE
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Timer Minimum Delays (cont.) Minimum Delays Displayed on Timer Summary Tab
Window re-named to reflect minimum delays
Libero™ IDE
Required min delays shadowed no user input accepted
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Timer Outdated Data Outdated Data Grayed Out in GUI Users Must Update manually Use Recalculate Buttons or Tools > Calculate Delays
Re-calculate Min delays buttons after re-calculating
Data is grayed out after changing from “longest” to “shortest” Warning indicates data is out of date
Libero™ IDE
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Timer Breaks Tab – Global Stop Sets
Any path Passing through Defined Stop Is Don't Care Regardless of Any Other Defined Delay Useful for Removing False Paths
Libero™ IDE
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Stop Set Example
Don’t care path
Timer with no Stop set:
Libero™ IDE
Timer with $1I10:E in Stop set:
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155
Timer Breaks Tab – Global Pass Sets By Default, Timer Breaks All Signal Paths at Inputs of Flipflops and Latches Global Pass Set Editor Provides Mechanism for Modifying Breaks to Be Passthrough Paths on All Input Pins of Flip-flops and Latches Except Data Input to Flipflops Useful for Eliminating False Paths from Configuration and Control Registers
Libero™ IDE
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Pass Set Example
Desired path
Timer with no Pass set:
Libero™ IDE
Timer with U1:CLR in Pass set:
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156
Identifying Combined Cells in Timer Antifuse Designs Timer Back-annotates 0ns Delay to Combined cells Original Cells Remain in Netlist
0ns delay for U6 indicates it was combined with U5
Libero™ IDE
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Identifying Removed Cells in Timer Flash Designs
0ns delay for B_c_I indicates it was removed during netlist optimization
Libero™ IDE
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Timer SDC Constraints
Supported SDC Constraints Designer Currently Supports the Following Synopsys Design Constraints (SDC) for ProASICPLUS Devices: create_clock set_multicycle_path set_false_path set_max_delay
More SDC Constraints Coming in Future Releases With Full SDC Support, GCF Constraints Will Be Dropped
Libero™ IDE
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Specifying Design Objects in SDC Most Constraint Commands Require Command Argument SDC Supports both Implicit and Explicit Object Specification To Avoid Ambiguity, Explicitly Specify Object Type by Using Nested Object
Access Command
Design object Access command clock
port a design all_inputs all_outputs
Description
get_clocks all_clocks
Single clock in a design All clocks in a design
get_ports
An entry point to or exit point from
All entry points to a design. All exit points from a design.
cell
get_cells
An instance of a design or library cell
pin cell pin
get_pins
An instance of a design port or library
Example: set_max_delay 15.00 -from [all_inputs]
-to [get_clocks
{MY_CK_SEL}] Libero™ IDE
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Importing Timing Constraints Synopsys Design Constraint (SDC) Is Accepted File Format for Timing Constraints Synthesis Timing Constraints May Be Imported into Designer
Libero™ IDE
© 2005 Actel Corp.
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159
Exporting Timing Constraints Timing Constraints Entered in Timer Can Be Exported File Can Be Edited and Imported into Designer if Desired
Libero™ IDE
© 2005 Actel Corp.
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Designer 6.1 Timer Improved Constraints Handling PALACE .sdc File Now Imported as Source Audited as Source File Can Still Be Imported as Auxiliary File post-Compile Designer 6.1
Synthesis Synthesis
Timer
Menu select
Generate Generate design design constraints constraints
PALACE PALACE audited
GCF
compile
netlist SDC
Layout unaudited Import Importaux auxSDC SDC constraints constraintsfile file
*True Synopsys Design Constraints Libero™ IDE
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Designer 6.1 Timer Multi-cycle Path Constraints SDC Support for Multi-cycle Paths - All NGT Families APA (PA3) AX, AX-S SX-A, eX, SX-S Clock Generator
CK
FF FF 11
FF FF 22 MyDesign
CKsource New setup relationship
Default setup relationship
CKsink set_multicycle_path -setup 2 -from FF1 -to FF2
Libero™ IDE
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Designer 6.1 Timer Other Enhancements Fmax in Summary Tab Now Takes Duty Cycle into Account Sort by Slack on User-defined Sets Sort by Highest Negative Slack Now Supports Sort-by-slack and Sort-by-delay
Libero™ IDE
© 2005 Actel Corp.
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161
Timer Reports
Timing Report Tool -> Report Paths from Timer Main Menu Generates Standard Set of
Measurements External Setup and Hold Times
Can Be Included Report Can Be Printed or
Saved to File Report Can also Be Generated from Designer Main Menu
Libero™ IDE
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Timing Violation Report Lists Timing Violations in Design Tool > Report Violations
Libero™ IDE
© 2005 Actel Corp.
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Cross-Probing Timer and MVN Tools Designers Can Cross-probe between Timer and MVN Tools
Libero™ IDE
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163
Cross Probing Timer and ChipEditor Timer Expanded Path Can Cross-probe with ChipEdit and Netlist Viewer
Libero™ IDE
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Constraint Recommendations Set Realistic Constraints Set Sufficient Constraints Don’t Over constrain Improperly-Constrained Design Can Lead to Long Run Times,
Multiple Iterations and/or Sub-optimal Results max_delay Is Not Equivalent to Clock Constraint or Clock Period Use Exceptions Use Global Stop Set
Libero™ IDE
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Layout Assign Physical Locations to Unassigned I/Os Place Logic Modules Assign Routing Tracks to Nets Calculate Detailed Delays for All Paths
Libero™ IDE
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Layout Modes SX Architecture Layout Mode
Timing-Driven: Constraints Defined in Timer De-selecting Timing-Driven Layout Selects Standard
Layout
Incremental Placement
Lock Existing Placement: Treats All Unchanged Macros as Fixed Placements De-selecting Allows Placer to Relocate Unchanged
Macros if Necessary
Multiple Passes
P&R Runs Multiple Times User Specifies Number of Times and which Results to
Save (Best or All)
Advanced Options Allow Additional Control of Timing-driven Placement Engine
Libero™ IDE
SX, SXA and eX Families
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Advanced Layout Options SX Architecture Extended Run Directs Layout to Use Larger Number of Iterations during
Optimization to Improve Layout Quality Causes Layout to Run up to 5 Times Longer
Effort Level Specifies Duration of Timing-driven Phase of Optimization during
Layout as Percentage of Default Duration Default Value is 100 Selectable Range from 25 to 500
Reducing Effort Level also Reduces Run Time of Timing-driven
Place and Route (TDPR). With Effort Level of 25, TDPR Is Almost Four Times Faster than Default
of 100 However, with Fewer Iterations Performance May Suffer
Routability May or May Not Be Affected Libero™ IDE
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Advanced Layout Options (cont.) SX Architecture Timing Weight Setting this Option Changes Weight of Timing Objective Function Recommended Range: 10 - 150 (Default is 100) Bias TDPR in Favor of either Routability or Performance
Weight Is Specified as Percentage of Default Weight Value of 100 Has No Effect Value Less than 100 – More Emphasis on Routability and Less on
Performance Appropriate for Design that Fails to Route with TDPR
Value Higher than 100 – More Emphasis on Performance BUT … Very High Value of Timing Weight Might Degrade Performance!
Libero™ IDE
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166
Layout Options Axcelerator Layout Mode
Timing-Driven: Constraints Defined in Timer De-selecting Causes Standard Layout to Be
Used
Place and Route Tools
Can Be Turned On or Off
Incremental Placement and Routing
Lock Existing Placement: Treats All Unchanged Macros as Fixed Placements
Placement Effort Level
Provides Degree of Control over TimingDriven Placement Engine Range is from “Low” to “High”
Multiple Passes
P&R Runs Multiple Times User Specifies Number of Times and which
Results to Save (Best or All)
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Layout Options Flash Architecture Layout Mode Timing-Driven: Constraints Defined in
Timer De-selecting Causes Standard Layout to
be Used
Place and Route Tools Can Be Turned On or Off
Incremental Placement and Routing Lock Existing Placement: Treats All
Unchanged Macros as Fixed Placements
Multiple Passes P&R Runs Multiple Times User Specifies Nmber of Times and which
Results to Save (Best or All)
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Which Layout Mode to Use? Analyze the pre-layout estimates
Are estimates well within design specs ?
Yes
No constraints needed (Use Standard Mode Layout)
No
Are estimates within 15% of design specs ?
Libero™ IDE
Yes
Apply constraints within Timer (Use Timing-Driven Layout)
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Completed Layout
Libero™ IDE
168
Exporting SDF File Extract Timing delays for post-layout simulation
Libero™ IDE
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Other Designer Tools
169
SmartPower SmartPower Supports Axcelerator, ProASIC, and ProASICPLUS Families SmartPower Icon Not Visible for
other Families
SmartPower Report Contains Clock Domains, Set of Pins, and Annotated Pins Detailed Information Available in Designer Documentation SmartPower.pdf
SmartPower icon
Libero™ IDE
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SmartPower Summary Tab Total Static and Dynamic Power of Design Calculates Junction Temperature for Given Cooling Scenario
Design Level Power Summary
Ambient Temp. Cooling Type Calculated Junction Temp.
Libero™ IDE
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SmartPower Domains Tab Shows Clock Domains with their Corresponding Frequencies Delete selected domain Create New Domain
Domain management window – add domains or select an existing domain
Pin management window add pin to the current domain.
Filter Boxes
Libero™ IDE
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SmartPower Dynamic Tab Provides Detailed Hierarchical Reports of Dynamic Power Consumption
Reported Values
Hierarchy Instances Window
Report Window
Libero™ IDE
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171
SmartPower Activity Tab Allows Entry of Switching Activity Information on Interconnects of Design
Global Frequency
Selected Clock Domain
Pin Type Annotated Pins
NonAnnotated Pins Specified Frequency
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SmartPower Power Report Text Format Select Hierarchical, Flat or Breakdown as Report Style Select Static and/or Dynamic Power for Reporting Options Menu Invokes Preferences Menu
Libero™ IDE
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Post-Layout Simulation
Design Capture
Simulation
Synthesis
Post-Synthesis Simulation
Place & Route
Post-P&R Simulation
Libero™ IDE
Programming
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Post-Layout Simulation Steps Route design Export .sdf file (Back-annotate) Run Post-layout Simulation
SDF File Contains Delays for Min, Typ and Max (DELAYFILE (SDFVERSION "2.1") (DESIGN "counter") (VOLTAGE 2.70:2.50:2.30) (PROCESS "WORST") (TEMPERATURE 0:25:70) (TIMESCALE 100ps) (CELL (CELLTYPE "OUTBUF") (INSTANCE COUNT_pad_12) (DELAY (ABSOLUTE (PORT D (1.65:2.55:3.52) (2.21:3.40:4.62)) (IOPATH D PAD (19.19:28.90:39.88) (17.49:26.35:38.85)) ) ) )
rising min:typ:max
Libero™ IDE
© 2005 Actel Corp.
falling min:typ:max
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Post-Layout Simulation Click on “Simulation” in Design Flow Window or…
Right Mouse Click!
Double Click!
Libero™ IDE
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Post-Layout Simulation Structural Netlist and .sdf File Used for Simulation Simulator runs for 1 uS as
Default Max Operating Conditions
Default
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Post-Layout Simulation Selecting Operating Conditions Post-layout Operating Conditions Can Be Specified within Libero Tools > Options from Libero
Main Window Select Simulation Tab in
Options Window Choose Min/Typ/Max
Libero™ IDE
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Programming & Debugging
Design Capture
Simulation
Synthesis
Post-Synthesis Simulation
Place & Route
Post-P&R Simulation
Libero™ IDE
© 2005 Actel Corp.
Programming
175
Generating Programming File Flash
Generate programming file (bitstream or STAPL)
Select output file type
File Format Contains Bitstream Raw Data Raw Data plus programming infomration STAPL Libero™ IDE
Programmer Sculptor, Sculptor II Sculptor, Sculptor II, FlashPro, FlashPro Lite, In system programming © 2005 Actel Corp.
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Sculptor II Overview PC-based Parallel-port, Single Device Programmer Designed to Allow Concurrent Programming of Multiple Units from Same PC Replaces Silicon Sculptor I as Actel's Programmer of Choice Silicon Sculptor II Benefits: Programs All Actel Packages Antifuse and Flash Programming Support
Universal Actel Socket Adapters Works with Silicon Sculptor I Adapter Modules Uses Same Software as Silicon Sculptor I Provides Extensive Self-test Capability
Libero™ IDE
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Sculptor II Software Available from Actel Website http://www.actel.com/custsup/updates/silisculpt/
Requirements (Windows Version) Microsoft Windows 95/98, Win NT or Win 2000
Requirements (DOS Version) 286 with 4MB RAM, Approx. 6MB Hard Drive Space DOS-driven Program - Memory Managers Not Required DOS Shell from Windows 95/98 - OK Does Not Work with Windows NT
Libero™ IDE
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Invoking Sculptor II Software from Libero Click “Program” Button in Design Flow Window or.. Right Mouse Click!
Double Click!
Libero™ IDE
or
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Silicon Sculptor II Windows Interface
1. Select > Device 2. Buffer > Load Check to see if the chip is blank.
Programs the design fuses. Programs the security fuse.
Checksum Command (under the pull down menu) compares checksum on the chip to FUSCHECKSUM in the .afm file. Libero™ IDE
Status Area
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Silicon Sculptor II DOS Interface
Programs the security fuse. Programs the design fuses. Checks to see if the chip is blank.
2. Buffer > Load
Compares checksum on the chip to FUSCHECKSUM in the .afm file.
1. Select > Device
Status Area Libero™ IDE
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Flash Programming Flash FPGA Devices Can Be Programmed Multiple Ways Off-board Programming with Silicon Sculptor II In-System Programming (ISP) using JTAG Interface with Silicon
Sculptor II, Flash Pro or Flash Pro Lite Portable Programmer Programming via Microprocessor Interface (ProASICPLUS)
Libero™ IDE
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FlashPro Programmer Supports All Flash FPGAs Small Form Factor - 24 in3 Low Cost Hardware Features Small 26-pin Header 20” Ribbon Cable ECP Parallel Port
Software Features Win 95/98/NT/00 O/S STAPL Support Daisy Chain Capability Log File Generation Self-test Option
Libero™ IDE
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FlashPro Lite Programmer Supports ProASICPLUS Devices Low Cost Ultra-small Form Factor Hardware Features Draws Power from Target Board Connects to Parallel Port Supports In-system Programming
Software Features Supports Windows 98, NT, 2000, and XP Operating Systems STAPL Support Free Software Updates
Libero™ IDE
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July, 2005
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ISP for ProASICPLUS Programming Header New Header Samtec 26-pin Header Support by Flash Pro and Silicon Sculptor Part Number:
FTSH-113-01-L-D-K
Pinout (on Customer PCB Board, Top View) 2.5/3.3V 2.5V/3.3V 2.5V/3.3V GND GND GND NC NC GND GND TRSTB 2.5V 2.5V Libero™ IDE
1 3 5 7 9 11 13 15 17 19 21 23 25
© 2005 Actel Corp.
2 4 6 8 10 12 14 16 18 20 22 24 26
VDDP VDDP VPP VPN GND TCK TDI TDO TMS RCK TRSTB VDDL/VDD VDDLVDD
180
FlashPro User Interface
Libero™ IDE
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Programming with FlashPro Launch FlashPro from Libero Connect to Programmer Analyze Chain Select Device and Operation Execute Operation
Libero™ IDE
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Connect to Programmer File -> Connect Connect to Programmer Select Flash FPGA Device
Specify PC port Select Family Disable programming voltages from programmer if available on board
Libero™ IDE
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Analyze JTAG Chain File -> Analyze Chain Chain Details Appear in Log Window First Device Listed Is Nearest TDO of Programming Header
Select device in chain
Libero™ IDE
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Load STAPL File Load STAPL File for Programming STAPL File Exported from Designer
Open file
Libero™ IDE
© 2005 Actel Corp.
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Selecting an Operation Select Action to Perform
Option Program Erase
Verify Verify BOL Verify EOL READ_IDCODE READ DEVICE_INFO CHECK
Libero™ IDE
© 2005 Actel Corp.
Action Programs device Erases device Verify device (same as VERIFY_EOL) Verify all flash cells within BOL spec Verify all flash cells within EOL spec Reads device ID Reads back device Returns device type and s/n Checks device id
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Execute Operation Execute button
Programming sequence Optional steps in bold font
Progress displayed in log window
Libero™ IDE
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Invoking FlashPro Software from Libero Click “Program” Button in Design Flow Window or..
Right Mouse Click!
Double Click!
Libero™ IDE
or
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Programmer Summary
Programmer Sculptor II Flash Pro Flash Pro Lite
Libero™ IDE
Supported Families ALL ProASIC and ProASICPLUS PLUS ProASIC
Manufacturer BP Microsystems
Connection PC Parallel
FS2 FS2
PC Parallel PC Parallel
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Silicon Explorer Debug Designs in Real Time! Select Internal FPGA Nodes on the Fly for Viewing while Device
Runs at FULL Speed! Reduce Debug Time and Decrease your Time to Market!
Design Prototype Select Nodes Observe Results Debug
Libero™ IDE
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Preparing for Debug If Possible, Avoid Using Probe Pins for Regular User I/O
Reserve Probe pins during compilation
Make Probe Pins Accessible Jumper Leads, Dedicated
Connector
Libero™ IDE
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Preparing for Debug (cont.) Silicon Explorer Used for Debugging Can Probe any Two INTERNAL Nodes in Real Time Four Internal Nodes for Axcelerator
Also Functions as 18-channel Logic Analyzer Needs Only .prb File to Allow Debugging. Security Fuse Should NOT Be Programmed on Device
Generate Probe file
Libero™ IDE
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Action Probe Circuitry Dynamic Internal Node Access No Changes to Timing
Relationships No Changes to Fan-out or Node
Loading Antifuse Devices Only
Registers
Patented Architectural Feature Unique to Actel
No Silicon Overhead Uses Zero Logic Resources Always there if Needed
Libero™ IDE
Control Registers
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Silicon Explorer Setup SX/SX-A/eX
18 Logic Analyzer Channels
Windows PC Serial Connection
Silicon Explorer
SX/SXA TMS TDI TCK TDO
D Q
PRA PRB
Libero™ IDE
© 2005 Actel Corp.
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Silicon Explorer II Action Probe Control Serial Port Connection No Plug-in Cards
High-speed Signal Acquisition Sampling Rate 100MHz Asynchronous 66 MHz Synchronous
Analyze PC-hosted Software Optional External Power Supply (Recommended for SX-A) Multilevel Triggering
Libero™ IDE
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188
Silicon Explorer Software Full-featured 18 channel Logic Analyzer Flexible Signal Assignment Signal Grouping, Bussing Decimal, Hex, Binary,
Analog Radix Selection for Bussed Signals Edge and Level Trigger
Selection 64K Samples per Channel
Easy-to-learn, Easy-to-use Interface
Libero™ IDE
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Designer Cross-Probing Designer Allows you to Verify and Optimize your Design
Silicon Explorer II Helps you Perform In-system Debugging
Cross-Probing Links All Design Views
Libero™ IDE
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Invoking Silicon Explorer Launch Silicon Explorer from Toolbar or Process Window
Select from menu
or
Double Click!
Libero™ IDE
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Summary Libero FPGA Design Suite Includes: Design Entry ViewDraw, HDL Editor, ACTgen Synthesis Synplicity Physical Synthesis Magma PALACE Verification ModelSim, WaveFormer Lite Designer (P&R, Timing Analysis and Constraints)
Actel Continues to Improve Libero IDE Increased Quality of Results Ease of Use Additional Features
Libero™ IDE
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Outline Session 1: Introduction to Actel products Libero IDE overview and design flow Design entry Session 2: Functional simulation Synthesis Session 3: Place & Route Session 4: Post-Layout simulation Programming
Libero™ IDE
© 2005 Actel Corp.
July, 2005
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1
Introduction to Actel Products
Actel Commercial Product Spectrum Markets Full Featured FPGA
Axcelerator Axcelerator >500MHz >500MHz
PLUS ProASIC ProASICPLUS
150MHz 150MHz
Economy FPGA
ProASIC ProASIC 100 100 MHZ MHZ
SX-A SX-A 250 250 MHz MHz
CPLD Equivalent
eX eX 250 250 MHz MHz
3,000
10,000
100,000
1M
2M
Density Libero™ IDE
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July, 2005
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2
FPGA Technologies Compared
SRAM
Flash
Antifuse
1T 6T Best of Both Worlds Reprogrammable & Nonvolatile
Reprogrammable
Libero™ IDE
© 2005 Actel Corp.
Nonvolatile
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Flash Product Offering Benefits of flash FPGA technology Lowest power in its class In-system programmable Non-volatile Single-chip Lowest system cost
Product Product
KKGates Gates
Max MaxI/O I/O
Leading Leadingfeatures features
ProASIC ProASIC
475 475
440 440
ISP, ISP,2P-RAM/FIFO, 2P-RAM/FIFO,FlashLock, FlashLock,Mixed Mixed2.5V/3.3 2.5V/3.3I/O I/O
712 712
ISP, ISP,2P-RAM/FIFO, 2P-RAM/FIFO,PLLs, PLLs,LVPECL, LVPECL,FlashLock FlashLock
PLUS ProASIC 1000 ProASICPLUS 1000
Libero™ IDE
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3
Antifuse Product Offering Benefits of antifuse FPGA technology High performance
Secure FuseLock Technology
Low power
Live at power-up
Single-chip
Cost effective
High utilization/100% pin locking
Firm error resistant
Product Product
KKGates Gates Max MaxI/O I/O Leading Leadingfeatures features
SX-A SX-A
108 108
360 360
350MHz, 350MHz,64/66 64/66PCI, PCI,2.5/3.3/5V 2.5/3.3/5VHot HotSwap SwapI/O I/O
eX eX
12 12
130 130
Single-chip Single-chipFPGA FPGAoffered offeredat atCPLD CPLDdensities densities
MX MX
54 54
202 202
Best Best55volt voltsolution, solution,Embedded Embeddedblock blockRAM RAM
RTSX-S RTSX-S
108 108
205 205
SEU SEUimmune immunewith withbuilt-in built-inTMR TMR
Axcelerator Axcelerator
2000 2000
684 684
500MHz 500MHzcore/FIFO, core/FIFO,1GHz 1GHzPLL, PLL,LVDS LVDSI/O I/O
Libero™ IDE
© 2005 Actel Corp.
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Libero IDE Overview and Design Flow
4
Libero IDE Overview Complete Toolset for Actel FPGA Development Project Manager ViewDraw Schematic Capture Synplify Synthesis Testbench Generation Mentor ModelSim Simulation PALACE Physical Synthesis (Libero Platinum) Actel Designer Design Implementation Compile, Place & Route Timing and Physical Constraints Timing Analysis Power Analysis Back Annotation Programming File Generation
FlashPro Programming Software Silicon Explorer Debug Software Libero™ IDE
© 2005 Actel Corp.
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Libero Tool Suite Design Implementation
Design Verification
Physical Implementation
Synplify
SynaptiCAD
PALACE •Physical Synthesis
•Integrated Design Environment
• Synthesis
• Stimulus
ViewDraw AE
ModelSim
Actel Designer
•Place & Route
Libero™ IDE
•Schematic Capture
•Simulation
Actel
Actel
• ACTgen Macro builder
• Silicon Explorer Debugger
© 2005 Actel Corp.
FlashPro
•Programming
July, 2005
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5
Libero Project Manager Features Centrally Manages and Integrates Files and Tools Coordinates Project Information between Tools e.g., Family Is Selected Once and Communicated to All Tools
Provides Seamless Piping of Internal Design Files among Tools From within Libero’s Project Manager, User Can Invoke Tools for: Design Entry Stimulus Generation Simulation Synthesis Design Implementation and Static Timing Analysis
Libero™ IDE
© 2005 Actel Corp.
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Libero IDE Project Manager Design Explorer Window
Design Hierarchy Tab Displays Hierarchical Representation of Source Files in Project Libero Continuously Analyzes
and Updates Hierarchy
File Manager Tab Displays All Files in Project Grouped by Type
Language-Sensitive HDL Editor
Verilog 95 or VHDL 93
Design Explorer Window
HDL pane
Tools Can Be Launched from Design Flow Window or Process Window Log Windows Provide Status and Error Messages
Log Window Error Manager Status Bar
Libero™ IDE
© 2005 Actel Corp.
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Libero IDE Design Flow Window
Flow Window Displayed in HDL Pane
Tabs Switch between Flow Window and HDL Window
Libero™ IDE
© 2005 Actel Corp.
July, 2005
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Libero IDE Design Flow Window Step-by-Step design flow decreases design development time Current state of design
Design Flow Window Displays: Tools Files Transitions Current State Tool Tips
Interactive Blocks Activates Tools View Files
Display changes dynamically based on target family
Libero™ IDE
© 2005 Actel Corp.
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7
File Status of Displayed Items Group of Files Can Be … … Missing If ANY Are Missing, Block Is Shadowed Out
… Available and Current Green Check Mark Is Shown
… Available, but Not Current If at Least One is Not Current, Warning Icon Is Displayed
Synthesis Incomplete Libero™ IDE
Synthesis Complete
Source Modified – EDIF Netlist not current
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Tool States Disabled => Button Is Shadowed White => Available, but Not Yet Used Green => Completed Successfully Red => Error in Running Tool
Synthesis Succeeded
Libero™ IDE
© 2005 Actel Corp.
Synthesis Failed
8
Libero IDE View Options Displayed Windows Turned On or Off Using Libero “View” Menu
Libero™ IDE
© 2005 Actel Corp.
July, 2005
17
Libero Log Window Error Manager Error Manager Consists of 4 Tabs in Log Window: All: Displays All Messages Errors: Displays Error Messages Warnings: Displays Warning Messages Info: Displays Information Messages
Default Colors: Red => Errors Blue => Hyperlinks Light Blue => Warnings
Right Mouse Click!
Click in window to clear or copy text
Icon appears next to each message
Libero error manager tabs Libero™ IDE
© 2005 Actel Corp.
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Libero Software Updates Manually Check for Software Updates from Help Menu Configure Libero to Automatically Check for Software Updates from
Preferences Tab (File > Preferences)
Libero™ IDE
© 2005 Actel Corp.
July, 2005
19
Libero IDE New Project Wizard Menu-Driven Wizard
Use Browse button to change project location
File > New Project
Status Guide Shows Current State All Fields Must Be Filled in to
Continue
HDL Type Must Be Consistent with License Next Button Goes to Next Wizard Screen Finish Button Finishes/Closes Wizard after Making Changes. Saves All Selections.
Libero™ IDE
© 2005 Actel Corp.
July, 2005
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10
Libero IDE New Project Wizard: Select Device Select Family After Family Is Selected, Devices from that Family Are Displayed After Device Is Selected, Available Packages for that Device Are Displayed
Libero™ IDE
© 2005 Actel Corp.
July, 2005
21
July, 2005
22
Libero IDE New Project Wizard: Select Tools Synthesis
Vendor (e.g. Synplify) Version
Physical Synthesis
PALACE Version
Testbench Generation
WaveFormer Lite Select Version
Simulation
ModelSim Select Version
Support for Mentor Graphic’s LeonardoSpectrum and Precision
Standard Tools Direct from Mentor
Licensing and Technical Support Directly from Mentor
No Actel OEM Versions
Libero™ IDE
© 2005 Actel Corp.
11
Libero IDE New Project Wizard: Add Files Add Existing Design Files to Project Schematics, Symbols, HDL (VHDL or Verilog), Stimulus (VHDL or
Verilog), ACTgen Macros or EDIF Netlists
Browse to file location
Select file type
Libero™ IDE
© 2005 Actel Corp.
July, 2005
23
Libero IDE New Project Wizard: Finish Project Information Listed in Dialog Box Click “Finish” to Complete Project Creation or “Back” to Make
Corrections or Additions
Project summary shown in window
Libero™ IDE
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12
Organization of Libero Project Files Default folder for Libero projects
Libero project file
Libero™ IDE
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Libero IDE Project Startup Default Operation Upon Launch of Libero, Most Recent
Project Is Opened If No Project in Most Recently Used
List, Libero Launches the New Project Wizard
Default Controlled in Startup Properties Choose “Preferences” under “File”
Menu Choose “Startup” Tab Check or Uncheck “Open the most
recently used project at startup”
Libero™ IDE
© 2005 Actel Corp.
13
Libero Project Manager: Design Implementations Create Project Variations Save Different Project Views for Comparison Requires .adb file, Back-annotated File, Programming/Debugging
File, or Post-layout Simulation Folder
Libero™ IDE
© 2005 Actel Corp.
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27
Libero Project Manager: Design Implementations Add, Rename or remove design implementations
Libero™ IDE
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14
Libero Project Manager: Design Implementations Implementations Making Changes in Current View Can Change State of Project Pre-Synthesis Post-Synthesis Post-Physical Synthesis Affects All Other Views
Changing Implementation Files for Current View Does Not Affect
Other Views
Libero™ IDE
© 2005 Actel Corp.
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Importing Files File -> Import Files Existing Design Files Can Be Imported into Libero Project Schematics, Symbols, HDL (VHDL or Verilog), Stimulus (VHDL or Verilog),
ACTgen Macros, EDIF Netlists, SDC Files, Constraint Files, Tool Profiles Constraint Files NOT Automatically Sent to External Tools
Select file type from pull-down menu
Libero™ IDE
Schematics (*.[1-9]*) Symbols (*[1-9]*) Vhdl Sources (*.vhd, *.vhdl) Vhdl Package Files (*.vhd, *.vhdl) ACTgen Macros (*.gen) Stimulus Files (*.vhd, *.vhdl) Edif Netlists (*.edn) SDC file (*.sdc) Gatefield Constraint files (*.gcf) Tool Profiles (*.ini)
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Import Files: File Manager Tab Files Can Also Be Imported from File Manager Tab Click on File Type and Select Import
Right Mouse Click!
Libero™ IDE
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Deleting Files from Libero Project Files Can Be Deleted from Project and from HDD Files Deleted from HDD Cannot Be Recovered!
Right Mouse Click!
Libero™ IDE
© 2005 Actel Corp.
16
Design Hierarchy Tab: Block Properties Block Properties Dialog Box Displays File Path, Date Created and Last Modified Date
Right Mouse Click!
Libero™ IDE
© 2005 Actel Corp.
July, 2005
33
Libero Project Manager Include Modules for Simulation Libero Only Passes Top-level Source-related Modules to Simulation If Other Source Modules Are Required for Simulation, Check Box on File Properties
Check to include file in simulation
Libero™ IDE
© 2005 Actel Corp.
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17
Unknown Hierarchy Libero Displays Files in “Default Configuration” Tree Missing Files Indicated with “?” When Libero Cannot Determine Hierarchy, Files Are Shown with “X” under Unknown Hierarchy on Design Hierarchy Tab Files also Shown with “X” on File
Manager Tab Examine these Files to Correct Problem
or Remove File from Project
Libero™ IDE
© 2005 Actel Corp.
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Package Files Compile Order Package Files Displayed on Libero IDE File Manager Tab VHDL Packages Verilog Include Files
Use Package Files Order Window to Indicate if Packages Are for Simulation, Synthesis or Both and to Set Compile Order Use Up or Down Arrows to Change
Compile Order
Check Boxes to Compile Packages
for Simulation, Synthesis, or Both
Select Options => Package Files Organization, or Right Click in Design Hierarchy Window
Libero™ IDE
© 2005 Actel Corp.
18
Libero Project Manager Find Module To find Module in a Hierarchy, click Find Module Icon on Tool bar, or Click Edit/Find Module
Libero selects and displays the found module
Libero™ IDE
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Find in Files Edit => Find in Files, or Toolbar Icons Search for Files, Words, etc Specify by File Types Specify where to Search Match Whole Word Match Case Regular Expression
Results Shown in “Find in Files” Tab in Log Window
Libero™ IDE
© 2005 Actel Corp.
19
Find in Files Cross Probing Selecting File Name Presented in Find in Files Log Window … … Opens Selected File in Libero Text Editor … Highlights Match
Libero™ IDE
© 2005 Actel Corp.
July, 2005
39
Libero IDE Project Settings Users can change device and specify simulation and programming options Options > Project Settings
Device - change FPGA die or package Simulation - specify simulation options “Compile VHLD Package Files”
option is on by default
Programming – specify location of programming file and software
Libero™ IDE
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20
OEM Tools Support Tool Profiles Create or Edit Tool Profile for Project Options > Profiles Select Third-Party Tools & Versions Synthesis Vendor (e.g. Synplify) Version
Physical Synthesis PALACE Version
Simulation ModelSim Select Version
Testbench Generation WaveFormer Lite Select Version
Name Profile and Save Edit or Add Profiles As Needed
Libero™ IDE
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Add / Edit Tool Profiles Add/Edit Profile Requires … Name of Profile … Choosing Tool From Drop-down Menu Choose Version
… Choosing Tool Location Browse for Location Specify Location
Libero™ IDE
© 2005 Actel Corp.
21
Profile Conflict Occurs when Current Profile Settings Are Different from those of Previous Project that is Opened May Have Newer Version
Selected when Opening Project Created with an Older Version
Libero™ IDE
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Libero IDE Other Features Save Project to Different Name “Save-As” Enables Saving Project
with Different Name and/or in Different Location
Text Editor Selection Use Libero IDE Text Editor or
External Text Editor File > Preferences Text Editor Tab
Drag-Drop Dragging and Dropping Libero .prj
File in Libero Window Opens Project File
Enter location of external text editor if selected Libero™ IDE
© 2005 Actel Corp.
22
Libero IDE Online Help HTML-based Help System Help Available for Error Messages,
Specific Screens and Menus Expanded Content
Hyperlinks to Application Notes and
Actel Web Pages Help Menu Provides Direct Access to All Libero PDF Reference Manuals
Libero™ IDE
© 2005 Actel Corp.
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Design Entry
23
Design Entry Libero Supported Design Flows Structural Schematic Flow Mixed-Mode Flow HDL Flow
ACTgen Macro Builder ViewDraw Overview Schematic Design Entry Tool
Libero™ IDE
© 2005 Actel Corp.
July, 2005
47
Libero Design Flows
24
Libero Design Flows Structural Schematic Flow Contains only Actel ViewDraw Library Components or Mix of Actel
ViewDraw Library Components and Structural HDL Top Level Must Be Schematic! Synthesis Optional before Layout
Mixed-Mode Flow Schematic and RTL Blocks May also Contain Structural HDL Blocks
Top Level Must Be Schematic! Synthesis Required before Layout
HDL Flow VHDL or Verilog (not both) May Contain Structural Blocks
Libero™ IDE
© 2005 Actel Corp.
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ACTgen Macro Builder
25
ACTgen Macro Builder
Create Macro Functions from User’s Parameters
Optimized for Actel Architecture
Rule-based Generation Guarantees Functional Accuracy
Outputs:
Libero™ IDE
High Speed Small Area
© 2005 Actel Corp.
VHDL - Behavioral and Structural Verilog Behavioral and Structural
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Using ACTgen within Libero ACTgen Macros Can Be Used in … … Structural Schematic flow … Mixed-mode Flow … HDL Flow
Steps: Launch ACTgen from Libero IDE Project Manager Create HDL Structural Implementation VHDL or Verilog
HDL Flow Instantiate Macro in Top-level RTL
Structural Schematic and Mixed-mode Flows Create ViewDraw Symbol from Libero instantiate Symbol in Schematic
Libero™ IDE
© 2005 Actel Corp.
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Launching ACTgen from Libero ACTgen icon
Libero™ IDE
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ACTgen User Interface
Version #
Core details
Shows Categories Based on Selected Family View by category or alphabetically
Version of selected or configured core
View selected and configured cores for project Libero™ IDE
© 2005 Actel Corp.
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ACTgen Alphabetical Browse
Libero™ IDE
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ACTgen Browse by Family
Libero™ IDE
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ACTgen Counter Example
1. Choose Function
2. Select type and variation
Libero™ IDE
© 2005 Actel Corp.
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ACTgen Counter Example
3. Enter width
4. Complete the rest of the description
Optional Fan-In Control 5. Click Generate Libero™ IDE
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ACTgen Buffering Control Users Can Control Buffering in ACTgen Macros Control Net Loading or
Eliminate Buffering
Libero™ IDE
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Component Generation
Macro name Output format Generate behavioral VHDL or Verilog
Files appear on Libero File Manager tab
Libero™ IDE
© 2005 Actel Corp.
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Structural Schematic Designs
Structural Schematic Design Flow Design Capture
Generate Structural Netlist
Pre-Layout Simulation
Place & Route
Post-P&R Simulation
Libero™ IDE
© 2005 Actel Corp.
Programming
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Design Capture Design Capture
Generate Structural Netlist
Pre-Layout Simulation
Place & Route
Post-P&R Simulation
Libero™ IDE
Programming
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ViewDraw Overview Schematic Design Entry Tool
32
ViewDraw Features Powerful Editing Capabilities Simple, Push-Button GUI Enables Rapid Design Input Infinite Undo/Redo Dynamic Pan and Autoscroll Automatic Connection of Abutting Pins Rubber Banding of Connected Nets with Dynamic Redraw
Flexible and Customizable Designers can Add, Delete, or Reorder Items in Menu System Commands Can Also Be Entered via Function Keys or CLI Selectable Display Styles for Lines, Fill Patterns, Bus Widths
Libero™ IDE
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ViewDraw Additional Features ViewDraw AE can read EPD 2.0 and 3.0 Generated schematics Schematic files Outputs in ViewDraw format
ViewDraw can now co-exist/co-install with ePD Customers can switch back and forth between ViewDraw and ePD
tools easily
Libero™ IDE
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Invoking ViewDraw Launch ViewDraw from Libero. Create Schematic Save and Check Right Mouse Click!
Libero™ IDE
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ViewDraw Save+Check Command Window Insert Component
Zoom Functions
Net and Bus Connection
Push symbol or schematic
Drawing Tools
Libero™ IDE
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Inserting ViewDraw Components Add -> Component Enter component name
Select Directory • Project directory •Actel cells •ViewDraw builtin
Component appears here •Drag and drop into schematic Libero™ IDE
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Adding Schematic Border Built-in Library Contains Several Sheet Border Templates Templates Can Be Modified
Enter sheet name (asheet, bsheet, etc.)
Select built-in library Drag and drop into schematic
Libero™ IDE
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ViewDraw Border in Schematic
Libero™ IDE
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Customizing a Schematic Border Border Template Can Be Customized Open Border (File > Open) Select Symbol from “Type” Menu
Select built-in library
Select Symbol
Libero™ IDE
© 2005 Actel Corp.
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Customizing a Schematic Border (cont.) Save File to New Name (File > Save Copy As
Enter new sheet name
Visible on Libero File Manager Tab
Select project library
Select Symbol
Libero™ IDE
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Customizing a Schematic Border (cont.) Open Saved Border and Edit (File > Open) Add Lines, Arcs, Text, etc. as Necessary Modified border visible on File Manager tab
Libero™ IDE
© 2005 Actel Corp.
37
Adding Schematic Components Add > Component from ViewDraw Menu Add ACTgen Macros, Custom Macros or Actel Basic Cells Select VCC or GND from ‘actelcells’
Enter cell name
Select cell library Drag and drop into schematic
Libero™ IDE
© 2005 Actel Corp.
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Drawing Wires and Busses Adding a Net To Add Net: Choose Add > Net (or Add > Bus) Alternate: Click Wire (
) or Bus (
) Icon on Toolbar
Specify Net Origination Point and Depress Left Mouse Button Drag Mouse to Form Net (or Bus), specifying Points along Net
by Clicking Right Mouse Button Click Right Mouse Button to Insert Vertex in Net Release Left Mouse Button to Specify Ending Point for Net
Libero™ IDE
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Adding I/O Cells Add I/O Cells to Top-level Design Schematic Schematic-only Designs or Structural Schematic Designs Macros Contained in “actelcells” Component Library
I/O Cells Must Have Dangling Hierarchical Connector Attached to Pad Side Label Dangling Connector
I/O Macros Can Be Buried in Hierarchy
Add and label this net
Libero™ IDE
Add and label this net
Add and label this net
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Hierarchical Connectors Use Hierarchical Connectors from ViewDraw Built-in Library for All Designs Add just like Any Other Component Same Connector for Wire or Bus Called ‘in’, ‘out’, or ‘bi’ in Built-in Library
Label Net or Bus Next to Connector
add label to net Libero™ IDE
add label to bus © 2005 Actel Corp.
add label to net
39
ViewDraw Attributes A Limited Number of Attributes Can Be Entered into Schematic and Passed to Designer $Array Attribute Creates Arrays of Cells in Schematic Useful for I/O Buffers
Double-click Cell, Enter on Attribute Tab
Libero™ IDE
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Design Rule Checking
At Design Entry Completion , Save and Check Design
Click Save Check Icon Use Tools > Schematic Checker
Viewdraw Status Bar:
Libero™ IDE
© 2005 Actel Corp.
40
Design Entry Completion Files in Implementation Are Displayed on Libero Design Hierarchy and File Manager Tabs
Schematic
Libero™ IDE
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ViewDraw File Structure on HDD Schematic Files Saved in “sch” Folder Symbol Files Saved in “sym” Folder Wire Files Saved in “wir” Folder Files Visible on Libero File Manager Tab
Libero™ IDE
© 2005 Actel Corp.
41
Opening Existing Schematics
Right Mouse Click!
Libero™ IDE
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Completed Schematic
Input buffers
Actel library components
Output buffer
Hierarchical
Hierarchical
connectors
connector
Libero™ IDE
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Libero Schematic Checker (Optional) Schematic Connectivity Checker in Libero Checks for Errors Not Included in ViewDraw Save + Check Optional Step Available from File Manager Tab
Right Mouse Click!
Libero™ IDE
© 2005 Actel Corp.
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Structural Schematic Flow Using ACTgen Macros Launch ACTgen from Libero Project Manager Create HDL Structural Implementation VHDL or Verilog
Create ViewDraw Symbol from Libero and Instantiate Symbol in
Schematic Symbol Visible on File Manager Tab
Symbol
Right Mouse Click!
Libero™ IDE
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Mixed-Mode Designs
Mixed-Mode Design Flow
Design Capture
Simulation
Synthesis
Post-Synthesis Simulation
Place & Route
Post-P&R Simulation
Libero™ IDE
© 2005 Actel Corp.
Programming
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Design Capture
Design Capture
Simulation
Synthesis
Post-Synthesis Simulation
Place & Route
Post-P&R Simulation
Libero™ IDE
Programming
© 2005 Actel Corp.
July, 2005
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Mixed Mode Design Entry Mixed Mode => RTL Blocks within Schematic HDL Blocks Can Be Structural or Behavioral RTL RTL Blocks Can Be VHDL or Verilog (But Not Both)
Top Level Must Be Schematic
Procedure Create HDL Blocks RTL Blocks - Use HDL Editor or Import Existing Design Files Structural Blocks - Use HDL Editor or ACTgen
Create ViewDraw Symbols for HDL Blocks Done Automatically from Libero Design Flow Manager
Instantiate Blocks in Schematics and Make Interconnects Use Hierarchical Connectors from ViewDraw “built-in” Library for HDL
Ports in Schematic
Libero™ IDE
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RTL or ACTgen in Mixed-Mode Flow Create RTL from Libero HDL Editor or Import File
OR Create HDL Structural Implementation using ACTgen VHDL or Verilog
Create ViewDraw Symbol from Libero Instantiate Symbol in
Schematic Symbol Appears on File Manager Tab
Symbol
Right Mouse Click!
Libero™ IDE
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Mixed Mode Schematic
Libero™ IDE
© 2005 Actel Corp.
46
Synthesize Optional for Pure Schematic or Structural Schematic Flows All HDL Blocks Are Structural VHDL or Verilog (e.g., ACTgen Blocks)
Required for Mixed-mode Designs Designs Containing RTL Blocks
Libero Launches Synplicity to Insert Pads and Optimize Design Hierarchical Connectors Must Be Used Structural Schematics with All Pads Instantiated Can Go Directly to
Designer Tool
Synthesize
Libero™ IDE
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HDL Designs
47
HDL Design Flow
Design Capture
Simulation
Synthesis
Post-Synthesis Simulation
Place & Route
Post-P&R Simulation
Libero™ IDE
Programming
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Design Capture
Design Capture
Simulation
Synthesis
Post-Synthesis Simulation
Place & Route
Post-P&R Simulation
Libero™ IDE
© 2005 Actel Corp.
Programming
48
Creating New HDL Macros
Libero™ IDE
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HDL Editor
Libero™ IDE
49
HDL Editor Block Comments Comment and Uncomment Command Allows Users to Comment or Uncomment Sections of VHDL or Verilog Code
Libero™ IDE
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HDL Editor Detect Changes If File Is Open in Libero HDL Editor and Modified by another Text Editor, Warning Is Issued
Warning message in Libero log window
Libero™ IDE
© 2005 Actel Corp.
50
Libero HDL Syntax Checker HDL Syntax Checker Available from File Manager Tab Checks for Errors in HDL Blocks Errors Indicated in Libero Log Window Optional Step
Right Mouse Click!
Libero™ IDE
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Project Manager with Saved Files...
VHDL file
Libero™ IDE
© 2005 Actel Corp.
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Functional Simulation
Design Capture
Simulation
Synthesis
Post-Synthesis Simulation
Place & Route
Post-P&R Simulation
Libero™ IDE
© 2005 Actel Corp.
Programming
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Simulation Flow For Each Block You Want to Simulate . . .
Generate stimulus
Export Testbench
View Waveforms
Associate Stimulus
Invoke simulator
Compile and Run the simulation
Libero™ IDE
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Invoking WaveFormer Lite
Right Mouse Click!
or
Double Click!
Libero™ IDE
© 2005 Actel Corp.
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WaveFormer Lite Features Allows Convenient Test Stimulus Specification via GUI User Specifies Stimulus by Drawing Waveforms Supports Copy / Paste / Append Operations
Significantly Reduces TestBench Creation Time Automatically Converts Graphical Stimulus Files into HDL
TestBenches Can Generate: VHDL Testbench (*.vhd) Verilog Testbench (*.v)
Users Can Annotate Waveform For Design Documentation
Libero™ IDE
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Drawing the Stimulus WaveFormer Lite Diagram Window Bus value controls Signal level controls
Zoom controls
Cursor location inputs
Libero™ IDE
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Creating Clocks Clock name
Double Click!
Clock frequency
Clock duty cycle
Start high or low Libero™ IDE
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Creating Clocks
Libero™ IDE
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Drawing Signals State button toggles automatically Select “low” state button
Align courser and click! Use zoom controls to make viewing easier Libero™ IDE
© 2005 Actel Corp.
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Drawing Signals Edge Placement
Enter time for edge placement
Libero™ IDE
Double click at end of signal
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Editing Signals
Libero™ IDE
56
Drawing Busses Double click “VAL” state button
Double Click!
Libero™ IDE
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Editing Signals Appending and Inserting
Copy of waveform is inserted!
Libero™ IDE
© 2005 Actel Corp.
57
Copying to a Different Signal Signal Can Be Copied
Copy of waveform is inserted!
Libero™ IDE
© 2005 Actel Corp.
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Reactive Test Bench: Stimulus and Expected Response Draw stimulus waveforms on the input ports of the model under test. Draw expected response waveforms on the output ports of the model under test
Libero™ IDE
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58
Reactive Test Bench: Samples Samples Verify MUT Output Sample constructs can monitor and perform actions based on the
data sampled Sample can work at a single point or over a windowed area Sample can perform relative to the beginning of the transaction or
relative to another event in the diagram.
Libero™ IDE
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Reactive Test Bench: Control & Looping Markers used for Control & Looping Sections of Transactions Specify the end of the transaction Create loops using for, while, and repeat loop markers Insert HDL code
Libero™ IDE
© 2005 Actel Corp.
59
Reactive Test Bench: Variables Variables Parameterize State Values Variables can drive values on stimulus waveforms Variables can store values on expected waveforms Waveform states can be expressed as conditional expressions
using variables
Libero™ IDE
© 2005 Actel Corp.
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Reactive Test Bench: Delays Delays Parameterize Time Values Delays represent the time between two edges in the diagram Specify min and max values
Delay values can be time or cycle-based Conditionally control when edges occur
Libero™ IDE
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60
Reactive Test Bench: Help Resources Online Manual: Under the Help menu choose Reactive Test Bench Generation to open the help PDF Manual: Under the SynaptiCAD install directory there is a subdirectory called Help with Reactive_test bench_Generation_Option.pdf SynaptiCAD’s website: www.syncad.com
Libero™ IDE
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Saving Stimulus Save Stimulus File > Save File Name May Contain Name of Top-level Module Stimulus Appears on Libero File Manager Tab
Libero™ IDE
© 2005 Actel Corp.
61
Generating the Testbench Select Export from WaveFormer Lite Menu WaveFormer Lite Has Many Export Options Recommendations VHDL Testbench - Select “VHDL with Top Level Testbench” Verilog Testbench - Select “Verilog with Top Level Testbench”
Libero™ IDE
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Waveform and Testbench
Stimulus and testbench appear on File Manager tab in Libero
stimulus testbench
Libero™ IDE
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ModelSim AE
Libero™ IDE
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ModelSim AE Same Functionality as ModelSim PE Windows 98, Win NT, Win 2000 or Win XP
Node-Locked VHDL or Verilog
Reduced Performance No Co-simulation (VHDL and Verilog) Capability Limited to Simulation of Actel’s Gate-level Libraries Supported through Actel
Libero™ IDE
© 2005 Actel Corp.
63
ModelSim User Interface
TCL/TK User Interface TCL Scripting Source Level Debug Debug Windows
Waveform Display
Data linked to cursor
Libero™ IDE
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ModelSim Windows There Are Nine Windows
Main, Structure, Source, Signals, Process, Variables, Dataflow, Wave, & List Windows
Additional Window Features
Drag & Drop HDL Items Can Be Dragged from Dataflow, List, Signals, Source,
Structure, Variables, and Wave Windows … … And Dropped into either List or Wave Window
Libero™ IDE
Automatic Window Updating
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ModelSim Main Window Menu Bar
Tool Bar (Break, Run, Cont, Step, and Step Over)
Design Hierarchy
Status Bar (current time,
TCL Interpreter
delta time step, environment)
Libero™ IDE
ModelSim> prompt before design is loaded. VSIM> prompt is displayed after design is loaded © 2005 Actel Corp.
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Structure Window Hierarchical View of Design Structure VHDL (Squares) – Package, Component Instantiation, Generate and Block Statements Verilog (Circles) – Module Instantiation, Named fork, Named begin, task, and function
Instantiation Label, entity/module, architecture
Becomes Current Region for Source and Signals Window, Updates Process and Variables Window
Libero™ IDE
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65
Signals Window Follows Structure Window Shows Names and Values of HDL Items in Current Region of
Structure Window
Items Can Be Sorted in Ascending, Descending or Declaration Order Hierarchy (+) Expandable VHDL Items - Signals Verilog Items - Nets, Register Variables Named Events
“Drag & Drop” Wave & List windows
Force Apply Stimulus Filter Signal Types (input,output etc) Find HDL Items
Libero™ IDE
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Source Window Selected from Structure Window
Color-coded Comments, Keywords, Strings, Numbers, Executable Lines, Identifiers, System Tasks, Text
Full Edit Capability
Save, Compile and Restart
Drag and Drop Describe Examine
Libero™ IDE
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Wave Window Multiple Cursors Drag & Drop
Virtuals Multiple Panes
Zooming
Simulation Control
Libero™ IDE
Item formatting
Cursor Measurements
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Creating Busses in Wave Window Scalar Signals Can Be Combined into Vectors
Libero™ IDE
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Saving Wave Data Signals Added to Wave Window Can Be Saved for Future Simulation Runs File > Save Format from Wave Window
Libero™ IDE
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Saving Wave Data (cont.) Enter File Name in Save Format Dialog Box Enter Name on Libero Simulation Tab to Include Signals in Future
Simulation Runs
Enter file name
Libero™ IDE
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Wave Log Files (Datasets) Wave window waveforms can be saved as a Wave Log File (.wlf) for importing into other simulations. File > Save Dataset in Wave window
Libero™ IDE
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Wave Log Files (cont.) Enter file name in Save Dataset dialog box
Enter name
Libero™ IDE
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Opening Datasets Any number of Datasets can be opened for viewing or comparing to the current simulation File > Open > Dataset (Main Window) File > Open Dataset (Wave Window)
Libero™ IDE
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Opening Datasets (cont.) Click to browse for dataset
Select file and click open
Libero™ IDE
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Opening Datasets (cont.) Open dataset is displayed on a new tab in the ModelSim Main Window workspace.
Tab for dataset “gold” Libero™ IDE
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Adding Datasets to Wave Window Dataset signals can be added to the Wave window Select appropriate tab in workspace then use Structure and Signals
windows Visually compare simulation results
Libero™ IDE
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Adding Datasets to Wave Window (cont.)
Signals from dataset “gold”
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Managing Datasets Multiple Datasets can be managed with the Dataset browser View > Datasets from Main Window
Options: Open, Close, Make Active, Rename
Libero™ IDE
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Process Window View Active
Displays All Processes Scheduled to Run during Current Simulation Cycle
View In Region
Displays any Processes that Exist in Region Selected in Structure Window
Process State
Ready, Wait, Done
Window Update Show Region in Structure Window Points to Source Lines Shows Variables in Process Displays Process in Dataflow
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Variables Window Lists Names of HDL Items in Current Process VHDL - Constants, Generics and Variables Verilog - Register Variables
Tree Hierarchy - (+) Expandable, (-) Expanded Sort Ascending, Descending Declaration Order
Change Value of Selected HDL Item Find
Forward or Reverse Search
Drag & Drop
Libero™ IDE
Wave or List Windows or Log File
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DataFlow Window Explore physical connectivity of design Displays processes, signals,
nets and registers
Links to Main, Process,
Signals, Wave and Source windows
Find feature allows searching for signal, net or register names
Libero™ IDE
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Dataflow Window ModelSim AE Simulator The ModelSim AE simulator has a limited Dataflow functionality Only one process and it’s attached signals or one signal and it’s
attached processes are displayed Display net drivers or readers
Libero™ IDE
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Zoom control
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List Window Simulation Results in Tabular Format VHDL - Signals and Process Variables Verilog - Nets and Registers
“Drag & Drop” Find Function Trigger / Strobe Properties Write List
Tabular Event TSSI
Markers - Add, Delete or Goto
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Saving Tabular Output
Drag & Drop!
Libero™ IDE
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Advancing Simulation Time Three Methods At VSIM prompt: VSIM 12> run 100 ms In Main Window Tool Bar:
Restart
Run
Run Length
Run -all
Step
Continue Run
Break
Step Over
In Wave Window Tool Bar:
Run
Run -all
Continue Run Libero™ IDE
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Re-running Simulation Restart to Zero Force Restart at VSIM Prompt VSIM 12> restart –f
In Main Window Run > Restart or Restart Button Displays Restart Dialog
Keep Current
Libero™ IDE
Listed Signals Waved Signals Breakpoints Logged Signals Virtual Signals
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ModelSim Macro Files ModelSim Commands Can Be Saved in Macro File The ‘do’ Command Executes Commands Macro File Can Have any Name and Extension
Syntax: do
Example: do run.do This Command Executes File run.do
vlib presynth vmap presynth ./presynth vcom -93 -work presynth D:/Actelprj/count32/hdl/count32.vhd vcom -93 -work presynth D:/Actelprj/count32/stimulus/count32.vhd vsim presynth.testbench add wave /testbench/* run 1000ns Libero™ IDE
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Libero Simulation Options Simulation Options Can Be Set from Simulation Tab under Options Results Saved in run.do File
Specify simulation run time
Use Automatic Do File allows Libero to automatically set up the simulation for the user Include Do file allows Libero to include user-defined script. User can enter name of script file Select min, typ, max simulation conditions for post-layout simulation Default resolution based on family choice 1ps for 500K, APA, 54SXA, AX 1ns for all other families Libero™ IDE
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Invoking ModelSim Pre- or Post-Synthesis
Click “Simulation” Design Flow Window or …
Right Mouse Click!
Double Click!
Libero™ IDE
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Associating Stimulus Right Mouse Click!
Libero™ IDE
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Hierarchical Testbench Support Libero Allows Users to Specify List of Stimulus Files for Simulation No Stimulus File Selected by Default Libero Remembers Stimulus Association for Any Block
Libero™ IDE
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Pre-Synthesis Simulation ModelSim Automatically Compiles Design and Runs Simulation for 1 µS (External) Signals from
Testbench Automatically Added to Wave Window Additional (Internal) Signals Can Be Added by User
Libero™ IDE
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Libero Simulation files on HDD
Libero™ IDE
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Simulating Designs Summary Capture Design Generate RTL Netlist (VHDL or Verilog)
OR Create Schematic May Include RTL blocks Structural VHDL or Verilog Netlist Automatically
Created before Simulation
Create Testbench Use WaveFormer Lite, or Text Editor
Associate Stimulus Run Pre-Synthesis Simulation
Libero™ IDE
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Synthesis
Design Capture
Simulation
Synthesis
Post-Synthesis Simulation
Place & Route
Post-P&R Simulation
Libero™ IDE
Programming
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Invoking Synplicity Click “Synthesis” in Design Flow Window or ..
Right Mouse Click!
or Double Click!
Libero™ IDE
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Synplify Interface Add constraint files or VHDL packages
Libero automatically lists files lowest levels first, top last
Change target and result file
Libero™ IDE
Global synthesis constraints
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Result File Synplicity Produces an EDIF Netlist <design>.edn
Libero Automatically Produces Structural VHDL or Verilog Netlist <design>.vhd or <design>.v Results Appear on File Manager Tab under Synthesis Files
Libero™ IDE
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Setting the Target Options High fanout = slow, small designs Low fanout = fast, large designs Use defaults for first pass
By default, Synplify will insert Actel I/O macros on all the HDL I/O ports. When synthesizing lower-level blocks, this must be disabled.
Libero™ IDE
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Global Constraints Frequency Symbolic FSM Compiler Configure HDL Compiler Resource Sharing
Libero™ IDE
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Frequency Global clock frequency 0MHz means optimize for area
Libero™ IDE
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Symbolic FSM Compiler
When checked, it selects proper encoding for all state machines.
Encoding method can be set on individual state machines with syn_encoding directive in the HDL code
Libero™ IDE
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State Machine Encoding (VHDL) Options > Configure VHDL Compiler Sets the default encoding style for enumerated types Override encoding style on an individual basis using syn_encoding directive in constraint editor or the HDL source code # of states default encoding 1-4 sequential 5 - 24 one-hot > 24 gray
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Resource Sharing When enabled, Synplify performs automatic sharing of operator resources, including adders, subtractors, incrementers, and decrementers.
if if (s (s == ‘0’) ‘0’) then then YY <= <= AA ++ B; B; else else YY <= <= CC ++ D; D; end end if; if; S
S
A
A
+ C
B Y C
+
+ D
D
Without resource sharing Libero™ IDE
Y
B
With resource sharing © 2005 Actel Corp.
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Performing Synthesis
Compile only or check syntax
Libero™ IDE
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View Log Synplify Log contains Plenty of Valuable Information:! Warnings and Errors Double-click and Jump to Code! Fanout Limit Extraction Information
Libero™ IDE
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(Found Counter, FSM, Adder, etc.) Net Loading Logic Buffering and Replication Information Resource Usage Critical Path Timing Analysis
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Reading the Log File: Errors
Double Click!
Libero™ IDE
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Constraint Editor Synplify facilitates constraint entry with a spreadsheetlike constraint editor. File->New Select Constraint File (Spreadsheet) Select Files of type Constraint Files
Press OK Extremely easy to use
Libero™ IDE
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Constraint Editor (Cont.) Constraint Editor supports a Drag and Drop interface. There are sheets for entering: Clock Frequency or Period Clock to Clock timing Input/Output Constraints Registers Constraints Multi-Cycle Paths False Paths Attributes
Libero™ IDE
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Synplicity Directives and Attributes
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Synplicity Directives and Attributes Let You Direct Analysis, Optimization, and Mapping of Design during Synthesis Attributes Control Mapping Optimizations Attributes Can Be Entered in either .sdc Constraint File or HDL
Source Code Synplify Supports Limited Number of Attributes that Can Be Entered in
Attribute Pane Most Attributes Are Entered in your VHDL or Verilog Code
Directives Control Compiler Optimizations Directives Must Be Entered in HDL Source Code
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Actel Attribute and Directive Summary NAME
Type VALUE
alspreserve
A
syn_encoding
A
DESCRIPTION
Boolean sequential,
Prevents a net from being removed during Place and Route
onehot, gray, safe
Specifies the encoding style for state machines.
1/0
Controls the handling of hierarchy boundaries of a module
syn_hier
A
true/false 1/0
or component during optimization and mapping. Prevents the internal signal from being removed during
syn_keep
D
true/false
synthesis and optimization.
syn_maxfan
A
integer 1/0
Controls the maximum fanout of an instance, net, or port.
syn_noclkbuf
A
true/false 1/0
Turns off the automatic insertion of clock buffers. Prevents sequential optimization such as constant
syn_preserve
D
true/false
propagation, inverter push-through and FSM extraction. Specifies register design technique to apply to a module, architecture or register
syn_radhard level
A
syn_replicate
A
string 1/0 1/0
syn_sharing
D
true/false
Libero™ IDE
Disable register replication Enables/disables the resource sharing of operators inside a module during synthesis.
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alspreserve Actel-Specific Attribute Keeps Net from Being Collapsed in Designer (Back-end) Tools Must also Add syn_keep to Ensure Synplicity Retains Net Synplicity Adds alspreserve Attribute to EDIF Netlist
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alspreserve Syntax Verilog Syntax object /* synthesis alspreserve = 1 */ ; Example: module foo ( in, out); input [6:0] in; output out; wire out; wire or_out1 /* synthesis syn_keep=1 alspreserve=1 */; wire and_out1; wire and_out2; wire and_out3 /* synthesis syn_keep=1 alspreserve=1 */;
VHDL Syntax attribute alspreserve of object : signal is true ; Example: architecture comb of foo is signal and_out1, and_out2, and_out3, or_out1 : std_logic; attribute attribute attribute attribute attribute Libero™ IDE
syn_keep of and_out3 : signal is true; syn_keep of or_out1 : signal is true; alspreserve: boolean; alspreserve of and_out3 :signal is true; alspreserve of or_out1 : signal is true; © 2005 Actel Corp.
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syn_radhardlevel Example (cont.) SCOPE attribute tab:
Source files:
use C-module flip-flop for qA
Add to infer C-module flip-flops
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syn_encoding Attribute Sets Encoding Style for State Machines Overrides Default Style
Default Style - Compiler Selects Encoding Style Based on Number of States as Follows: 1 - 4 States: 5 - 24 States: > 24 States:
Sequential One-hot Gray
syn_encoding Can Have the Following Values: onehot gray sequential safe
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syn_maxfan Attribute Controls Maximum Fanout of Instance, Net, or Port Limit Specified by this Attribute May Be Treated as Hard or Soft Depending on Where It Was Specified Soft Limit May Not Be Honored if it Degrades Performance
You Can Apply syn_maxfan Attribute to Module, Register, Instance, Port, or Net For ProASIC and APA Designs Only – You Can also Apply to Module
or Entity
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syn_maxfan Usage SCOPE Constraint Editor Usage
SDC File Syntax define_attribute { object } syn_maxfan { integer } Example – Limit Fanout for Signal clk to 200:
. . . define_attribute {clk} syn_maxfan {200}
. . . Libero™ IDE
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syn_maxfan Syntax
Verilog Syntax object /* synthesis syn_maxfan = "value" */ ; Example: module test (registered_data_out, clock, data_in); output [31:0] registered_data_out;
input clock;
input [31:0] data_in /* synthesis syn_maxfan=1000 */; reg [31:0] registered_data_out /* synthesis syn_maxfan=1000 */; // Other code
VHDL Syntax
attribute syn_maxfan of object : object_type is "value" ; Example: entity test is port(clock : in bit; data_in : in bit_vector(31 downto 0); registered_data_out: out bit_vector(31 downto 0)) attribute syn_maxfan : integer; attribute syn_maxfan of data_in : signal is 1000; -- Other code Libero™ IDE
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syn_replicate Attribute Prevents Replication of Register assign syn_replicate = 0 Turns Off Register Replication Cannot Force Tool to Replicate Works along with max_fanout Value Only Supported on Individual Register
When Will Synplify Replicate or Buffer? Generally Flip-flops Are Replicated to Achieve Fan-out Control For Combinatorial Cells, Buffers Are Added
Libero™ IDE
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syn_replicate Usage SCOPE Constraint Editor Usage
SDC File Syntax define_global_attribute syn_replicate 1=enables { 1 replication | 0 } Example - Disables All Replication in Design:
0 disables replication
. . . define_global_attribute syn_replicate {0}
. . . Libero™ IDE
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syn_replicate Usage (cont.) Verilog Syntax
1 enables replication
disables replication object /* synthesis syn_replicate = 1 | 0 0*/;
Example: module norep (Reset, Clk, Drive, OK, ADPad, IPad, ADOut);
. . . reg [31:0] IPad; reg DriveA /* synthesis syn_replicate = 0 */; assign ADPad = DriveA ? ADOut : 32'bz; always @(posedge Clk or negedge Reset) if (!Reset) begin DriveA <= 0; IPad else
<= 0;
end
begin
DriveA <= Drive & OK; IPad
<= ADPad;
end
endmodule Libero™ IDE
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syn_replicate Usage (cont.) VHDL Syntax attribute syn_replicate of object : object_type is true | false ; Example: entity norep is port ( Reset : in std_logic; Clk : in std_logic; Drive : in std_logic; OK : in std_logic; ADPad : inout std_logic_vector (31 downto 0); IPad : out std_logic_vector (31 downto 0); ADOut : in std_logic_vector (31 downto 0)); end norep; architecture archnorep of norep is signal DriveA : std_logic; attribute syn_replicate : boolean; attribute syn_replicate of DriveA : signal is false; begin -- Other code
Libero™ IDE
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syn_sharing Directive Enables/Disables Resource Sharing of Operators inside Module during Synthesis By Default, Directive Is Enabled (Value 1 for Verilog, true for
VHDL). If Resource Sharing Check Box in Project View is Disabled, You Can Still Enable Resource Sharing Using syn_sharing Directive
Libero™ IDE
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syn_sharing Usage Verilog Syntax object /* synthesis syn_sharing = 1 | 0 */ ;
Example: module my_design(out,in,clk_in) /* synthesis syn_sharing=0 */; // Other code
VHDL Syntax attribute syn_sharing of object : object_type is " true | false";
object can be architecture name Example: entity alu is port ( a, b : in std_logic_vector (7 downto 0); . . . ); end alu; architecture behave of alu is -- Turn on resource sharing for the architecture. attribute syn_sharing of behave : architecture is "true"; begin -- Other code Libero™ IDE
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Retiming Synplify Pro Retiming Is Feature in Synplify Pro ver 7.5.1 Helps Improve Performance of Sequential Circuits Moves Registers across Combinatorial Gates Also Called Register Balancing
Global Option – Can Be Turned On/Off in GUI Cannot Have this Option on per-Block Basis because it Optimizes Whole
Design
Advantages Improves Design Performance
Synplify 7.5.1 Pro GUI
No Need to Modify RTL Code # of Register Cycles Remains the Same
Impact May Result in Higher Utilization May Increase Difficulty in Routing Some Designs May Degrade in Performance!
Libero™ IDE
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Retiming (cont.) Retiming Moves Registers across Design to Achieve the Best Possible fmax Before Retiming Reg
15ns
Reg
5ns
Reg
Performance: 67MHz Limited by 15ns
Reg
8ns
Reg
Performance: 83MHz Limited by 12ns
After Retiming
Reg
Libero™ IDE
12ns
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Synplify and Synplify PRO for Actel Synplify for Actel Is Equivalent to Synplicity's Synplify Product. Limited to Actel Products Only Does Not include RAM Inferencing
Included in All Libero Products Synplify Pro AE has additional features beyond Synplify AE and requires a separate license from Actel Limited to Actel products only
Libero™ IDE
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Synplify® for Actel and Synplify Pro® Features Comparison
Libero™ IDE
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Synplicity Help Synplicity Has Complete On-line Manual Invoked from Help Pulldown or
by Pressing F1
Libero™ IDE
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Post-Synthesis Simulation
Design Capture
Simulation
Synthesis
Post-Synthesis Simulation
Place & Route
Post-P&R Simulation
Libero™ IDE
Programming
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Post-Synthesis Simulation Steps: Synthesize Design with Synplicity Generate EDIF Netlist from Synplicity Libero Automatically Creates Structural VHDL or Verilog Netlist
Run Post-synthesis Simulation on Structural Netlist
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Post-Synthesis Simulation Click on “Simulation” in Design Flow window or…
Right Mouse Click!
or Double Click!
Libero™ IDE
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Post-Synthesis Simulation ModelSim automatically compiles structural netlist exported from Designer Runs simulation for 1 uS Structural library mapping
handled by Libero Pre-compiled libraries do not require compiling prior to simulation
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Place and Route
Design Capture
Simulation
Synthesis
Post-Synthesis Simulation
Place & Route
Post-P&R Simulation
Libero™ IDE
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Programming
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Open Design for Place & Route Click on “Place & Route” in Design Flow Window or… Right Mouse Click!
or Double Click!
Libero™ IDE
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Designer Interface
Designer Provides Graphical Flow Manager to Lead Designer through Design Flow Completed Tasks Highlighted Design Flow Steps Listed at Top User Tools Grouped Below
Designer Error Manager Tabs (same as Libero) Libero™ IDE
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Designer TCL Script Support Industry-standard Language Tool Command Language
Launch Multiple Tools from Single Script Launch Multiple Design Runs
Synthesis
TCL script
Designer
Simulator
Libero™ IDE
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Running Scripts within Designer In File Menu, Click Execute Script File Displays Execute Script Dialog Box
Enter name of script file Enter arguments to be passed to script file
Click Run to execute script
Tcl Scripts can be Executed from the Command Line: Example: d:\Libero\Designer\bin\designer script:my_script
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Recording Scripts Designer Can Export Tcl Script File that Contains Commands Executed in Current Session Exported Tcl Script can be used to … … re-Execute Same Commands Interactively or in Batch … Become More Familiar with Tcl Syntax
Libero™ IDE
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Importing Source Files Multiple files can be imported at the same time Netlist import is done automatically by Libero
Import File types: File Type EDIF Verilog VHDL Actel ADL Netlist Criticality ProASIC Constraint File Physical Design Constraint File
Libero™ IDE
© 2005 Actel Corp.
Extension *.ed* *.v *.vhd *.adl *.crt *.gcf *.pdc
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Importing Auxiliary Files Optional step to import pin files, timing constraints, etc. Import Auxiliary files after compile completes Import File types: File Type Criticality PIN SDC Physical Design Constraint Value Change Dump Switching Activity Intermediate File/Format Design Constraint File
Libero™ IDE
© 2005 Actel Corp.
Extension *.crt *.pin *.sdc *.pdc *.vcd
*.saif *.dcf
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Entering Constraints in Designer Option 1 - Import Files in Designer Source or Auxiliary Files
Option 2 - Import Files in TCL Script Option 3 - Set All Constraints Directly in Designer Physical - PinEdit Timing - Timer
Libero™ IDE
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Constraint File Types Physical Pin Locations SX-A, SX-S - .pin File APA - .gcf File Axcelerator - .pdc File
All I/O Attributes Axcelerator - .pdc File
Timing All Constraints APA - .sdc File Antifuse – .sdc File
Libero™ IDE
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Designer File Auditing Designer Audits Source Files to Ensure Imported Files Are Current All Imported Source Files Are Date-
and Time-stamped Designer Notifies You if File Is Changed
Audit Settings Can Be Changed (File > Audit Settings) Enable / Disable Auditing
Move File to New Location
Associate File with Current Date
and Time
Libero™ IDE
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Importing Files into Designer Summary Import the Following Source Files EDIF, VHDL, Verilog Netlists PDC, SDC, and GCF Files Source Files Are Audited per User Settings
Import the Following Auxiliary Files DCF, SDC, PDC, VCD, and SAIF Files
Libero™ IDE
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Designer Compile Reads Netlist Compiles Design into Actel Database (ADB) File Runs Combiner Performs Design Rule Checking Checks for Netlist Errors (Bad Connections and Fanout Problems) Removes Unused Logic (gobble) Verifies that Design fits into Selected Device
Libero™ IDE
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Compile Wizard Select: Die Package Speed Grade Die Voltage
Select Restrict Pin Usage Reserve JTAG Pins Reserve ActionProbe Pins
Select Ambient Temperature Commercial (0 - 70ºC) Industrial (-45 - 85ºC) Military (-55 - 125ºC) Custom
Select Voltage Range Libero™ IDE
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Radiation Derating Radiation Derating for SX-S Users Can Now Add Radiation
Exposure Level in Device Selection Wizard for Radiation Derated Timing
Libero™ IDE
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Flash Netlist Optimization
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Netlist Optimization Constraints Flash Designs Attempts to Remove All Cells from Netlist that Have No Effect on Circuit’s Functional Behavior Reduces Overall Size of Design Produces Faster Place and Route Times Takes Advantage of Inverted Inputs of Logic Tiles
By Default All Optimizations Are Performed on Netlist Original Netlist Preserved Removed Cells Back-annotated with 0ns Delay in Timer
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dont_optimize Flash Designs Turns Off All Netlist Optimizations When Followed by One or More Netlist Optimization Options, this Statement Turns off Named Option(s). Syntax dont_optimize {inverter buffer clocktree resettree const dangling};
Example: dont_optimize buffer inverter;
Libero™ IDE
© 2005 Actel Corp.
Disables buffer and inverter optimization
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optimize Flash Designs Turns On All Netlist Optimizations When Followed by One or More Netlist Optimization Options, this Statement Turns On Named Optimization Option(s) Syntax optimize {inverter buffer clocktree resettree const dangling};
Example: optimize buffer inverter;
Libero™ IDE
Enables buffer and inverter optimization
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Netlist Optimization Constraints Options buffer - Removes All Buffers Provided Maximum Fanout Not
Exceeded inverter - Removes All Inverters Provided Maximum Fanout Not Exceeded clocktree - Removes All Inverters and Buffers in Nets Connected to Clock Inputs on All Flip-Flop Cell Types resettree - Removes All Inverters and Buffers in Nets Connected to Reset Inputs on All Flip-Flop Cell Types const - Replaces All Logical Elements with One or More Constant Inputs (Connected to Logical “1” or “0”) by Simplified Logic Function If Replacement Logic Function Is Inverter or Buffer, that Element Is
Removed
dangling - Recursively Removes All Cells Driving Unconnected Nets
Libero™ IDE
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set_max_fanout May Retain Buffers and Inverters in Netlist Removes All Buffers and Inverters whose Elimination Does Not
Exceed Specified Fanout
Use this Constraint if Design Has High-Fanout Net in Critical Paths Syntax set_max_fanout
set_max_fanout
set_max_fanout
Libero™ IDE
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dont_touch Selectively Disables Optimization of Named Hierarchical Instances Wildcard (*) Isolates All Sub-Blocks Under Named Block Syntax dont_touch hier_net_name [, hier_net_name];
Example optimize buffer inverter; dont_touch /U1/myblock/*;
Enables Only Buffer and Inverter Optimization Types. Optimizes All Instances except those Contained in Block /U1/myblock. Libero™ IDE
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Import Log Flash Designs Import Log Written after Compile Step in Designer Created under
What it Reveals Promoted Globals Distribution of Fanout Device Utilization (RAMs, PLLs, IOs, Global Routes, Logic) Internal and External Nets (Min, Average and Max fanout) High Fanout Net Candidates to be Mapped to Spines Internal Clocks
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Designer Import Log Flash Designs . . . Compile Output: NOTE [removed_pwr_gnd_cells]: Removed 2 power/ground cells from the design.
Removed cells
Optimizing Netlist.
Promoting nets to globals.
Following nets are possible candidates for Globals/Spines : Fanout
Type
Driver
Name
48
CLK_NET
CLK_pad/MUXTILE
CLK_c
48
SET/RESET_NET
RESET_pad/MUXTILE
RESET_c
Following nets are assigned to global resources: Fanout
Name
48
CLK_c
48
RESET_c
Nets assigned to global resources
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Designer Import Log (cont.) . . . I/O
Cells:
Core cells: | Instances |
Input. IOs: Bidir
2
IOs:
0
Output IOs:
16
Global IOs:
2
Internal Global:
0
IOs:
Tiles
Logic
|
81
|
185 |
81
Storage
|
48
|
384 |
48
RAM/FIFO
|
0
|
0 |
0
|
|
|
----------------------Total
Gates |
----------|-----------|--------|-------
----------|-----------|--------|-------
20
Total
|
129
|
569 |
129
Actual number of tiles used Nets
| Count
| Average Fanout | Max. Fanout
---------------|--------|----------------|-----------Global
|
2
|
48.0
|
48
External
|
18
|
2.9
|
20
Internal
|
113
|
1.9
|
16
Net statistics
---------------|--------|----------------|-----------Total
|
133
|
2.7
|
48
. . . Libero™ IDE
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Identifying Removed Cells Flash Designs While Compile or Layout Is Running, Temporary File Named deleted_blocks Is Created under
Libero™ IDE
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113
Netlist Optimization Example Flash Designs -- example to test APA optimization library ieee; use ieee.std_logic_1164.all; entity test is port (A, B, presetn, resetn, clk: in std_logic; out1, out2, Q1, Q2: out std_logic); end test; architecture RTL of test is begin process (clk, resetn) begin if (resetn = '0') then Q1 <= '0'; elsif (clk 'event and clk = '0') then end if; end process;
Q1 <= A;
process (clk, resetn, presetn) begin if (resetn = '0') then Q2 <= '0'; elsif (presetn = '0') then Q2 <= '1'; elsif (clk 'event and clk = '0') then Q2 <= B; end if; end process;
Deleted blocks
out1 <= A and not B; out2 <= not A xor not B; end RTL;
Libero™ IDE
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Successful Compile Compile Button Turns Green if Compile Completes Successfully Errors Indicated in
Designer Log Window
Libero™ IDE
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114
MultiView Navigator
MultiView Navigator MultiView Navigator Includes the Following Tools: PinEditor, I/O Attribute Editor, NetlistViewer, and ChipPlanner
Allows Cross-probing Among Different Designer Tools
Libero™ IDE
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MultiView Navigator Zoom Controls
Toolbar Icons
Design Window
Working Area
Log Window
World View Window Libero™ IDE
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MultiView Navigator Windows Design Window View Design as Logical Blocks, Physical Elements, Ports, Nets, and
Regions
World View Window Shows Position of Current Viewing Window Relative to Chip
Working Area Shows Current Active Tools Tile or Cascade Active Tools
Log Window Keeps Running Log of Activity Output – Shows All Messages Errors – Shows Error Messages Warnings – Shows Warning Messages Info – Shows Informational Messages Find Window – Keeps Result of Find Function for Later Usage
Libero™ IDE
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MultiView Navigator Features Message Bar Hierarchical Error / Info Message Display Summary Line Shown in New Message Bar Expands on Demand to Show More Details Copy / Clear Messages Most Messages Transitory (Removes Clutter) Reduced Number of Tabs (Removes Clutter)
Ongoing Effort to Improve Message Content
Libero™ IDE
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MultiView Navigator Toolbar File -> Commit – Writes any Changes Made in Editors to Design Prelayout Check – Verifies Placement Changes in Editors Are
Legal
Edit -> Undo/Redo – Allows User to Undo a Mistake or Redo an
Accidental Undo
Find – Enables Find Interface
Zoom Controls Zoom Region, Zoom In, Zoom Out, Zoom to Fit
Assignment Options Place, Unplace, Lock (Fix), Unlock (Unfix)
Tools Menu ChipPlanner, PinEditor, NetlistViewer, I/O Attribute Editor
Libero™ IDE
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MultiView Navigator Prelayout Checker Infeasible Constraints Identified pre-Layout Automatically Runs when You Commit from MVN Users Can Run Using MVN Command Tools->DRC
Enhanced Checks Overlapping Region Checks Resource Overbooking I/O Technology Checks
Libero™ IDE
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MultiView Navigator Find / Search Search for Instances, Nets or Ports Wildcard (*) Matching Advanced Options - Choice of Log Window Pane for Search Results
Cross-probing from Find Tab to the other Four Windows
Libero™ IDE
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118
PinEditor
Pin Assignment Options I/O Locations Can Be Assigned as Follows: Automatically by Designer Software during Layout By Importing: . Gatefield Constraint File (.gcf) (ProASIC and ProASICPLUS)
Manually using PinEdit Tool in Designer Pin Assignments May Be Exported for Later Use
Libero™ IDE
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119
MultiView Navigator PinEditor Graphical Pin Location Editor Drag and Drop Placement of Pins Fix Pin Locations for Subsequent Place and Route Runs
Flip Display Enables Assignments as if Looking from Top or Bottom of Chip
Pinout Can Be Printed for Documentation
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I/O Features Axcelerator I/O Bank Configuration Select Bank Select I/O Standards Incompatible Options
Disappear when Selecting I/O Standards Select Low-power Mode Select Input Delay
Libero™ IDE
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VREF Pins Axcelerator Assigning VREF Pins
Libero™ IDE
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Pin Assignment Recommendations Enter Design as Completely as Possible Don’t Worry about Functionality
Compile (Ignore Warnings) and Layout “Fix”All Pin Assignments Edit > Select All then Edit > Fix
Send Pin Report to PCB Layout Continue Working Out Bugs Future Layouts Will Honor “Fixed” Assignments
Libero™ IDE
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Exporting Pin Report Pin Report Can be Exported from Designer
Libero™ IDE
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July, 2005
243
Exporting Pin Constraint File Pin Constraint File Can be Exported from Designer
File Type
PIN file Gatefield Constraint file Physical Design Constraint Libero™ IDE
© 2005 Actel Corp.
File Extension Family ACT1, ACT2, ACT3, MX, XL, DX, SX, SX-A, eX *.pin ProASIC, *.gcf ProASIC PLUS *.pdc Axcelerator July, 2005
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122
I/O Attribute Editor
MultiView Navigator I/O Attribute Editor Input/Output Attribute Editor Select (Varies by Family): I/O Standard I/O Threshold Slew Rate I/O Power-up State
Enter Load Capacitance Does Not Change SDF File
Generation
Spreadsheet-like Sort, Copy, Paste
Libero™ IDE
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MultiView Navigator I/O Attribute Editor (cont.)
Double click on column to sort display by that column
Hold down CTRL key to select multiple rows
With multiple rows selected, changing the value of a drop-down item with CTRL key pressed will change the value for all rows Libero™ IDE
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Netlist Viewer
124
MultiView Navigator Netlist Viewer Displays Netlist in Hierarchical Manner, Providing Logical View of Design Netlist Viewer Can Explore each Level of Hierarchy and Trace Signals
Open Netlist Viewer Libero™ IDE
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MultiView Navigator Netlist Viewer (cont.)
Schematic View Window – displays a graphical representation of the netlist
Search Window – shows results of searches
Libero™ IDE
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125
MultiView Navigator Netlist Viewer (cont.) Viewing Options Push, Pop, Jump to Top Go to First Page, Go to Last Page, Go to Next Page, Go to Last
Page Right-click on Net to Follow Net to Other Pages or Net Driver
Highlight, Highlight Append, un-Highlight, un-Highlight All Allows Page Splitting Allows User to Decide if All Elements on that Level Are Shown as
Single Page
Libero™ IDE
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MultiView Navigator Netlist Viewer View pre- and post-Optimized Netlists Pre-optimized Netlist Is Original Hierarchical Netlist Post-optimized Netlist is Flattened Reflects what other Tools Use (ChipEdit, PinEdit)
Libero™ IDE
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126
ChipPlanner
ChipPlanner Editing and Floorplanning ChipPlanner Capabilities: Editing Place, Unplace, or Move Logic and I/O View Macro Placements Made during Layout View Net Connections with Ratsnest or Route View View Architectural Boundaries View and Edit Silicon Features, such as I/O Banks View Placement and Routing of Paths when Used with Timer
Floorplanning Create and Assign Logic or Nets to Regions
Cross-probe with Silicon Explorer to Select Probes
Libero™ IDE
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127
ChipPlanner Terminology Region Defined sub-Portion of Die Shapes - Rectangular or Rectilinear (Union of Rectangles) Types: Empty - No Logic Can Be Put into this Region Inclusive - Assigned Logic Must Be Put into this Region Other Unassigned Logic Can Be Added to this Region by Layout
Exclusive - Only Assigned Logic Can Be Put into this Region Not Supported for APA or A500K
Assign Place Logic into Particular Region or Location
Lock Finalizes Allocation of Logic in Particular Location
Libero™ IDE
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ChipPlanner Editing and Floorplanning Drag Logic or I/O to Desired Location ChipPlanner Floorplanning Functions Create local clock region
Create Logic Region Create Empty Region
Create empty region
Delete region
Select Region Move Region
Assign / Unassign
Delete Region Resize Region
Create inclusive region
Assign/Unassign Logic to Region
Create exclusive region
Regions Can Span Logic, Memory Cells and I/O
Libero™ IDE
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128
ChipPlanner Empty Region Region > Create Empty No Logic Assigned to Empty Regions
Libero™ IDE
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ChipPlanner Inclusive Region Region > Create Inclusive Assigned Logic Put in Inclusive Region Other Logic May also Be Put in this Region
Libero™ IDE
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ChipPlanner Exclusive Region (Axcelerator) Region > Create Exclusive Only assigned logic placed in exclusive region
Libero™ IDE
© 2005 Actel Corp.
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ChipPlanner Local Clock Region (Flash) Region > Create Local Clock Assign net to a spine region graphically All logic connected with the net will be assigned to the spine region
Libero™ IDE
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130
ChipPLanner Region Color Control Individual Region Color Control Regions Have Different Default Colors Based on Types Can Change Each Region’s Default Color Region Colors Saved in .adb File Region Colors Reset to Defaults upon Recompile
Libero™ IDE
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July, 2005
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ChipPlanner Region Properties Region > Properties Indicates:
Change region color
Region Type Region Width, Height and Origin Region Usage
Shows Region Default Color Default Color Can be Changed
Also Provides Access to Assignment Window
Region size and utilization
Libero™ IDE
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MultiView Navigator Region Color Control Example
Libero™ IDE
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July, 2005
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ChipPlanner Logic Assignment Two Logic Assignment Methods Assignment Window (Region > Assign/Unassign Logic…) Provides Search and Selection Capability Also Available from Region Properties Dialog Box
Drag and Drop Logic into Region
Checkmark Indicates Assigned Logic
Libero™ IDE
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ChipPlanner Display Settings Users Can Show/Hide Object and Assign Color to Resource View > Display Settings
Libero™ IDE
© 2005 Actel Corp.
July, 2005
265
ChipPlanner Viewing Nets Select Net View Options from Nets Toolbar: Display No Nets Show nets
Display Input Nets
Hide nets
Show routes
Display Output Nets Display Input and Output Nets Display Ratsnest
Show inputs only Show Ratsnest Show outputs only
Display Routes Routes Option for APA and A500K Only
View Ratsnest Libero™ IDE
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ChipPlanner Highlighting Nets Selected Nets Can Be Highlighted to Aid Analysis Select Net from Design Window Nets Tab or Search
Results Change Highlight Color from Toolbar or Edit Menu
Highlight Color Highlight Unhighlight All
Libero™ IDE
© 2005 Actel Corp.
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ChipPlanner
ProASIC/ProASICPLUS Floorplanning Capabilities Define Rectangular Regions x/y Location Displayed During Region Resize Only Empty and Inclusive Regions Supported for APA and A500K
Assign Logic, Regular I/O and Regular Nets to Region Drag and Drop Assignments Selection Highlighting and Color Selection
Create Local Clock Region Multi-region Assignments Not Recommended Assigning Same Macro to Two Overlapping Regions is Legal However … NO Check to Ensure that Regions Overlap Layout May Fail
I/O Assignments View Spines Created through GCF View Routing Libero™ IDE
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134
Silicon Support
ProASIC/ProASICPLUS Multi-type Region Support Region Support for RAM LocalClock Regions Can Include RAM and I/O Controlled by Compile Option (Designer -> Options -> Compile) Need to Recompile after Modifying Option Default is ON for New Designs from Designer 6.0 on
Top1
RAM block
Top2
Top3 …
1) Core + memory 2) Core + memory + I/O i/o
spine core
i/o i/o i/o i/o i/o Libero™ IDE
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ChipPlanner Axcelerator Floorplanning Capabilities Define Rectangular Regions Empty, Exclusive and Inclusive Region Support for Axcelerator Modify Region types (Inclusive / Exclusive)
Assign Logic and Nets to Region I/O Assignments PLL and RAM
Assignments Drag and Drop
Assignments Multi-region Assignments NOT Recommended
Libero™ IDE
© 2005 Actel Corp.
135
Silicon Support Axcelerator LocalClock Region Support Created through PDC only PDC Syntax assign_local_clock –type routing_resource_type –net netname
3
Tile3C.Row0
2 Tile1C.RowN-1
1 A Libero™ IDE
B
C
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ChipPlanner Scripting Support ProASIC/ProASICPLUS Existing GCF Format and Capabilities GCF Enhancement to Support Partial I/O Regions
Axcelerator PDC Commands for Floorplanning Define and un-Define Region Rectangular Rectilinear (Currently Only Supported in PDC)
Region Types Empty Inclusive Exclusive (Axcelerator Only)
Assign and Unassign Resources Macros Nets
Reset Floorplan
Libero™ IDE
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136
MultiView Navigator LogicalCone Helps View Critical Portions of Netlist Identify Critical Paths using Timer Add this Logic to LogicalCone Incrementally Add / Remove Logic from Cone CrossProbe from / to LogicalCone All NetlistView Features available in LogicalCone New LogicalCone Tab in Hierarchy Window New LogicalCone Menu Accessible from NetlistViewer Can Simultaneously Create Multiple Cones Set of Macros Can Be Highlighted, then Added to Cone LogicalCone Data No Longer Valid after Recompile Applies to All Families Supported by MVN
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LogicalCone User Interface
Libero™ IDE
137
ChipEditor
ChipEditor Older Antifuse Families
ChipEditor icon Libero™ IDE
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138
ChipEditor Older Antifuse Families
Graphical Placement Editor Place Logic Modules and
I/O
ChipEdit Shows Routing Congestion with “Rats Nest” Views Gives More Control to Power User
Libero™ IDE
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ChipEditor Viewing Routing Rats Nest View Shows Connectivity Example – CLKBUF Connected to Several Registers
Libero™ IDE
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139
ChipEditor Viewing Routing (cont.) Minimum Spanning Tree Mode Shows Connectivity between Selected Macros
Libero™ IDE
© 2005 Actel Corp.
July, 2005
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Timing Constraints and Analysis
140
Designer Timing Analysis Tools Timer Static Timing Analysis Tool Generates User-specified Measurements Click Timer Icon from Designer GUI
Timing Report Generates Standard Set of Measurements Report Can Be Printed or Saved to File
Libero™ IDE
© 2005 Actel Corp.
July, 2005
281
Timer Select Timer in Graphical Flow Manager Functions: Define Clock Constraints
and Exceptions Define Path Constraints Define Global Stop Sets Define Global Pass Sets
Information Used to Generate Timing Reports Assist in Timing Verification
in Timer Constrain Timing-driven
Layout Engine
Libero™ IDE
© 2005 Actel Corp.
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141
Timer Summary Tab Displays Maximum Frequency for Clock(s) in Design Clock Selected from Pull-down
Window Enter Clock Frequency Requirement
Select Clock
Libero™ IDE
Constraints Entered on Clock Tab
Used for Register-to-Register Constraints
© 2005 Actel Corp.
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Timer Clock Tab
Select Clock
Expand button opens expanded clock path window
Specify Global Clock Constraints Select Clock from Pull-
down Menu Enter Period and Duty
Cycle
Enter Clock Exceptions to Make Exceptions to Global Clock Constraints Useful for Multicycle Path
Definition Specify clock exceptions Libero™ IDE
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142
Timer Paths Tab Define Path Constraints for Signal Groups Default or User-defined
Four Default Groups: Inputs to Registers Registers to Registers Registers to Outputs Inputs to Outputs
Clock Selected from Pulldown Menu Additional Paths Can Be Defined Edit -> Add Set of Paths
Constraints for default groups entered on Summary tab Libero™ IDE
© 2005 Actel Corp.
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285
Timer Breaks Tab Provides Mechanism for Forcing Paths to Be Don't Cares
Libero™ IDE
© 2005 Actel Corp.
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143
Timer Preferences Select File -> Preferences Longest/Shortest Path(s) Maximum Number of Paths to Display
Expanded Path(s) in List Maximum Number of Expanded Paths
to Display
Show Longest – Maximum Delays Used for Setup Calculation Shortest – Minimum delay Used for Hold-time Calculation
Sort by Actual Delay Slack
Libero™ IDE
© 2005 Actel Corp.
July, 2005
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Timer Preferences (cont.) Path Selection Critical Paths Only Shows Maximum Delay to any
End Terminal Only Paths Between Any Pair Shows All Paths Conforming to
Defined Filters
Break Path at Register Clk/G Pins Option - Include /
Exclude Clk / G pins in/from Path Starting/Ending Points Clr/Pre Pins Option – Include / Exclude Clr / Pre Pins in/from Path Starting/Ending Points Data Pins of Latches – Include / Exclude Latch Data Pins in/from Path Starting or Ending Points Libero™ IDE
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144
Using Timer for Static Timing Analysis Understanding Setup Check Understanding Hold Check User Defined Paths
Timer Measurements d2
d1
d3
d1: delay from clock pad to driving flip-flop d2: data path delay d3: delay from clock pad to destination flip-flop Data arrival time: d2 + d1 (longest)
Libero™ IDE
© 2005 Actel Corp.
July, 2005
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145
Maximum Clock Frequency Same Edge of Clock
Clock edge indication Expand button opens expanded clock path window to display path used to calculate the maximum clock frequency Constraints can be entered summary tab Violations indicated with “X” Min clk period = d2(longest) + setup – d3(shortest) + d1 (longest) d1 and d3 are displayed in timer info window d2 is displayed in timer path tab and info window
Libero™ IDE
© 2005 Actel Corp.
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July, 2005
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Maximum Clock Frequency Calculation Same Edge of Clock Info Window Displays Clock Network Delays
Longest Datapath delay
Min Period 15.57 + 0.77 -0.85 + 0.87 = 16.36
Libero™ IDE
© 2005 Actel Corp.
146
Maximum Clock Frequency Opposite Edges of Clock d2
d1
d3
Min clk period* / 2 = d2(longest) + setup – d3(shortest) + d1 (longest) d1 and d3 are displayed in timer info window d2 is displayed in timer path tab and info window *uses duty cycle entered on Clock tab
Libero™ IDE
© 2005 Actel Corp.
July, 2005
293
Maximum Clock Frequency Calculation Opposite Edges of Clock Timer Calculates Maximum Frequency when Opposite Edges Are Used Based on Duty Cycle
Min Period 3.53 + 0.77 -1.91 + 1.93 = 4.32 x 2 = 8.64
Libero™ IDE
© 2005 Actel Corp.
July, 2005
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147
Setup Check Data Must Be Stable and Valid for Specified Amount of Time before ‘Capture’ Clock Edge Key Point: FF1.Q Changes with FF1.clk. Setup Is Checked on Captured Data (NOT Launched Data)
FF1:CLK
FF3:CLK
Setup Time of FF3
Libero™ IDE
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July, 2005
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July, 2005
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Timer Setup Check Longest Delays Used for Setup Check Select Longest in Timer Preferences Dialog Box
Libero™ IDE
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148
Timer Setup Check (cont.) Info Window Displays Setup Check
Setup:
Setup violation = (tclk + d3 (shortest) – setup – (d2 (longest) + d1 (longest)) < 0) Negative indicates timing violation
40.00
(clock period)
+ 0.85
(d3 shortest)
- 0.77
(library setup time)
- 15.57
(d2 longest)
- 0.87
(d1 longest)
= 23.65 (MET)
Libero™ IDE
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Hold Check Data Should Arrive after Clock Edge of FF3 Hold Check Is Done on Launching Edge
F F 1 :C L K
F F 3 :C L K
Libero™ IDE
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149
Timer Hold Check Shortest Delays Used for Hold Check Select Shortest in Timer Preferences Dialog Box Need to Recalculate Timer Delays
Libero™ IDE
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Timer Hold Check (cont.) Info Window Displays Hold Check
Hold:
Hold time violation = (d2 (shortest) + d1 (shortest) – d3 (longest) < 0) Negative indicates timing violation
11.93
(d2 shortest)
+ 0.87
(d1 shortest)
- 0.85
(d3 longest)
= 11.95
(Met)
Libero™ IDE
© 2005 Actel Corp.
150
Clocks Tab Clock Exceptions
Libero™ IDE
© 2005 Actel Corp.
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Timer Add Path Set Path Tab Displays Registerto-Register Delays (d2) Add Specific Path or Groups of Paths Select ‘From’ Filter Inpad or Register
Select ‘To’ Filter Outpad or Register
Select Path Use of Keywords Makes Process Easier
Libero™ IDE
© 2005 Actel Corp.
Advanced Tab
July, 2005
302
151
Timer Constraining User Paths Enter constraints for User-defined Groups on Paths Tab Select Clock from Drop-down Menu Use Commit Command in File Menu to Save Constraints
Constraint id
Constraint for user defined group
User Path
Libero™ IDE
© 2005 Actel Corp.
July, 2005
303
Timing Analysis Timer Performs Static Timing Analysis Using either Pre-Layout (Estimated) or Post_Layout (Actual) Timing Data Shows Performance Relative to Constraints Entered Default Groups Show: Inputs to Register Register to Register, Register to Output Inputs to Outputs
Pre-Layout delay
Libero™ IDE
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152
Timing Analysis Failed Paths Paths which Fail to Meet Constraints Are Easily Identified Expand Path for Analysis Correct Failed Paths: Change Speed Grade Change Synthesis
Constraints Modify Design
Post-Layout delay Failed timing paths
Libero™ IDE
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July, 2005
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Timer Minimum Delays Timer Displays Minimum Delays when “Shortest” is Selected in Preferences Minimum delay displayed
Libero™ IDE
© 2005 Actel Corp.
153
Timer Minimum Delays (cont.) Minimum Delays Displayed on Timer Summary Tab
Window re-named to reflect minimum delays
Libero™ IDE
Required min delays shadowed no user input accepted
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July, 2005
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Timer Outdated Data Outdated Data Grayed Out in GUI Users Must Update manually Use Recalculate Buttons or Tools > Calculate Delays
Re-calculate Min delays buttons after re-calculating
Data is grayed out after changing from “longest” to “shortest” Warning indicates data is out of date
Libero™ IDE
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Timer Breaks Tab – Global Stop Sets
Any path Passing through Defined Stop Is Don't Care Regardless of Any Other Defined Delay Useful for Removing False Paths
Libero™ IDE
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Stop Set Example
Don’t care path
Timer with no Stop set:
Libero™ IDE
Timer with $1I10:E in Stop set:
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155
Timer Breaks Tab – Global Pass Sets By Default, Timer Breaks All Signal Paths at Inputs of Flipflops and Latches Global Pass Set Editor Provides Mechanism for Modifying Breaks to Be Passthrough Paths on All Input Pins of Flip-flops and Latches Except Data Input to Flipflops Useful for Eliminating False Paths from Configuration and Control Registers
Libero™ IDE
© 2005 Actel Corp.
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Pass Set Example
Desired path
Timer with no Pass set:
Libero™ IDE
Timer with U1:CLR in Pass set:
© 2005 Actel Corp.
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156
Identifying Combined Cells in Timer Antifuse Designs Timer Back-annotates 0ns Delay to Combined cells Original Cells Remain in Netlist
0ns delay for U6 indicates it was combined with U5
Libero™ IDE
© 2005 Actel Corp.
July, 2005
313
Identifying Removed Cells in Timer Flash Designs
0ns delay for B_c_I indicates it was removed during netlist optimization
Libero™ IDE
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157
Timer SDC Constraints
Supported SDC Constraints Designer Currently Supports the Following Synopsys Design Constraints (SDC) for ProASICPLUS Devices: create_clock set_multicycle_path set_false_path set_max_delay
More SDC Constraints Coming in Future Releases With Full SDC Support, GCF Constraints Will Be Dropped
Libero™ IDE
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158
Specifying Design Objects in SDC Most Constraint Commands Require Command Argument SDC Supports both Implicit and Explicit Object Specification To Avoid Ambiguity, Explicitly Specify Object Type by Using Nested Object
Access Command
Design object Access command clock
port a design all_inputs all_outputs
Description
get_clocks all_clocks
Single clock in a design All clocks in a design
get_ports
An entry point to or exit point from
All entry points to a design. All exit points from a design.
cell
get_cells
An instance of a design or library cell
pin cell pin
get_pins
An instance of a design port or library
Example: set_max_delay 15.00 -from [all_inputs]
-to [get_clocks
{MY_CK_SEL}] Libero™ IDE
© 2005 Actel Corp.
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Importing Timing Constraints Synopsys Design Constraint (SDC) Is Accepted File Format for Timing Constraints Synthesis Timing Constraints May Be Imported into Designer
Libero™ IDE
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159
Exporting Timing Constraints Timing Constraints Entered in Timer Can Be Exported File Can Be Edited and Imported into Designer if Desired
Libero™ IDE
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Designer 6.1 Timer Improved Constraints Handling PALACE .sdc File Now Imported as Source Audited as Source File Can Still Be Imported as Auxiliary File post-Compile Designer 6.1
Synthesis Synthesis
Timer
Menu select
Generate Generate design design constraints constraints
PALACE PALACE audited
GCF
compile
netlist SDC
Layout unaudited Import Importaux auxSDC SDC constraints constraintsfile file
*True Synopsys Design Constraints Libero™ IDE
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Designer 6.1 Timer Multi-cycle Path Constraints SDC Support for Multi-cycle Paths - All NGT Families APA (PA3) AX, AX-S SX-A, eX, SX-S Clock Generator
CK
FF FF 11
FF FF 22 MyDesign
CKsource New setup relationship
Default setup relationship
CKsink set_multicycle_path -setup 2 -from FF1 -to FF2
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Designer 6.1 Timer Other Enhancements Fmax in Summary Tab Now Takes Duty Cycle into Account Sort by Slack on User-defined Sets Sort by Highest Negative Slack Now Supports Sort-by-slack and Sort-by-delay
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Timer Reports
Timing Report Tool -> Report Paths from Timer Main Menu Generates Standard Set of
Measurements External Setup and Hold Times
Can Be Included Report Can Be Printed or
Saved to File Report Can also Be Generated from Designer Main Menu
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Timing Violation Report Lists Timing Violations in Design Tool > Report Violations
Libero™ IDE
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Cross-Probing Timer and MVN Tools Designers Can Cross-probe between Timer and MVN Tools
Libero™ IDE
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Cross Probing Timer and ChipEditor Timer Expanded Path Can Cross-probe with ChipEdit and Netlist Viewer
Libero™ IDE
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Constraint Recommendations Set Realistic Constraints Set Sufficient Constraints Don’t Over constrain Improperly-Constrained Design Can Lead to Long Run Times,
Multiple Iterations and/or Sub-optimal Results max_delay Is Not Equivalent to Clock Constraint or Clock Period Use Exceptions Use Global Stop Set
Libero™ IDE
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Layout Assign Physical Locations to Unassigned I/Os Place Logic Modules Assign Routing Tracks to Nets Calculate Detailed Delays for All Paths
Libero™ IDE
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Layout Modes SX Architecture Layout Mode
Timing-Driven: Constraints Defined in Timer De-selecting Timing-Driven Layout Selects Standard
Layout
Incremental Placement
Lock Existing Placement: Treats All Unchanged Macros as Fixed Placements De-selecting Allows Placer to Relocate Unchanged
Macros if Necessary
Multiple Passes
P&R Runs Multiple Times User Specifies Number of Times and which Results to
Save (Best or All)
Advanced Options Allow Additional Control of Timing-driven Placement Engine
Libero™ IDE
SX, SXA and eX Families
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Advanced Layout Options SX Architecture Extended Run Directs Layout to Use Larger Number of Iterations during
Optimization to Improve Layout Quality Causes Layout to Run up to 5 Times Longer
Effort Level Specifies Duration of Timing-driven Phase of Optimization during
Layout as Percentage of Default Duration Default Value is 100 Selectable Range from 25 to 500
Reducing Effort Level also Reduces Run Time of Timing-driven
Place and Route (TDPR). With Effort Level of 25, TDPR Is Almost Four Times Faster than Default
of 100 However, with Fewer Iterations Performance May Suffer
Routability May or May Not Be Affected Libero™ IDE
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Advanced Layout Options (cont.) SX Architecture Timing Weight Setting this Option Changes Weight of Timing Objective Function Recommended Range: 10 - 150 (Default is 100) Bias TDPR in Favor of either Routability or Performance
Weight Is Specified as Percentage of Default Weight Value of 100 Has No Effect Value Less than 100 – More Emphasis on Routability and Less on
Performance Appropriate for Design that Fails to Route with TDPR
Value Higher than 100 – More Emphasis on Performance BUT … Very High Value of Timing Weight Might Degrade Performance!
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Layout Options Axcelerator Layout Mode
Timing-Driven: Constraints Defined in Timer De-selecting Causes Standard Layout to Be
Used
Place and Route Tools
Can Be Turned On or Off
Incremental Placement and Routing
Lock Existing Placement: Treats All Unchanged Macros as Fixed Placements
Placement Effort Level
Provides Degree of Control over TimingDriven Placement Engine Range is from “Low” to “High”
Multiple Passes
P&R Runs Multiple Times User Specifies Number of Times and which
Results to Save (Best or All)
Libero™ IDE
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Layout Options Flash Architecture Layout Mode Timing-Driven: Constraints Defined in
Timer De-selecting Causes Standard Layout to
be Used
Place and Route Tools Can Be Turned On or Off
Incremental Placement and Routing Lock Existing Placement: Treats All
Unchanged Macros as Fixed Placements
Multiple Passes P&R Runs Multiple Times User Specifies Nmber of Times and which
Results to Save (Best or All)
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Which Layout Mode to Use? Analyze the pre-layout estimates
Are estimates well within design specs ?
Yes
No constraints needed (Use Standard Mode Layout)
No
Are estimates within 15% of design specs ?
Libero™ IDE
Yes
Apply constraints within Timer (Use Timing-Driven Layout)
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Completed Layout
Libero™ IDE
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Exporting SDF File Extract Timing delays for post-layout simulation
Libero™ IDE
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Other Designer Tools
169
SmartPower SmartPower Supports Axcelerator, ProASIC, and ProASICPLUS Families SmartPower Icon Not Visible for
other Families
SmartPower Report Contains Clock Domains, Set of Pins, and Annotated Pins Detailed Information Available in Designer Documentation SmartPower.pdf
SmartPower icon
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SmartPower Summary Tab Total Static and Dynamic Power of Design Calculates Junction Temperature for Given Cooling Scenario
Design Level Power Summary
Ambient Temp. Cooling Type Calculated Junction Temp.
Libero™ IDE
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SmartPower Domains Tab Shows Clock Domains with their Corresponding Frequencies Delete selected domain Create New Domain
Domain management window – add domains or select an existing domain
Pin management window add pin to the current domain.
Filter Boxes
Libero™ IDE
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SmartPower Dynamic Tab Provides Detailed Hierarchical Reports of Dynamic Power Consumption
Reported Values
Hierarchy Instances Window
Report Window
Libero™ IDE
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SmartPower Activity Tab Allows Entry of Switching Activity Information on Interconnects of Design
Global Frequency
Selected Clock Domain
Pin Type Annotated Pins
NonAnnotated Pins Specified Frequency
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SmartPower Power Report Text Format Select Hierarchical, Flat or Breakdown as Report Style Select Static and/or Dynamic Power for Reporting Options Menu Invokes Preferences Menu
Libero™ IDE
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Post-Layout Simulation
Design Capture
Simulation
Synthesis
Post-Synthesis Simulation
Place & Route
Post-P&R Simulation
Libero™ IDE
Programming
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Post-Layout Simulation Steps Route design Export .sdf file (Back-annotate) Run Post-layout Simulation
SDF File Contains Delays for Min, Typ and Max (DELAYFILE (SDFVERSION "2.1") (DESIGN "counter") (VOLTAGE 2.70:2.50:2.30) (PROCESS "WORST") (TEMPERATURE 0:25:70) (TIMESCALE 100ps) (CELL (CELLTYPE "OUTBUF") (INSTANCE COUNT_pad_12) (DELAY (ABSOLUTE (PORT D (1.65:2.55:3.52) (2.21:3.40:4.62)) (IOPATH D PAD (19.19:28.90:39.88) (17.49:26.35:38.85)) ) ) )
rising min:typ:max
Libero™ IDE
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Post-Layout Simulation Click on “Simulation” in Design Flow Window or…
Right Mouse Click!
Double Click!
Libero™ IDE
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Post-Layout Simulation Structural Netlist and .sdf File Used for Simulation Simulator runs for 1 uS as
Default Max Operating Conditions
Default
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Post-Layout Simulation Selecting Operating Conditions Post-layout Operating Conditions Can Be Specified within Libero Tools > Options from Libero
Main Window Select Simulation Tab in
Options Window Choose Min/Typ/Max
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Programming & Debugging
Design Capture
Simulation
Synthesis
Post-Synthesis Simulation
Place & Route
Post-P&R Simulation
Libero™ IDE
© 2005 Actel Corp.
Programming
175
Generating Programming File Flash
Generate programming file (bitstream or STAPL)
Select output file type
File Format Contains Bitstream Raw Data Raw Data plus programming infomration STAPL Libero™ IDE
Programmer Sculptor, Sculptor II Sculptor, Sculptor II, FlashPro, FlashPro Lite, In system programming © 2005 Actel Corp.
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Sculptor II Overview PC-based Parallel-port, Single Device Programmer Designed to Allow Concurrent Programming of Multiple Units from Same PC Replaces Silicon Sculptor I as Actel's Programmer of Choice Silicon Sculptor II Benefits: Programs All Actel Packages Antifuse and Flash Programming Support
Universal Actel Socket Adapters Works with Silicon Sculptor I Adapter Modules Uses Same Software as Silicon Sculptor I Provides Extensive Self-test Capability
Libero™ IDE
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Sculptor II Software Available from Actel Website http://www.actel.com/custsup/updates/silisculpt/
Requirements (Windows Version) Microsoft Windows 95/98, Win NT or Win 2000
Requirements (DOS Version) 286 with 4MB RAM, Approx. 6MB Hard Drive Space DOS-driven Program - Memory Managers Not Required DOS Shell from Windows 95/98 - OK Does Not Work with Windows NT
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Invoking Sculptor II Software from Libero Click “Program” Button in Design Flow Window or.. Right Mouse Click!
Double Click!
Libero™ IDE
or
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Silicon Sculptor II Windows Interface
1. Select > Device 2. Buffer > Load Check to see if the chip is blank.
Programs the design fuses. Programs the security fuse.
Checksum Command (under the pull down menu) compares checksum on the chip to FUSCHECKSUM in the .afm file. Libero™ IDE
Status Area
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Silicon Sculptor II DOS Interface
Programs the security fuse. Programs the design fuses. Checks to see if the chip is blank.
2. Buffer > Load
Compares checksum on the chip to FUSCHECKSUM in the .afm file.
1. Select > Device
Status Area Libero™ IDE
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Flash Programming Flash FPGA Devices Can Be Programmed Multiple Ways Off-board Programming with Silicon Sculptor II In-System Programming (ISP) using JTAG Interface with Silicon
Sculptor II, Flash Pro or Flash Pro Lite Portable Programmer Programming via Microprocessor Interface (ProASICPLUS)
Libero™ IDE
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FlashPro Programmer Supports All Flash FPGAs Small Form Factor - 24 in3 Low Cost Hardware Features Small 26-pin Header 20” Ribbon Cable ECP Parallel Port
Software Features Win 95/98/NT/00 O/S STAPL Support Daisy Chain Capability Log File Generation Self-test Option
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FlashPro Lite Programmer Supports ProASICPLUS Devices Low Cost Ultra-small Form Factor Hardware Features Draws Power from Target Board Connects to Parallel Port Supports In-system Programming
Software Features Supports Windows 98, NT, 2000, and XP Operating Systems STAPL Support Free Software Updates
Libero™ IDE
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ISP for ProASICPLUS Programming Header New Header Samtec 26-pin Header Support by Flash Pro and Silicon Sculptor Part Number:
FTSH-113-01-L-D-K
Pinout (on Customer PCB Board, Top View) 2.5/3.3V 2.5V/3.3V 2.5V/3.3V GND GND GND NC NC GND GND TRSTB 2.5V 2.5V Libero™ IDE
1 3 5 7 9 11 13 15 17 19 21 23 25
© 2005 Actel Corp.
2 4 6 8 10 12 14 16 18 20 22 24 26
VDDP VDDP VPP VPN GND TCK TDI TDO TMS RCK TRSTB VDDL/VDD VDDLVDD
180
FlashPro User Interface
Libero™ IDE
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Programming with FlashPro Launch FlashPro from Libero Connect to Programmer Analyze Chain Select Device and Operation Execute Operation
Libero™ IDE
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Connect to Programmer File -> Connect Connect to Programmer Select Flash FPGA Device
Specify PC port Select Family Disable programming voltages from programmer if available on board
Libero™ IDE
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Analyze JTAG Chain File -> Analyze Chain Chain Details Appear in Log Window First Device Listed Is Nearest TDO of Programming Header
Select device in chain
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Load STAPL File Load STAPL File for Programming STAPL File Exported from Designer
Open file
Libero™ IDE
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Selecting an Operation Select Action to Perform
Option Program Erase
Verify Verify BOL Verify EOL READ_IDCODE READ DEVICE_INFO CHECK
Libero™ IDE
© 2005 Actel Corp.
Action Programs device Erases device Verify device (same as VERIFY_EOL) Verify all flash cells within BOL spec Verify all flash cells within EOL spec Reads device ID Reads back device Returns device type and s/n Checks device id
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Execute Operation Execute button
Programming sequence Optional steps in bold font
Progress displayed in log window
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Invoking FlashPro Software from Libero Click “Program” Button in Design Flow Window or..
Right Mouse Click!
Double Click!
Libero™ IDE
or
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Programmer Summary
Programmer Sculptor II Flash Pro Flash Pro Lite
Libero™ IDE
Supported Families ALL ProASIC and ProASICPLUS PLUS ProASIC
Manufacturer BP Microsystems
Connection PC Parallel
FS2 FS2
PC Parallel PC Parallel
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Silicon Explorer Debug Designs in Real Time! Select Internal FPGA Nodes on the Fly for Viewing while Device
Runs at FULL Speed! Reduce Debug Time and Decrease your Time to Market!
Design Prototype Select Nodes Observe Results Debug
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Preparing for Debug If Possible, Avoid Using Probe Pins for Regular User I/O
Reserve Probe pins during compilation
Make Probe Pins Accessible Jumper Leads, Dedicated
Connector
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Preparing for Debug (cont.) Silicon Explorer Used for Debugging Can Probe any Two INTERNAL Nodes in Real Time Four Internal Nodes for Axcelerator
Also Functions as 18-channel Logic Analyzer Needs Only .prb File to Allow Debugging. Security Fuse Should NOT Be Programmed on Device
Generate Probe file
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Action Probe Circuitry Dynamic Internal Node Access No Changes to Timing
Relationships No Changes to Fan-out or Node
Loading Antifuse Devices Only
Registers
Patented Architectural Feature Unique to Actel
No Silicon Overhead Uses Zero Logic Resources Always there if Needed
Libero™ IDE
Control Registers
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Silicon Explorer Setup SX/SX-A/eX
18 Logic Analyzer Channels
Windows PC Serial Connection
Silicon Explorer
SX/SXA TMS TDI TCK TDO
D Q
PRA PRB
Libero™ IDE
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Silicon Explorer II Action Probe Control Serial Port Connection No Plug-in Cards
High-speed Signal Acquisition Sampling Rate 100MHz Asynchronous 66 MHz Synchronous
Analyze PC-hosted Software Optional External Power Supply (Recommended for SX-A) Multilevel Triggering
Libero™ IDE
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Silicon Explorer Software Full-featured 18 channel Logic Analyzer Flexible Signal Assignment Signal Grouping, Bussing Decimal, Hex, Binary,
Analog Radix Selection for Bussed Signals Edge and Level Trigger
Selection 64K Samples per Channel
Easy-to-learn, Easy-to-use Interface
Libero™ IDE
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Designer Cross-Probing Designer Allows you to Verify and Optimize your Design
Silicon Explorer II Helps you Perform In-system Debugging
Cross-Probing Links All Design Views
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Invoking Silicon Explorer Launch Silicon Explorer from Toolbar or Process Window
Select from menu
or
Double Click!
Libero™ IDE
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Summary Libero FPGA Design Suite Includes: Design Entry ViewDraw, HDL Editor, ACTgen Synthesis Synplicity Physical Synthesis Magma PALACE Verification ModelSim, WaveFormer Lite Designer (P&R, Timing Analysis and Constraints)
Actel Continues to Improve Libero IDE Increased Quality of Results Ease of Use Additional Features
Libero™ IDE
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