Leakage Current.pdf

The Design of Low Leakage SRAM Cell with High SNM 1 1 12* Hao YAN , , , Donghui WANG , Chaohuan HOU

i

Digital System Integration Lab, Institute of Acoustics, Chinese Academy of Sciences 2 Graduate University of Chinese Academy of Sciences Beijing, China *Email:[email protected]

Abstract

provide additional well to separate the bulk of MOS

As the development of CMOS technology, the memory

increase the threshold voltage of transistor and reduce the

transistor from substrate. In a word, the main principle is to takes a great part in the entire chip area and becomes the

leakage in data retention.

main power contributor in the SOC system. SRAM which is

Another powerful group in limiting the leakage current is

the most used in on-chip memory for its low activity now

reducing voltage. Lower standby voltage or higher source

consumes a lot of power while in standby mode because of

voltage of SRAM cell to reduce all three components of

the increasing number of transistors and scaling feature

leakage current [4]-[7]. In order to dynamically reduce the

length. Therefore several analysis of traditional 6T transistor

leakage, feedback monitor scheme [8] and other dynamic

has been done and some design principles are given. At last,

adjust scheme based on BIST [5] are proposed to change the

in this paper a lOT low leakage SRAM cell with high SNM

voltage properly. Although the leakage power is cut down,

based

other problem such as stability and robustness emerge.

on

SMIC

90nm

CMOS

technology

has

been

introduced. The proposed SRAM cell saves about 88%

Among those anti-leakage structures, many designs are

leakage current and the SNM in read operation is enlarged

based on the probability of data occurrence. Thus many

3.5 times and does not decrease in data retention. In order to

structures are asymmetrical like Sanjeev's 8T SRAM cell [9]

reduce the sensing delay, a two-stage sense amplifier which

[10].

turns the differential to single-ended is also proposed. By

structure into single-ended, and this degrades the sensing

Asymmetrical

cell

always

turns

the

differential

using this sense amplifier, the sensing delay is reduced to

speedy in READ operation.

46% when the load capacitance is 100tF compared with

In order to design a symmetrical SRAM cell with low

conventional voltage sense amplifier. Key words: Low Leakage; SRAM; static noise margin; 1. Introduction

Over the years, on-chip memory capacity has increased with every new generation of CMOS process. And according to the ITRS forecast, memory is going to occupy 90% of SOC area by 2013 [1]. Thus the power consumed by the in-chip memory becomes the main contributor in total SOC system. Therefore, how to reduce the power consumed in memory becomes increasingly prominent. SRAM is the most common option in SOC chips design for its low activity factor. Although this benefits the entire SOC active power density, the standby power can not be ignored. As the development of CMOS process and the increasing number of transistors in SRAM, the standby power in SRAM even dominates the whole power performance. As a result, many schemes and structures are proposed to reduce the standby power generated in SRAM. And for simplicity these methods can be classified into three groups: 1) special process; 2) reducing voltage; 3) anti-leakage structure. In the special process group, the dual VT method [2] is often used because it is supported by most of CMOS technology. Another effective anti-leakage method in this group is body bias scheme [3], while this scheme needs the process to

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leakage in the standby mode, the leakage has been study in the 6T SRAM cell and some design tips have been discussed in anti-leakage cell design; in order to alleviate the power issue combined with the stability caused by voltage scaling, the principle of design high SNM cell has also been discussed. Then the lOT anti-leakage SRAM cell with high SNM is designed based on the above research. The reminder of this paper is organized as follows. In section 2, the analysis of the leakage in SRAM cell and the principles in design anti-leakage cell with high SNM have been given, and at last the proposed anti-leakage with HIGH SNM SRAM cell is been introduced. The sense amplifier is also proposed to reduce the sensing delay. Section 3 gives the simulation results of the proposed memory cell. Finally, the conclusions are drawn in section 4. 2. The Proposed SRAM Cell

Six-transistor SRAM cells have served as the workhorse embedded memory for several decades [11]. And it gives significance guidance to design novel SRAM cell by studying the 6T SRAM cell. 2.1 The leakage in 6T SRAM

Figure.l shows the typical leakage current in 6T SRAM cell. Compared with the subthreshold leakage current, the gate leakage current in transistor can be neglects. Therefore, the

gate leakage current is not drawn in figure.1.

READ STABLITY

HOLD STABLITY

Suppose that the storage node Q is "0", and the NQ stores data

"

I

".

0.9

And in the standby mode, the bit line BL and NBL

are pre-charged to power supply. In this data retention state

0.8

there exist three main leakage currents: 11, 12, and 13.

0.7 0.6

� 0.5 0.4 0.3 0.2 0.1 '°----::-': :----� 0 O .5 Q

Figure 1. The leakage in 6T SRAM cell In order to reduce these leakage currents, some special leakage path in figure.1. By considering the leakage current can be merged into one. As the figure 2 depicts, the transistors PA and NB are used to control the leakage. Here PA must be PMOS transistor and NB must be NMOS transistor

for

maintaining

keep

the

the

storage

feedback

during

nodes data

full

swing

retention.

in For

simplicity, the gate signals of PA and NB are not drawn in figure 2, but the PA and NB must be in the off state. Considering the symmetrical SRAM cell structure, it needs at least ten transistors to realize anti-leakage SRAM cell. Thus another two transistors PB and NA are needed to place in the symmetrical points, and this added transistor PB ( the symmetry transistor of PA) and NA must be turning on to keep the forward feedback loop in this situation, otherwise the storage node could not maintain the data that has been written into it.

Q

Figure 3. Butterfly curves simulated in 90-nm technology: read (a), hold (b)

transistors need to be insert into the cross point to cut off the 11 and 12 sink to a common node Q, thus the two cross point

0.5 �1I!IIi!1IIIIlj: °oi----::'-;-

The stability of the conventional 6T SRAM cell can be verified by examining its butterfly curve, which contains the voltage transfer characteristics of the two inverters. Figure 3 depicts the butterfly curves in the hold and read states. From figure 3, the SNM in read state is worse than the hold state. Because of the poor stability in read operation, the 6T SRAM cell can not work under ultra low voltage and this restricts its application. In the read operation, the access transistors are open, then the bit line can affect the storage node though the access transistors, and this deteriorates the SNM of 6T SRAM cell in the read operation. To enhance the SNM in read operation, a special concept is introduced here. In the traditional 6T SRAM cell, the access node and the storage node are superposition, and in the read step, the coupling factor of the access node and the st?rage node equals one, which degrades the SNM. However, If the access node and the storage node are separated, then the coupling factor becomes smaller, and therefore the SNM in read operation would be increased. Though the above analysis, one principle of design the SRAM cell with high SNM is decoupling the storage node and the access node. 2.3 The proposed SRAM cell and sense amplifier

Figure 2. The transistors used in reduceing the leakage current Through the above analysis in 6T SRAM cell, several principles in design the anti-leakage SRAM cell can be obtained: 1) insert additional transistor into the leakage path to cut off the leakage current; 2) make sure that the storage

Figure 4. The proposed 10T SRAM cell

nodes are full swing; 3) keep the feedback loop of the two cross coupled inverters to maintain the data. 2.2 The SNM of 6T SRAM

By

the

study

of

the

traditional

6T

SRAM

cell,

an

anti-leakage 10T SRAM cell with high SNM in read operation is introduced. Figure 4 gives the schematic of this proposed 10T cell. From figure 4, the access nodes are

separated from storage nodes. And in this lOT SRAM cell, NMOS N3 and N4 are access transistors; PMOS P3 and P4 are

decoupling

transistors;

PMOS

PS

and

P6

are

anti-leakage transistors; Pl,Nl and P2,N2 formed two cross coupled inverter. During the WRITE operation, the WL and NWL become effective, then N3, P3, N4, P4 conducts. In this time, the access node A though P3 and PS to change the storage node Q, and so does the access node B. Luckily, the conduction of P3 and P4 makes the pull up transistor PI and P2 cross coupled together by the access node, and this enhance the write ability. In the STANDBY step, the WL and NWL turn off, and the bit line BL and NBL are both pre-charged to V DD. Suppose the node Q stores "0" and "1" in node NQ. By removing the N3, P3, N4, P4, the PI, PS, Nl, P2, P6, N2 form the crossed coupled inverter to keep the data storage in these nodes. And the transistor PS which is inserted into the leakage path has

Figure 6. The layout of the proposed lOT SRAM cell Simulation results of leakage of 6T and lOT SRAM cell in data retention are shown in figure 7. From figure 7, the leakage current in lOT SRAM cell is 1.207nA at TT Conner, and the leakage current is reduced 88.62% compared with 6T SRAM cell.

been turned off by the node NQ. Thus the leakage currents through BL to node Q and V DD to node Q are reduced, and -

the PI, P2, PS, P6, Nl, N2 can use transistors with high In the READ operation, the access transistors plus with Q can discharge the bit line through P3 and N3. Meanwhile, the voltage difference between two bit lines increases, and then the sense amplifier detect this change on the bit lines and output the right data. Figure.S depicts the proposed sense amplifier for this lOT SRAM cell. The proposed sense amplifier aims at alleviating the low discharge speed caused by the decoupling PMOS transistors and realizing the

-

400

threshold voltage to reduce the leakage furthermore. decoupling transistors are turning on. And the storage node

ST lOT 350

,

300

t::5

200

(j) !!:! <:

.... --'.... u

'" "'-

100

The first sense logic in this sense amplifier is a coupling

0

stage is a common amplifier circuit, which gives the right response according to the first stage.

I fsL

!

•

!

I I I

55

fsH

sfL

,

PVT ()

It

I

i snfo

,

oJ ff

J ,( , I

fnso

Figure 7. Leakage in lOT SRAM cell compared with traditional 6T structure in different PVTs

NE is the equalize logic that used to initialize the sense

amplifier before it starts to work. The second sense amplifier

! 1 I, :

!

�,

sfH

I I I

i i

!

:,

I

I

!

! i

I I I

I

I

50.0

-50.0

I

I

150

differential bit lines, and uses PMOS as access transistor. NMOS structure between node C and D, and the transistor

!

250

conversion from the differential to single-ended. Therefore, this novel sense amplifier is interested in the high voltage of

,,

I

Figure 8 is the butterfly curves of this proposed lOT SRAM cell in read and hold state. By observing this figure, the SNM in lOT cell during read operation is 320mV and is about 3.S times to the 6T. In the hold stage, the SNM in lOT SRAM does not decrease. And this proves that the designed lOT cell has better stability in read and hold stage. READ STABLITY 0.9

o.

0.8

o.

I I

¢I

0.7 0.6 -0-. _ 0.4

I I I

1r---{3.. -EI I I I I [jJ I

0.3 0.2

Figure S. The proposed sense amplifier

0.1 0

3. Simulation Results

HOLD STABLITY

I I I I I

o.

0.4 0.3 0.2 0.1

0

0 0

0.5 Q

--g.�---g. I [jJ I \ I I

� 0.5 Q

In this part, the simulation results are shown based on SMIC

Figure 8. The butterfly curves of the proposed lOT SRAM

90nm CMOS technology. Figure 6 is the layout of this

cell

proposed lOT SRAM cell, and it occupies 3.S6x2.48 /lm2. Table 1 gives the comparison results of different sense amplifier

with

different

SRAM

structure.

And

these

[7] G Razavipour, A. Afzali-Kusha, and M. Pedram, IEEE

simulation results are obtained at 30° C under TT Conner.

Transactions on Very Large Scale Integration (VLSI) Systems, 17, p. 1551 (2009).

Table 1. The comparIson 0f sensmg deIay SRAM

6T

lOT

Sense amplifier

Load Capacitance

Unit

50

100

150

200

jF

CV

217

320

423

Failed

pS

Proposed

158

162

167

172

pS

CV

351

Failed

Failed

Failed

pS

Proposed

167

174

187

201

pS

From the table 1, the sensing delay has been reduced by using the proposed sense amplifier compared with the conventional

voltage

capacitance

becomes

sense

amplifier.

larger,

the

When

the

perfonnance

load of

conventional voltage amplifier gets worse and even fails to work. Especially in the lOT SRAM because of the slow discharge

speed

of

decouple

transistor.

However,

the

proposed sense amplifier can solve this problem and give a 46% perfonnance upgrade and compared with the 6T SRAM, the delay only increase about 7.4% as the load capacitance equals 100tF. And from the table, the proposed sense amplifier is very robustness as the change of the load capacitance.

4. Conclusion In this paper, by the study of the leakage and stability of traditional 6T SRAM cell, several anti-leakage and SNM enhancing design principles are proposed, and by the guidance of those design tips, a lOT SRAM cell has been introduced. This lOT SRAM cell consumes only 11.38% current during data retention, and improves the SNM about 3.5 times SRAM in read operation compared with traditional 6T SRAM cell. With the help of the proposed sense amplifier, the sensing delay is reduced 46% compared with the conventional voltage sense amplifier. Acknowledgments

This work is supported by National Science and Technology Major Projects of China (2009ZXO 1 034-00 1-002-005). References

[1] 2002

International

Technology

Roadmap

for

Semiconductors. [2] Behnam Amelifard, Farzan Fallah and Massoud Pedram, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 16, p.851 (2008). [3] Chris Hyung-il Kim, etc, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 13, P.349 (2005). [4] H. Qin, Y. Cao, etc, in Proc. Int. Symp. Quality Electronic Design (ISQED),

p. 55(2004)

[5] Mohammad Sharitkhani and Manoj Sachdev, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 15, p.196 (2007). [6] J. Wang and B. H. Calhoun, IEEE Journal of Solid-State Circuits, 43, p.2514 (2008).

[8] Chen

WU,

etc, International SoC Design Conference

(ISOCC), p. 315 (2010). [9] Navid Azizi, etc, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 11, p.701 (2003). th [10] Sanjeev K. Jain, etc, 19 International Conference on V LSI

Design,

Held

jointly

with

5th

International

Conference on Embedded Systems and Design, p.4 (2006). [ll]Faith

hamzaoglu,

etc,

Computers, p.22 (2011).

IEEE

Design

and

Test

of