Lab Manual Vlsi
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RAJIV GANDHI PROUDYOGIKI VISHWAVIDYALAYA, BHOPAL New Scheme Based on AICTE Flexible Curricula Electronics & Communication Engineering, VI-Semester Subject: VLSI Circuits & Systems List of Experiments
Course Code: B.E. 1. To design half adder using Verilog HDL. 2. To design full adder using Verilog HDL. 3. To design 4:1 mux using Verilog HDL. 4. To design 2:4 decorder using Verilog HDL. 5. To design 3:8 decorder using Verilog HDL. 6. To design 4:2 encorder using Verilog HDL. 7. To design D flip- flop adder using Verilog HDL. 8. To design T flip-flop using Verilog HDL.
Examination Scheme: EC-6004 VLSI Circuits & Systems 70 20 10 30 10 10 150 3 - 2 4 IA EndSem
Term work,Lab Work & Sessional
30
20
Prof.Shweta Agrawal Lab In-charge
Prof. Shweta Agrawal Faculty In-charge
Total 50
Prof. P.Badal Head of Department
Course Code: B.E. 1. To design half adder using Verilog HDL. 2. To design full adder using Verilog HDL. 3. To design 4:1 mux using Verilog HDL. 4. To design 2:4 decorder using Verilog HDL. 5. To design 3:8 decorder using Verilog HDL. 6. To design 4:2 encorder using Verilog HDL. 7. To design D flip- flop adder using Verilog HDL. 8. To design T flip-flop using Verilog HDL.
Examination Scheme: EC-6004 VLSI Circuits & Systems 70 20 10 30 10 10 150 3 - 2 4 IA EndSem
Term work,Lab Work & Sessional
30
20
Prof.Shweta Agrawal Lab In-charge
Prof. Shweta Agrawal Faculty In-charge
Total 50
Prof. P.Badal Head of Department
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