Joubert2006 Rws

Time Behavioral Model for Phase-Domain ADPLL based frequency synthesizer Cyril Joubert(1,2), Jean François Bercher(1), Geneviève Baudoin(1), Thierry Divel(2), Serge Ramet(2), Philippe Level(2) (1) ESIEE-ESYCOM, 2 Boulevard Blaise Pascal, 93160 Noisy-le-Grand, France. (2) ST-MICROELECTRONICS, 12 Rue Jules Horowitz, B.P.217, 38019 Grenoble, France [email protected], [email protected], [email protected], [email protected], [email protected], [email protected]

Abstract: In this paper, we present a Time Behavioral Model of a recently proposed Phase-Domain All-Digital Phase-Locked Loop (ADPLL) for RF applications. This model can be easily implemented, and results in a versatile and fast ADPLL simulator that enables to study many aspects of the PLL, e.g. transient responses, steady states, limit cycles, or to perform perturbation analysis. Moreover, we present a baseband analysis that allows computing the power spectral density from the instantaneous frequency given by the output of the behavioral model. Simulations illustrate the effectiveness of this new behavioral model.

1. Introduction Recently, a new All Digital Phase-Locked Loop based RF frequency synthesizer was presented by Staszeswski and al. [1]. A block diagram of the proposed architecture is shown in Fig 1. FCW

RPA

ΦR [ k ] + +

+

ΦE [ k ]

Loop Filter

FDCO

OTW DCO

−

ε[k] ΦD [k ] TDC

FREF

DQ

Q D

ΦD [ i ] DPA

1

FS

Fig 1. ADPLL based RF frequency synthesizer [1] A digitally controlled oscillator (DCO) allows for this PLL to be implemented in a fully digital manner [2]. Phase accumulators are used to count cycle periods of reference and feedback oscillators. A synchronous clock, FS, undersamples the output of the DCO phase accumulator (DPA), so that comparison of the two phases can be performed using the same clock. The retimed clock, FS, is achieved by oversampling the reference clock, FREF, by the oscillator clock, FDCO. Note that in Fig 1, index i and k do not refer to the same clock. Higher ADPLL precision is obtained using fractionnal phase error correction. One can show that this fractionnal phase error is proportionnal to a time delay. The Time to Digital Converter (TDC) is used to convert the delay

(phase) between the RF and reference clocks directly into a digital quantity [3], with a time resolution, noted ∆TRES, that can be equal to the elementary propagation delay through an inverter gate. The Frequency Command Word (FCW) is given as input to the reference phase accumulator (RPA), and enables to tune the output frequency of the DCO. FDCO = FCW .FREF (1) Designing a PLL requires a simulator in order to study the effect of varying parameters and optimize the PLL. Analysis and simulation of the ADPLL in Fig. 1, with a direct method requires a very high rate clock. Indeed, such a clock must have a rate that is greater than the highest frequency in the system. This requirement leads to an incredible simulation time and fantastic amounts of data. The objective of this paper is to show that it is possible to simulate such a PLL at much more reasonnable rate, without sacrifying accuracy. The limiting components are the DCO phase accumulator (at FDCO rate), and the TDC (with accuracy ∆TRES), because of they would need an extremely fast sampling frequency for a correct representation. The key for developing new simulation model is to express behavior of limiting components outputs directly at rate FREF but independently of internal rate FDCO or time accuracy ∆TRES. This can be understood as a kind of carrier frequency suppression. In section 2 we consider the analysis of the simplest phase comparator: a D flip-flop, and so doing we present the basics of our behavioral model. Then, in section 3 we develop the closed loop model; expressions of TDC and resampled oscillator phase accumulator outputs are derived using the analysis of section 2. Next, we show how to derive the Power Spectral Density (PSD) from the instantaneous frequency obtained at the output of the DCO. Finally, we show typical results obtained using the behavioral model and we make simulation comparison with conventional VHDL model.

2. Principle of behavioral model In order to understand the principle of the behavioral model, we focus on simple D flip-flop. Indeed, this

central element links asynchronous clocks FDCO and FREF because it resynchronizes them. Let us consider the waveform shown in Fig 2. In this diagram two important parameters appear: the delay τk and the integer value N(k). τk is defined as the difference between the kth reference rising edge and following oscillator rising edge, and N(k) is the real-value count of the DCO clock periods TD,k for each cycle of the reference clock. FREF

D

Q

FS

τk+1

TR

FREF TD,k

This analysis results in the following equations: (Ni + 1)TD,k − TR + τ (k) if τ (k + 1) − TD,k < 0 τ (k + 1) =  (5) otherwise .  NiTD,k − TR + τ (k) This can be further simplified into τ ( k + 1) = τ ( k ) + ( N i ( k ) + 0,5 )TD , k − TR

(6) − sgn (N i ( k )TD , k − T R + τ ( k ) )TD , k 2 using sgn(x) the sign function: sgn(x)= –1 if x<0, and sgn(x)=1 otherwise. Similarly, equation (2) and condition (3) leads to N ( k ) = N i ( k ) + 0 .5 (7) − 0.5 sgn (τ ( k ) + N i ( k ) TD ,k − TR ). An equivalent block diagram of (6) is shown in Fig 4.

FDCO

τk

In the case where N(k) take only two values, computation of N(k) proceeds as follows. First suppose that N(k)=Ni(k)+1, and compute τk+1 using (2). Then, we have to check that (3) is satisfied. If it is, we keep N(k)=Ni(k)+1, otherwise N(k) = Ni(k).

TD,k+1

FDCO N(k).TD,k

Ni

FS TD

Fig 2. Inputs/output of the D flip-flop with a representative set of waveforms

(2)

where TR is the period of the reference clock and TD,k is the DCO period during the kth FREF cycle. An important point is that the time delay is bounded according to

0 ≤ τ k +1 ≤ TD , k

∀k .

(3)

Another essential remark is that the phase error in the PLL is directly proportionnal to this delay. Equation (2) is valid if TD,k remains constant during a whole cycle of FREF. Let us define by Ni(k) the integer part of the ratio between the two periods defined above T  N i (k ) =  R  . (4)  TD ,k  In (2) we have either N(k) = Ni(k) or N(k) = Ni(k) +1. Hence the behavior of the D flip-flop is equivalent to a Dual Modulus Divider (DMD) controlled by the phase error (via the delay τ) as shown in Fig 3. In an extented model taking into account possible variations of TD,k during FREF cycle, we may represent N(k) by N(k) = Ni(k) + C(k) where C(k) is a natural number. FDCO

DMD Ni/Ni+1

FS

control

FREF

TD/2 τk+1

τk

The exact relation between reference and oscillator frequencies can be deduced from the waveform in Fig 2. We obtain the following relashionship between τk+1 and τk:

τ k +1 = τ k + N (k )TD , k − TR

TR

τ

Fig 3. Behavioral model of the D flip-flop by a DMD controlled by the phase error

Sgn

TD/2

Fig 4. Equivalent block diagram of (6).

3. Closed Loop Model For the closed loop model we need to compute the output of phase accumulators and fractionnal error correction ε. Expression of reference phase accumulator is simply given by the well-known relation φ R [k + 1] = (φR [k ] + FCW ) mod[2 R ] , (8) where we take care of modulo effect resulting of the finite width R of the reference phase accumulator. Similarly, the undersampled output of the DCO phase accumulator, RV(k) of the finite width D can be written (9) φ D [k + 1] = (φ D [k ] + N [k ]) mod[2 D ] . However this expression cannot be implemented without knowledge of N(k). Thanks to our previous analysis, we are here able to compute N(k) using (7) and, therefore implement (9). The fractionnal phase error ε can be simply modelized as the quantified version of our previous τk+1, normalized to TD , an averaged value of TD, as shown in Fig 5. A more precise model can be derived from the analysis of the TDC in terms of quantified delay between rising and falling edges preceding the rising edge of FREF. This model is not developped in this paper for sake of simplicity.

τk+1

q

With the assumption that x = 2π∆f pp

ε(k)

1 / TD

t

∫ g (τ )dτ 0

is

small enough so that sin( x ) ≈ x , we obtain the first order approximation t

sˆ(t ) = cos(ω 0 t ) − 2π ∆f pp sin(ω 0 t ) ∫ g (τ ) dτ

q=∆TRES/TV

(15)

0

Fig 5. Simple model of the fractionnal phase error correction Other elements involved in the ADPLL are the phase error computation, the loop filter and the DCO. They are briefly described now. The phase error is not just realized by an arithmetic additionner, which can be realised by a linear equation:

φ E [k ] = φ R [k ] − φ D [k ] + ε [k ]

(10) but by an adder with a limited width that take into account the binary-signed format and modulo effect. The digital loop filter is implemented by its difference equation. The DCO is modelized by equations given in [2]. For a small deviation ∆f, we can use simple linearized model

f DCO (k ) = f 0 + ∆f (k ) = f 0 + OTW (k ) K DCO

(11) where f0 is the central frequency, OTW is the oscillator tuning word at the input of the DCO, and KDCO the gain of the DCO. Note that the real output of our model is directly the instantaneous frequency, delivered at rate FREF, and not a time signal with that instantaneous frequency. However, we may compute the PSD of such virtual signal in baseband.

4. Spectral density computation The objective of this section is to show how to compute the PSD from the instantaneous frequency given by the output of the behavioral model. Let us consider fi(t) the instantaneous frequency of an oscillator

f i (t ) = f 0 + ∆f i (t ) = f 0 + ∆f pp .g (t )

(12)

where f0 is the mean frequency, ∆fpp is the peak-to-peak deviation from f0 and g(t) is a normalized frequency modulation pattern (-1
t

θ i (t ) = ∫ 2πf i (τ )dτ = 2πf 0 t + 2π∆f pp ∫ g (τ )dτ 0

(13)

0

The output signal s(t) of the oscillator is given by t   s(t ) = cos(θ i (t ) ) = cos 2πf 0 t + 2π∆f pp ∫ g (τ )dτ  . 0  

(14)

after developing the cosine in (14). The Fourier Transform of sˆ(t ) is   t  1 1 Sˆ( f ) = (δ f 0 + δ− f 0 ) − 2π ∆f pp TF ∫ g(τ )dτ  ⊗ (δ f 0 − δ− f 0 )   2  2j   0

(16)

∆f  G( f − f0 ) G( f + f0 )  1  − Sˆ ( f ) = (δ f 0 + δ − f 0 ) + pp  2 2  f − f0 f + f0 

(17)

where G ( f ) = TF [g (t )] For f = ±f0, the weight can also be computed by 1 tmax t 1 2 − π∆f pp g (τ )dτ dt . t max ∫0 ∫0 Thereby, with (17), we can directly compute the PSD transform of the instantaneous frequency using solely the lowpass signal g(t). The analysis above is continuous, but an exactly similar analysis can be done in the discrete case. For implementation of a simulator based on our behavioral model, care must be taken on spectral aliasing, and a zeroth-order interpolation have to be used in order to increase the sampling period.

5. Simulations The new behavioral model was implemented in MATLAB. Another conventional model was realized in VHDL and simulated in MODELSIM. Simulations were done with two objectives to achieve: 1. Validation of the time behavioral model by comparison with results obtains with a VHDL model. 2. Study of spurs linked to limit cycles and noise level due to quantization (TDC). Examples reported below are typical results obtained using the behavioral model. Statistical analysis of performances and sensibility of the PLL will be developed elsewhere.

5.1 Time behavioral model validation For both models with same set of parameters, we compare the transient behavior of the DCO output frequency when we change the frequency command word. Fig 6 show the transient reponse of the output frequency of the ADPLL, when FCW is out of synthesizable range of the DCO (T1) and next (T2), when FCW changes between minimum and maximum synthesizable value of the DCO. We observe the same behavior and settling time.

Different frequency steps and gains for the DCO characterize these three modes. The behavioral model enables measure and analysis of the locking sequence: transient parts and fluctuations during steady states as shown in Fig 8.

(a) T2

T1

5.3 Spectral density computation

(b)

With the spectral density computation analysis in section 4, we easily compute the PSD of the instantaneous frequency of the DCO. 0

Fig 6. Simulation comparison of instantaneous frequency between new behavioral model (a) and VHDL model (b)

20log|S(f)| [dB]

0

(FDCO - f0)/FREF

X: 0 Y : -6.021

-2 0

-1/400

-4 0 -6 0 X: 9.572e+004 Y : - 86.2

-8 0

X: 2.401e+006 Y : - 80.66

-1 0 0 -1 2 0 -1 4 0

-1/200

-1 6 0 -5

-3/400

-2 .5

0

2 .5

5

f-f 0 [M H z] -1/100 300

400

500

600

700

800

900

300

400

500

t/Tref

(a)

600

700

800

900

(b)

Fig 7. Limit cycle comparison between new behavioral model (a) and VHDL model (b) In Fig 7, we show the ADPLL locked behavior for both models (with the same scale). We note the same general behavior (frequency deviation, patterns), but also observe little differences in limit cycle sequence because of TDC modelisation and accuracy limitation of VHDL simulator (1 femtosecond).

5.2 ADPLL Locking sequence Convergence of the ADPLL is achieved using three different modes [2]: first, a calibration (CAL) mode intitiates the TDC and the central frequency of the PLL, independantly of frequency command word. Second, an acquisition (ACQ) mode acquires channel selected by FCW. Third, a tracking (TRK) mode achieves the required performances (use of a Sigma Delta modulator can further refine this last mode). 1

CAL

3/4

ACQ

Fig 9. PSD of the locking sequence when PLL is settled In Fig 9, we show an example of PSD when the PLL is locked. We can see amplitude and frequency of spurs, due to accuracy of TDC and precision of DCO.

6. Conclusion We have presented a simple and effective behavioral model for an all-digital phase locked loop. This model, based on a simple expression of the delay that is an image of phase error, enables simulating the PLL at low rate (independently of carrier frequency) instead of conventional high rate simulator. Simulation comparisons with traditionnal VHDL simulator confirm the validity of this new model. Such a model will be used to analyse several aspects of this ADPLL and select a set of parameters optimizing its performance. Results including the effect of the Sigma Delta modulator and adaptation of the behavior model will be presented at the conference.

TRK

References:

(a)

(FDCO - f0)/FREF

1/2 1/4 0

(b)

-1/4

[1]

(c)

-1/2 -3/4 -1

0

2000

4000

6000

8000 t/Tref

10000

3/40

(c)

1/20

1/40

(FDCO - f0)/FREF

(FDCO - f0)/FREF

(b)

12000

14000

16000

0

1/10

-1/80

0 -1/40

-1/40 1920 1930 1940 1950 1960 1970 1980 1990

t/Tref

4000 4500 5000 5500 6000 6500 7000 7500 8000

t/Tref

Fig 8. Locking sequence (a) and zoom (b, c) on transient at the modes shifts

R. B. Staszeswski and P. T. Balsara, Phase-Domain AllDigital Phase-Locked Loop, IEEE trans. on circuits and System, Vol 52, n°3, March 2005, pp 159-163. [2] R. B. Staszewski, C.-M. Hung, D. Leipold and P. T. Balsara, A first Multigigahertz Digitally Controlled Oscillator for Wireless Applications, IEEE Trans. on Microwave Theory and Techniques, Vol 51, n°11, Nov 2003, pp 2154-2164. [3] R. B. Staszewski, D. Leipold, C.-M. Hung and P. T. Balsara, TDC-Based Frequency Synthesizer for Wireless Applications, IEEE RFIC Symposium, 2004, pp 215-218.