Inverter

ELEC 301 Lab 5: Cadence Layout Tutorial 1 Revision: 2.0 Date: July 98

Overview This lab shows you how to layout a simply inverter using Virtuoso Layout Editor. Virtuoso provides a hierarchical I.C. layout and verification environment that supports all I.C. design techniques, from hand crafting, to automatic placement and routing. This tutorial will take you step-by-step through the process of handcrafting a simple inverter and perform the design rule checking (DRC) to verify the correctness of the physical design. This layout will correspond to the schematic, which has been created in lab2.

Learning the command in Virtuoso Layout Editor In virtuoso, you can always seek help from the OpenBook whenever you faced any difficulty. To begin this lab, you are required to familiar with the virtuoso command, which will be frequently used in the following sections, by going through the OpenBook. To start the OpenBook, type “openbook” in the command window. Then select IC Tools – Layout Design – Virtuoso Layout editor help. Spend at least 15 mins to go thought all 4 topics (Cellviews, The LSW, Creating Objects and the Editing Objects).

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Setting Virtuoso Layout Editor Environment Before you can draw the layout in Virtuoso, you must first create a cellview (view name layout in cell inv) to contain the layout data. This is done using the same procedures you used previously to create the schematic cellview. Step 1. 1.1.

Open inv layout in edit mode. When you open a layout cellview, you see both the cellview and Layer and Selection Window (LSW). The LSW will appear first along the left side of the screen. Next an empty Virtuoso window will appear. At this point, you may find that the CIW window is overlapped by the Editing window. You should move the windows around so that you have a good view of the LSW window, the Editing window and the CIW. Keep your eye on the CIW messages and the status banner at the top of the Editing window.

1.2

The Layer and Selection Window (LSW) allow you to choose the layer on which you draw objects (called the “drawing” or “entry” layer). layer Name nwell

active

poly pselect nselect cp metal1

via metal2

ca text dg pn ELEC301

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Description This is the well put down in a P-type wafer to provide a tub for the PMOS transistors Thin oxide region which identify active region for transistors. Polysilicon. Used to make the gate of the MOS device P-type implant mask N-type implant mask Contact cut between poly and metal1 First level metal. Used for horizontal routing. E.g. Power and Ground of cells First to second level metal contact cut Second level metal. Used for vertical routing. Eg I/O pin of signal. Contact cut between active and metal1. Label for parts. Drawing for a layer Label the metal which is used as a I/O pin. Page 2 of 13

It can also be used to set the layers to selectable or visible. The detailed procedure will be given in the following. 1.3.

You will notice that there are four quadrants in your screen. You will want to draw you layouts in the quadrant as figure. There is no specific reason for this other than that you will be more comfortable working with a positive coordinate system.

Drawing Area

The spacing between the snap points is exactly 0.2u because all of our layout for fabrication can have no finer resolution than 0.2um. 1.4

Before creating transistors layout, you may need to zoom out to give necessary space for drawing. In Virtuoso, you can find command Zoom under the menu Window. Allows you to draw a box to zoom in on a specific area. Zooms in on the current window image by a factor of 2. Allows you to draw a box into which you want the current window image to fit. Decreases the current window image by a factor of 2.

Zoom In Zoom In By 2 Zoom Out Zoom Out By 2

Refer to OpenBook for details of command Zoom.

Creating pmso Transistors Layout This part covers the basic steps used to layout a pmos transistor. You'll use polygons to describe most of the transistor geometric. The given geometry dimensions are based on the MOSIS scalable and generic CMOS design rule with lambda = 0.4 micron. You may need to refer to the design rule during design process You will start by drawing the polysilicon gate layer for the pmos transistor. The gate should be 21λ (8.4u) in width and 2λ (0.8u) in length. Step 2.

In the LSW, click on the active (dg) box. This refers to the Active Area drawing layer. (dg stands for drawing). Notice that the top of the LSW now displays the selected layer name. We say that any geometry you draw will be drawn with the selected drawing layer. You can change the selected drawing layer by clicking left on any of the layers in the LSW menu.

2.1

Click on the Rectangle icon from the left menu (short cut icon), OR - Select Create - Rectangle from the pull-down menu.

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2.2

Drawing a rectangle 16λ (6.4u) in width and 21λ (8.4u) in height as following figure. Remind that each snap point on the layout is 0.2um. To do so, you may want to use a ruler. In Virtuoso, Select Misc – Ruler. Click on mouse left button to start a ruler and move the cursor. The end of the ruler gives you the current length. Click again to complete the ruler.

Anytime, you can press the Escape <ESC> key to terminate any drawing command including Ruler. To clear the ruler, select Misc-Clear Ruler. If you have make any mistake, you can delete the unwanted object, highlight the unwanted object and then select Edit – Delete. In addition, you can stretch the object if the size is incorrect. Select Edit-Stretch. Click on the edge of the object you want to stretch, you will see the edge is highlighted. Then click again on the new position where the gate width is 4.4u. Hit <ESC> to exit creates rectangle mode. 2.3.

Next, click left on the poly (dg) box in the LSW window, and using Create>Rectangle, draw a poly rectangle with dimension as shown in figure below, such that it is centered on the active rectangle. (It should overlap this rectangle by 7λ (2.8u) on each side, and the active rectangle should overlap it by 2λ (0.8u) on the top and bottom... this is to satisfy our MOSIS design rules). Congratulations! You have just created your first transistor.

0.8u

0.8u (gate length)

8.4u (gate width)

2.8u 6.4u

Confused? Right now you are probably thinking to yourself "I don't know all those rules, and it takes forever to look them all up". Don't worry about them, Cadence is nice enough to check our design rules for us, as we will see later. Fixing most mistakes is fairly easy. For drawing, a good rule of thumb seems to be that most spacing rules are 0.8um (for example, overlaps, spacing between object of the same shape, etc.). Fixing design rule violations is normally fairly easy. 2.4.

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By now, we have finished drawing a transistor, however, we haven’t specified that it is P-Type. To do so, draw a rectangle using pselect (dg), which overlapped the active of the top transistor by 2λ (0.8u). And then, draw Dept. of ELEC, HKUST

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another nwell (dg) overlapped the pselect. The overlap rule for this is that nwell should overlap active by 6λ (2.4u) as figure. 2.5.

We need to connect nwell to vdd!. To do so, we draw a plug for our Nwell. First, draw a 4λ x 4λ (1.6u) active rectangle. Then, place a nselect (since we are plugging an Nwell) region around the active which will overlap it by 2λ (0.8u) on all sides. Move the well plus to the position as following. Stretch Nwell to overlap it as figure shown.

Well plug

S G B

B D G

S

pselect

D

0.8u p+

p+

n+ nwell

P substrate (i.e. layout window

nwell

Cross section

Current

Performing a Design Rule Check (DRC) Although our inverter is not yet done, let’s perform a design rule check. It’s always a good practice to perform DRC periodically so that you won't finish a large design with many errors. Step 3.

To do a DRC choose Verify-DRC, the DRC form will appear. Click on "OK". Look in the CIW, you should see all the design rules scroll by as they are checked. When it is done you will see something like: ******* Summary of rule violation for cell "inv layout" ******* # errors Violated Rules 4 Active overlap of gate must be at least 3 2 Poly separation to active must be at least 1 6 Total errors found

If you look at your layout, you will see these errors flagged and highlight parts. Lets fix these errors now by referring to the appendix A for detail debugging. 3.1. Re-run the DRC, and make sure your design is correct. Save your design. ELEC301

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Wiring the Transistor You now have finished a pmos transistor, which are design rule passed. As from the schematic, the pmos transistor of our inverter is connected to the power and ground lines, and the well plugs. 4.2. Let’s first create the output node. We cannot connect N-active and P-active directly, so we need to use metal1 to connect them. •

To do so, we need to create 8 active contacts for PMOS and then connect those contacts with metal1. We also will route our power/ground lines in metal1. Refer to figure for detailed position.

•

To drawing an active contact, first draw a 2λ x 2λ (0.8u) rectangle of ca (dg), ca standing for contact for active.

•

Instead of drawing 8 contacts by hand, lets draw one then copy it. To do so, select the contact and issue menu command Edit - Copy. Repeat copy command for another contacts. Notice that the spacing between contacts should be 1.2u.

•

These are your contacts. MOSIS rules say that contact to metal needs to be surrounded by metal1 and active by 2λ (0.8u). Create two metal1 (dg) rectangles, which surrounds the ca (dg) on both sides of PMOS. Run a DRC to ensure this.

•

For the well plug we need to add a contact also, copy and move it into the active of well plus. It should be overlapped by 1λ (0.4u) on each side with active.

4.4. Draw the metal1 rectangles for the Power, which should be 5u in height and at least 10u length. Place it at the upper side of the inverter. 4.5. Stretch the metal1 to touch the power as figure and merge the two metal1. Refer to OpenBook for detail usage of merge. 4.6. By now, you have finished the upper part of the transistor, run a DRC to check it. The complete view should be as following figure:

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Creating nmos Transistor Layout You have just finished the pmos part of the inv. Now, you need to go on finished the nmos part also. The procedure is similar to the pmos one. Step 5

Using the same procedure as drawing pmos transistors, draw another nmos transistor and put in below the pmos transistor with some spaces between them. The gate width of nmos transistor should be 11λ (4.4u) as following figure.

5.1

To specify that this transistor is N-type. Draw a nselect (dg) rectangle (instead of the pselect and nwell) around the transistor. Again there should be a 2λ (0.8um) overlap of the active.

5.2

Similar to well plus to the Pmos transistor, we need to connect p-type substrate contact to gnd!. You may want to copy the well plug you created (including the select area)and then change the nselect rectangle to pselect rantangle. Highlight the nselect rectangle and choose Edit - Properties. The edit properties form appear.

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Notice that one property of the rectangle is its layer, in the Layer field, hold down your mouse button, and choose pselect. Click OK. 5.3

Finished wiring the nmos transistor as in pmso one and run DRC again to ensure that there is no error.

4.4u

Wiring the Inverter You have now finished the two transistors for the inv. The next step is to finished the internal and external connection for the inv.

Input connection Step 6

Connect the two transistors’ poly to become the inverter input. To do so, we can stretch either transistor’s poly to touch the other’s one. Refer to the following figure as the guideline.

6.1

In virtuoso, the two-touched poly will already be considered to be one long poly. However, you may want to merge them to give better appearance. First click on the poly(dg) box in LSW window, highlight the long poly, then select Edit - Other - Merge. The two rectangles will now become one.

6.2

Create Input terminal (Signal name "A"). For external connection point, we want to using metal2 so that it can be accessed in both upward and downward direction. Since we can’t connect poly and metal2 directly, we need to connect poly to metal1 by using cp (dg) first and then connect metal1 to metal2 by using via (dg) via(dg) cp(dg)

•

Draw a 0.8u x 0.8u poly contact in cp (dg). Place it between two transistors.

•

Draw a poly which overlap cp 0.8u on each sides. Metal1 + Metal2

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Poly + Metal1

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•

Draw a 0.8u x 0.8u via (dg) on the left side of cp, then place a metal2 (dg) which overlap via 0.4u.

•

Connecting both via and cp you just created by metal1. It should have 0.8u overlapping to both. Run a DRC to ensure this.

Output Connection 6.3.

Create the output node. Draw a rectangle in metal1 (dg) which overlaps the two metal1 on right side of transistors. Refer to following figure for details.

6.4

Create Output terminal Again, create an external connection point using metal2 and via at the output node.

Labeling 6.4.

Create Power and Ground labels for identification. In LSW, select text (dg). Click on Create - Label. Fill in "vdd!" as the label name, then place it on the top metal1 line as shown in page. Create "gnd!" for the lower metal1 line by the same procedures.

6.5.

Create labels "A" and "Out" as mentioned above. Refer to the figure for label position.

6.6.

Run a final DRC, and save your design.

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The complete inverter layout should resemble the following diagram:

Layer name

Part name Power

metal1

well plus nwell ca active

PNP Transistor

pselect poly Input Terminal

via metal2

NPN Transistor

nselect

P type substrate contact

label

Power

Figure 1 Setting Layer Visibility using the LSW After step 6. You are basically finished the inv layout. However, you may want to check the transistor design in each layer. The layer and Selection Window (LSW) allow you to set particular layers selectable and visible. Step 7.

Move the cursor over the cp (dg) layer in the LSW and click the middle mouse button. The middle mouse button toggles layer visibility. It also automatically sets invisible layers to be unselectable.

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The contact layer colour disappears to show that the layer is invisible, and the layer name turns gray to show that the layer is not selectable. 7.1.

Select Window - Redraw in the inv window. The inv layout is displayed without contacts, since they are drawn on the cp layer.

7.2.

Click on the AV (All Visible) button in the LSW. The coloured square showing the contact layer colour reappears, and the shading on the layer name disappears.

7.3.

Select Window - Redrew in the inv window. The inv layout is re-displayed with cp (dg).You must redraw the window to see the effect of LSW changes. This way you can make several changes before you take the time to redraw a complex design.

7.4

Show you layout to T.A

7.5.

Click on Window - Close, the inv layout will be closed.

End of Lab

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Appendix A: Design Rule Check (DRC) Debugging If you find that there are lots of error appear, don’t be panics. Virtuoso provides an easy environment to fixe the errors. Most common errors are design rule violations, which can be fixed by checking the CIW window. Step 1.

Look at the CIW windows for the errors.

Error type description Space rule in λ

2.

3

Look at the Editing window for the corresponding error parts. Here, there are 2 errors in contact spacing on same active. The space should be 3λ (1.2u). From the editing windows, the space between two ca (dg) is highlight that should correspond to the error.

In addition, you can select Verify-markers-find to find the error marker. Press apply to get the first error marker and so on.

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4

Select verify-markers-Explain to check for error explanation. User mouse to click on the error marker that you want it to be explained.

5

Correct the error and re-run the DRC, make sure your design is correct. Save your design.

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