Illustration Of Substrate Noise Generation In Digital Circuits Using The Example Of An Sram Cell

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Illustration of Substrate Noise Generation in Digital Circuits using the Example of an SRAM Cell Mridula Allani, M2435581, University of Central Florida Abstract—Bulk voltage variations injected due to fast switching of digital circuits is a major obstacle for the integration of analog, RF, and digital circuits on a single die. But with the growing demand for portability and miniaturization, this trend is unavoidable. Hence, suitable modeling of these non-idealities is important for the accurate estimation of the performance of the CMOS circuits. This paper studies the various mechanisms for injection of substrate noise and how the substrate noise affects the performance of digital circuits. The substrate noise generation mechanism is illustrated for an 6T-SRAM cell.

Index Terms—Analog Circuits, Body Effect, Capacitive Coupling, Digital Circuits, Hot Carriers, Impact Ionization, Radio Frequency (RF ircuits, Substrate Current, Substrate Noise.

INTRODUCTION With the down scaling of CMOS technology, the substrate coupling with the various p-n junctions in the CMOS device and with the supply terminals becomes crucial in the analysis of the performance of the various circuits integrated on the same die. The fast switching transients couple with the sensitive analog or RF circuits integrated on the same die and affect their signal-integrity. The process of substrate noise generation and propagation can be described as first spurious fluctuations being injected into the bulk nodes. These voltage variations propagate through the substrate and then finally perceived by the sensitive analog or RF circuits, as shown in figure 1. The various paths in this process are modeled as impedances for the signal flow which alter the substrate voltages. The fluctuations in the substrate voltages decrease the threshold voltage of the MOS devices. This phenomenon is called the body-effect. Due to the decrease in the threshold voltage, leakage currents increase and thus, the power dissipation increases. Various mechanisms leading to the substrate noise injection into the die are discussed in this paper. It is illustrated that the substrate voltage variations affect digital circuits also along with the analog and RF circuits in the deep-sub-micrometer technologies. The CMOS substrate is modeled as a network of resistances and capacitances, as shown in figure 2, to demonstrate

Fig. 1. Substrate crosstalk is due to electrical fluctuations which (A) are generated and locally couple into the substrate, (B) propagate through the substrate and (C)Fig. 2. Three substrate noise coupling mechanisms in an inverter. (1) Impact are received by a sensitive device or circuit. ionization. (2) S/D coupling. (3) Supply coupling.

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the effects of substrate noise injection. This modeling is important in modern CMOS designing to get accurate results by simulations because owing to the enormous integration most of the designing is done using the EDA tools before sending the design to the foundry for the development of a proto-type. These are the phenomenon occurring in practical CMOS circuits which alter the circuit behavior. These phenomena can be partially reduced using various techniques like isolation of substrate from the sensitive analog components using guard-rings, or silicon on insulator techniques, etc. But total elimination of these non-idealities is not possible. Hence, an accurate model accounting for the unexpected behavior of the CMOS circuits so that the simulation results are as close to the practical results as possible. SUBSTRATE NOISE INJECTION MECHANISMS The various sources of bulk voltage fluctuations have been described in this section. A. Impact Ionization When a MOSFET operates in the saturation region, the electric field near the drain increases due to high drain-tosource voltage. Some of the carriers in the channel gain excess energy and get accelerated. These hot carriers collide with the silicon lattice atoms and generate an electron-hole pair. This process is known as impact ionization. The generated electrons move towards the supply terminal of the device. Holes, thus generated, move into the negatively biased substrate. This movement of holes into the substrate generates a substrate current and decreases the bulk potential. This phenomenon is called substrate current induced body-bias effect and it decreases the threshold voltage of the device. Impact ionization current is exponentially dependent on the gate-to-source voltage. At low gate voltages the drainto-source voltage is relatively high and the impact ionization current is independent of the channel length. For higher gate voltages, the electric field is low and thus, the impact ionization current diverges depending on the electric field as a function of voltage for different channel lengths. Also, for long-channel devices, it is straight forward to relate the electric field to the supply voltages. In short-channel devices, the velocity saturation comes into effect and should be considered while relating the electric field to the terminal voltages [1].

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The impact ionization current for a PMOSFET is negligible when compared to that of an NMOSFET. This is due to the capacitive shielding provided by the n-well. B. Capacitive Coupling of the Source, Drain and the Well with the Substrate The source, drain, and the n-well form p-n junctions at the interface with the substrate and produce a depletion region. This depletion region provides the dielectric region to form a capacitive coupling between this terminals and the substrate. Additionally, the gate is coupled to the substrate through the gate oxide and channel capacitances. Thus, the variations in the gate, drain, source voltages due to switching are injected into the substrate through these capacitive impedances. This alters the bulk potential and causes body-effect. The junction capacitances are dependent on the area and perimeters of the respective regions. This capacitive coupling contributes to the majority of the substrate currents and bulk voltage fluctuations in a CMOS transistor. C. Supply Coupling In digital circuits, supply current peaks of the switching gates generate noise in the supply network. This noise capacitively couples with the substrate from VDD via the n-well junction and resistively from VSS via the substrate contacts in a PMOS device. The supply noise consists of common-mode noise and differential-mode noise. Common-mode noise results from the imbalance between supply current and the ground return current when a circuit is driven by the input signal referenced to a power region different from the one of the circuit in consideration. The damped LC tank formed between the circuit capacitance and the supply parasitic produce the differential-mode noise. For typical digital circuits, the number of gates driven by different power regions is very low. Also, the combined effect if the rising and falling switching transitions have a cancelling effect on the common-mode noise. Thus, the differential-mode noise is more dominant mechanism and common-mode noise is negligible. The amount of differential-mode supply noise oscillations can be obtained by analyzing the supply network [2]. D. Gate Induced Drain Leakage (GIDL) Gate-induced drain leakage occurs due to the overlap between the drain and gate regions in the presence of high electric field.this produces a deep depletion region in the drain. When sufficient voltage is achieved across this region, the electrons in the valence band tunnel into the conduction band resulting in hole current into the substrate.

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GIDL exponentially varies with the gate-drain voltage and is highly dependent on the area of overlap between the gate and the drain and the doping level in the drain region. In NMOS devices, GIDL does not come into effect under regular biasing conditions. It has significant effect in the negative gate-to-source bias conditions only. The substrate current due to GIDL is negligible when compared to the impact ionization current. Thus, GIDL has no significant contribution in the overall substrate current injected during NMOS switching. In PMOS devices, GIDL is significantly larger when compared to the drain and well currents for low gatevoltages. However, it is still less than the impact ionization current and in all, GIDL does not contribute significantly to the substrate crosstalk [1]. E. Photon-Induced Current (PIC) The hot carriers generated can alternatively release their energy as a photon emission. These photons generate electron-hole pairs by providing excess energy to the lattice atoms when reabsorbed by the lattice at a distant point. The PIC can affect the bulk nodes situated at farther distances when compared to the minority-carrier recombination length in the case of impact ionization. PIC is dependent on the hot carriers and thus is a function of the bias and device geometry in the same way as impact ionization [1]. F. Diode Leakage Current The drain, source and n-well junctions of a MOSFET forms a reverse biased p-n junction with the substrate. The minority-carrier movement across a reverse-biased p-n junction diode constitutes the diode leakage current. Such currents flow from the drain, source and n-well into the substrate. The substrate current flowing from the n-well is the dominant component as the n-well covers the significant portion of the die. The fluctuations on one side of the diode, i.e., at the drain, source or the n-well can strongly couple with the substrate through reverse-recovery. The diode reverse leakage current depends on the process [1]. EFFECTS OF SUBSTRATE NOISE IN DIGITAL CIRCUITS Typically, the substrate noise generated by the fast switching digital circuits resistively couples with the analog or radio frequency circuits located on the same die of a mixed-signal circuit. Analog and RF circuits are frequency sensitive and their signal- integrity and performance is significantly affected by the bulk voltage fluctuations. Traditionally, the digital circuits were not much affected by the substrate currents and the node fluctuations thus

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generated. But because of continuous scaling of CMOS technology, the device sizes are becoming smaller. The smaller device geometries, mainly the smaller channel lengths and oxide thickness, lower the threshold voltage of the device. Additionally, the supply voltages also scale down with each technology node. Thus, the noise margins for the logic 1 and logic 0 states come increasingly closer. As a result of this decreasing difference between the high and low logic levels, the performance of the digital circuits is becoming more and more sensitive to the substrate noise. Substrate currents generate voltage fluctuations at the bulk node of a transistor. These fluctuations are typically of the order of milli-volts in present CMOS technology. These fluctuations are capable of changing the logic state of the devices. With the decrease in threshold voltage due to the induced body-effect, the transistor might be ON for a supply voltage less than the logic 1 voltage. This can result in the extension of the logic 1 period of the output or decrease the logic 0 period of the output depending on the previous state of the output node. Thus, we see that the substrate crosstalk will result in erroneous toggles and timing faults in digital circuits [4]. Additionally, in the deep sub-micrometer technologies the decreasing supply voltage, decreasing wire spacing and enhanced signal slew rate, capacitive and also inductive cross coupling between adjacent interconnects will increase the noise levels and affect the digital circuits [3]. We have considered the SRAM cell to illustrate the bulk-node fluctuations of the NMOS and PMOS devices. SRAM arrays are stacked in huge numbers to provide the giga-bytes of memory required for today’s computing devices. Thus, the performance of SRAM cell is crucial towards defining the performance of the whole computational system. DESIGN DESCRIPTION The SRAM cell consists of four NMOSFETs and two PMOSFETs. The bulk terminals of the PMOS devices are capacitively coupled to the VDD supply through a series resistance and the bulk terminals of the PMOS devices are capacitively coupled to the VSS supply through a series resistance. A 1.67 GHz clock is fed to the WORD line and a similar clock is used to feed the BIT line. The latter clock is also fed to an inverter, to supply the BITBAR signal. This inverter is made of an NMOS device which capacitively couples to the substrate at the source and drain nodes and resistively at the bulk node. The PMOS device constituting the inverter is capacitive coupled to the n-well and

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Fig. 3. Schematic Diagram of the Simulated SRAM Cell.

the n-well is again capacitively coupled to the substrate. The bulk node of the PMOSFET is resistively coupled with the n-well and capacitively with the substrate. Additionally, the substrate is capacitively coupled to the VDD and VSS. The output of the inverter is fed to the BITBAR line of the SRAM cell directly. Again, the bulk nodes of the inverter are resistively coupled with the bulk nodes of the SRAM cell through the substrate. The power supply parasitics are modeled as the resistance and inductance of the bonding wires and a decoupling capacitance between supply and ground. Typical values for the various passive components are used for modeling the substrate noise generation mechanism [1]. The resistance between the supplies and the substrate, well and the substrate, NMOS bulk and the substrate and bonding wire resistances are taken as 1 ohm. The source drain junction capacitances are taken as 10fF. And the capacitances between the well and the substrate and PMOS bulk and the substrate and the power supplies and substrates are assumed to be 1nF. The decoupling capacitance at the power supply is taken to be 270pF. VDD = 1.8V and VSS = -1.8V are taken. The NMOS devices of channel length .18 microns and width of 1.1 micron are used for simulations. The PMOS devices used have a width of 2 microns and length same as the NMOSFET.

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BSIM 3V3.1 model has been used to simulate each of the devices. Orcad PSPICE is used to simulate the circuit. SIMULATION RESULTS AND OBSERVATIONS The currents at the bulk nodes of the NMOS and PMOS devices have been plotted as a function of time. The nodes are shown by the current markers shown in the circuit diagram. Also, the voltages at the bulk terminals are plotted as function of time. The terminals are represented as VNB and VPB in the circuit corresponding to the NMOS and PMOS device. The voltages at the output nodes of an SRAM cell have also been plotted.

Fig. 4. Schematic Diagram of the Simulated SRAM Cell. The NMOS Bulk Nodes where the Substrate Currents have been measured are shown by the current markers.

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Fig. 5. The NMOS Substrate Currents shown by the current markers in figure 4.

Fig. 6. The NMOS Substrate Voltage Fluctuations.

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Fig. 7. Schematic Diagram of the Simulated SRAM Cell. The PMOS Bulk Nodes where the Substrate Currents have been measured are shown by the current markers.

Fig. 8. The PMOS Substrate Currents shown by the current markers in figure 7.

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Fig. 9. The PMOS Substrate Voltage Fluctuations.

Fig. 10. The SRAM Output Node1 Fluctuations.

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Fig. 11. The SRAM Output Node2 Fluctuations.

We observe that the substrate current flowing into the bulk terminal of the NMOS devices is in between ±1 mA with occasional peaks of up to 8mA. For the PMOS device the currents oscillate between ±0.5 mA. Also the current fluctuates about the 0A. The bulk voltage fluctuations for both the devices are in the order of 0.1mV. We also observe that the output voltages of the SRAM do not have sharp transitions between the logic levels and also the hold-state of a particular logic level is affected. We now plot the leakage current of the circuit by varying the length of the transistors by keeping the W/L ratio constant and then varying the device threshold voltage at zero bulk voltage conditions and the drain-to-source voltage.

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(a)

(b)

(c) Fig. 11. The leakage Current Dependence on (a) Length of the device (b) Threshold voltage of the device at zero body-bias condition (c) VDS

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It can be seen that the leakage currents increase as the length of the device decreases and the threshold voltage at zero body bias condition decreases. It is also observed that the leakage currents increase with the increase in supply voltage. CONCLUSIONS The substrate noise is a limitation for the performance of not only analog and RF CMOS circuits, but also the digital circuits. This noise causes unexpected toggles and delays in digital circuits and also affects the signal-integrity of the circuit. We have illustrated the node fluctuation of the bulk terminals of an SRAM cell. Further study on the performance of SRAM cell subjected to substrate voltage variations can be done in terms of delay and logic level. Also, the increase in substrate currents in large SRAM arrays can be illustrated by stacking multiple numbers of SRAM cells in a similar fashion shown in this paper. REFERENCES [1] J. Briaire and K. S. Krisch, “Principles of substrate crosstalk generation in CMOS circuits,” IEEE Trans. Computer-Aided Design, vol. 19, pp. 645–653, June 2000.

[2] M. Badaroglu, P. Wambacq, G. Van der Plas, S.Donnay, G.G. E. Gielen, and H. J. De Man,” Evolution of Substrate Noise Generation Mechanisms With CMOS Technology Scaling” , IEEE Transactions on Circuits and Systems, vol. 53, No. 2,pp. 296-304, February 2006. [3] Chr. Werner, R.Göttsche, A. Wörner, and U. Ramacher, “ Crosstalk Noise in Future Digital CMOS Circuits”, Infineon Technologies, Corporate Research, Munich. [4] M. Nagata, J. Nagai, K. Hijikata, T. Morie, and A. Iwata, “Physical Design Guides for Substrate Noise Reduction in CMOS Digital Circuits” , IEEE Journal of Solid-State Circuits, vol. 36, No. 3,pp. 539-549, March 2001. [5] R. Gharpurey and R. G. Meyer, “Modeling and analysis of substrate coupling in integrated circuits,” IEEE J. Solid-State Circuits, vol. 31, pp. 344–353, Mar. 1996. [6] J. Briaire and K. S. Krisch, “Substrate injection and crosstalk in CMOS Circuits,” in Proc. 1999 IEEE Custom Integrated Circuits Conf., pp. 483–486, 1999. [7] D. K. Su, M. J. Loinaz, S. Masui, and B. A. Wooley, “Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits,” IEEE J. Solid-State Circuits, vol. 28, pp. 420–430, Apr. 1993. [8] K. Joardar, “A simple approach to modeling cross-talk in integrated circuits,” IEEE J. Solid-State Circuits, vol. 29, pp. 1212–1219, Oct. 1994.

14 [9] E. Charbon, P. Miliozzi, L. P. Carloni, A. Ferrari, and A. Sangiovanni- Vincentelli, “Modeling digital substrate noise injection in mixed-signal ICs,” IEEE Trans. Computer-Aided Design, vol. 18, pp. 301–310, Mar. 1999. [10]

R. M. Secareanu, S. Warner, S. Seabridge, C. Burke, J. Becerra, T. E. Watrobski, C. Morton, W. Staub, T.

Tellier, I. S. Kourtev, E. G. Friedman, ”Substrate Coupling in Digital Circuits in Mixed- Signal Smart-Power Systems”, IEEE Trans. VLSI, vol. 12, pp. 67-78, Jan 2004. [11] M. van Heijningen et al., “Substrate Noise Generation in Complex Digital Systems: Efficient Modeling and Simulation Methodology and Experimental Verification”, IEEE Journal of Solid- State Circuits, vol. 37, pp. 1065-1072, 2002. [12] X. Aragones, J. L. Gonzales, and A. Rubio, “Substrate coupling trends in future CMOS technologies,” in Proc. 7th Int.Workshop on Power and Timing Modeling, Optimization and Simulation, pp. 235–244, September 1997. [13]

M. Badaroglu, P. Wambacq, G. Van der Plas, S. Donnay, G. Gielen, and H. De Man, “Impact of technology scaling on substrate noise generation mechanisms,” in Proc. IEEE Custom Integrated Circuits Conf., pp. 501– 504, ., Oct. 2004.

[14] S. Kristiansson, S. P. Kagganti, T. Ewert, F. Ingvarson, J. Olsson, and K. O. Jeppson, “Substrate resistance modeling for noise coupling analysis,” in Proc. IEEE Int. Conf. on Microelectronic Test Structures, pp. 124–129, Mar. 2003 [15] BSIM3 Manual [Online]. Available: http://www-device.eecs.berkeley. edu/~bsim