Hyper Threading Of Intel

Introduction Ways To Enhance Performance-  Increase in clock rate o By reducing clock cycle time o Performance increased by increasing number of instructions executed per second o H/w limitations limit this feature

Introduction Ways To Enhance Performance-  2. Cache

hierarchies

o By using cache memories o Frequently used data is put in caches o Reduces average accesses time

Introduction Ways To Enhance Performance-  2. Pipelining

o Multiple instructions are overlapped in execution o Limited by instructions

the

dependencies

o Basis for multi-threading.

between

Instruction Level Parallelism To increase the number of instructions executed in each clock cycle. It should be possible to simultaneously execute instructions.

Thread level parallelism Chip Multi Processing o Two or more processors o Each has full set of execution and architectural resources,. o Are put together in a single die.

Thread level parallelism Time Slice Multi Threading o Only one processor o Multiple threads executed by switching

Thread level parallelism Switch on Event Multi Threading o Switch threads on long latency events such as cache misses

Hyper-Threading Technology Hyper-Threading Technology first invented by Intel Corp. Brings the simultaneous multi-threading approach to the Intel architecture. A single physical processor appears like two or more logical processors

Hyper-Threading Technology Provides thread-level-parallelism (TLP) on each processor TLP results in increased utilization of processor and execution resources. Each logical processor maintain one copy of the architecture state

Hyper-Threading Technology Architectu Arch State

Processor Execution Resources

Processor with out HyperThreading Technology

Arch State

Arch State

Processor Execution Resources

Processor with HyperThreading Technology

Sharing of Resources         Major Sharing Schemes areo Partition o Threshold o Full Sharing

Partition

     Each logical processor uses half the resources       Simple and low in complexity       Ensures fairness and progress       Good for major pipeline queues 

Partitioned Queue Example  Yellow

thread – It is faster thread  Green thread – It is slower thread

Threshold   

Puts a threshold on number of resource entries a logical processor can use.



Limits maximum resource usage



For small structures where resource utilization in burst and time of utilization is short, uniform and predictable



  E g - Processor Scheduler

Full Sharing   

  Most flexible mechanism for resource sharing, do not limit the maximum uses for resource usage for a logical processor



 Good for large structures in which working set sizes are variable and there is no fear of starvation



  E g : All Processor caches are shared

Single-Task & Multi-Task Modes

SINGLE-TASK AND MULTI-TASK MODES

Operating system  For

best performance, the operating system should implement two optimizations. ◦ The first is to use the HALT instruction if one logical processor is active and the other is not. HALT will allow the processor to transition MT mode to either the ST0- or ST1-mode. ◦ The second optimization is in scheduling software threads to logical processors. The operating system should schedule threads to logical processors on different physical processors before scheduling two threads to the same physical processor.

Business Benefits of Hyper-Threading Technology  Higher

transaction rates for e-Businesses

 Improved

reaction and response times for end-users and customers.

 Increased

number of users that a server system can support

 Handle

increased server workloads

 Compatibility

with existing server applications and operating systems

Limitations  Hyper-Threading

technology cannot beat dual processors in terms of performance.  Performance to cost ratio is much higher.  Hyper-Threading does not get 2x faster, but neither do dual CPU systems

Conclusion •

Intel’s Hyper-Threading Technology brings the concept of simultaneous multi-threading to the Intel Architecture.

•

It will become increasingly important going forward as it adds a new technique for obtaining additional performance for lower transistor and power costs.

•

The goal was to implement the technology at minimum cost while ensuring forward progress on logical processors, even if the other is stalled, and to deliver full performance even when there is only one active logical processor.

References 

“HYPER-THREADING TECHNOLOGY ARCHITECTURE AND MICROARCHITECTURE” by Deborah T. Marr, Frank Binns, David L. Hill, Glenn Hinton,David A. Koufaty, J. Alan Miller, Michael Upton, intel Technology Journal, Volume 06 Issue 01, Published February 14, 2002. Pages: 4 –15.



“:HYPERTHREADING TECHNOLOGY IN THE NETBURST MICROARCHITECTURE” by David Koufaty,Deborah T. Marr, IEEE Micro, Vol. 23, Issue 2, March–April 2003. Pages: 56 – 65.



http://cache-www.intel.com/cd/00/00/22/09/220943_220943.pdf



http://www.cs.washington.edu/research/smt/papers/tlp2ilp.final.pdf



http://mos.stanford.edu/papers/mj_thesis.pdf