High Speed Downlink Packet Hsdpa

Overview  What is HSDPA ?? HSDPA physical layer structure Comparison between different technologies Advantages of HSDPA Implementation of HSDPA

HSDPA      

Stands for High speed downlink packet access The protocol is used to increase : download packet data throughput the data transfer speeds the capacity of the packet data Current HSDPA deployment supporting speed is about 14.4 Mbps  The rate of throughput is very close to 1 Mbps  Backward compatible with UMTS (data rate 220 Kbps to 330 Kbps for multimedia messages)

HSDPA physical layer structure 3 new channels introduced in the physical layer of HSDPA i.e.

I.

High speed downlink shared channel (HS-DSCH)   

II.

Carries information in the downlink direction Maximum peak rate is up to 10 Mbps Shorter frame of about 2ms

High speed Shared Control Channel (HS-SCCH)  

Used to carry the important information about the physical layer controls to enable decoding of the date on HSDSCH Also used for combining the data which is sent over HSDSCH in the case of retransmission of the corrupted packet.

III. Uplink High-Speed Dedicated Physical Control Channel (HS-DPCCH)  

Different from the above two channels Carries data in the uplink namely ARQ acknowledgement (both positive and negative ones)

Comparison Table Parameter

Fixed WiMAX

Mobile WiMAX

HSDPA

Wi-Fi

Standard

IEEE 802.16

IEEE 802.16e

3GPP

IEEE 802.11a/g/n

Peak down link data rate

9.4Mbps in 3.5MHz with 3:1 DL-to-UL ratio TD

46Mbps with 3:1 DL- to-UL ratio TDD

Peak uplink data rate

3.3Mbps in 3.5MHz using 3:1 DL-to-UL ratio

7Mbps in 10MHz using 3:1 DL-to-UL ratio

1.4Mbps initially; 5.8Mbps later

Bandwidth

3.5MHz and 7MHz in 3.5GHz band;

3.5MHz, 7MHz, 5MHz, 10MHz, and 8.75MHz initially

5MHz

20MHz for 802.11a/g; 20/40MHz for 802.11n

Coverage

3–5 miles

< 2 miles

1–3 miles

< 100 ft indoor

Multiplexing

TDM

TDM/OFDMA

TDM/CDMA

CSMA

14.4Mbps

54 Mbps shared using 802.11a/g

Advantages  Speed 

 

Supports services which requires instantaneous high data rates in the downlink e.g. Internet browsing , video on demand Offering data rates up to 10 Mbps Peak data rates many times higher than current 3G  14 Mbps (theoretical) but the actual speed depends on the channel conditions

 Capacity  

Improves capacity 3-4 times at relatively low cost 100 – 200% improvement for the best effort packet data

 Reduced round trip delay  

Round trip times can be reduced below 100 ms Quicker response with high interactive services

 Improved end user quality  Deployed in both time division duplex (TDD) and in frequency division duplex (FDD)  Improves overall efficiency when interacting with higher layer protocols

Implementation of HSDPA using FPGA •

Channel coding scheme in HSDPA

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Of the many features implemented by the FPGA’s we will explain in the detail the use of the FPGA for implementing the following: Turbo coding: consists of an interleaver and the two recursive convolutional encoders which is very easy to implement in both software and in hardware but the interleaver creates problem with the implementation due to some variability. The biggest problem with the implementation is that the block size from 40 to 5114 is supported but the block size varies about 2ms for every Transmission Time Interval (TTI) that adds the latency in the digital signal processor . Therefore we can say that the turbo encoder can be easily implemented on the FPGA, also this method removes the need for calculating separate LUT for the interleaver.

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Coprocessor features •

The HSPDA implementation is extremely small and fits nicely into a low-cost Spartan™-3 devices. This is an efficient way to add HSDPA to an existing 3GPP compliant solution

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The HSDPA is used as a coprocessor to upgrade existing systems and process three sectors to provide 14.4 Mb/s bandwidth to each sector. Also from the above figure we can see that the FPGA device can be easily coupled to any other peripheral thus bringing down the cost of the overall system. Also, Altera has developed design tools and methodologies that enable you to develop FPGA co processing solutions using Altera’s Stratix® II, Stratix , and Cyclone devices

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