High--speed Digital Ic Design.pdf

ECE 225 High-Speed Digital IC Design Lecture 3

Prof. Kaustav Banerjee Electrical and Computer Engineering E-mail: [email protected]

Lecture 3, ECE 225

Kaustav Banerjee

The Diode B

A

Al

SiO2

p n Cross-section of pn-junction in an IC process A

Al A

p n

B

B One-dimensional representation

diode symbol

Mostly occurring as parasitic element in Digital ICs Lecture 3, ECE 225

Kaustav Banerjee

Diode Current Current increases by a factor of 10 every 60 mV

Ideal diode equation: ID= diode current, VD=diode bias voltage IS= saturation current of diode (constant) proportional to diode area, and function of the doping levels and width of neutral regions

ΦT=thermal voltage =kT/q=26mV at 300K

Lecture 3, ECE 225

Kaustav Banerjee

Diode Model RS

series resistance due to the neutral regions on both sides of the junction

+ VD

ID

CD = Cj + Cd

Non-linear current source

ID = IS exp[VD/nφT ] – 1 n is called the emission co-efficient = 1 for most common diodes but can be greater than 1 for others Lecture 3, ECE 225

Kaustav Banerjee

Secondary Effects

ID (A)

0.1 Reverse bias increases electric field across the junction and carriers crossing the junction get accelerated and attain high velocity.

0

–0.1 –25.0

–15.0

–5.0

0

VD (V)

5.0

At E=Ecrit = 2x105 V/cm, carriers create e-h pairs on collision with immobile Si atoms. These carriers in turn create more carriers….

Avalanche Breakdown Lecture 3, ECE 225

Kaustav Banerjee

SPICE Parameters

Lecture 3, ECE 225

Kaustav Banerjee

MOS Transistors Types and Symbols D

NMOS

D

G

G S

S

NMOS with Body Contact

D

PMOS

B

For NMOS: Body tied to Gnd

G

For PMOS: Body tied to Vdd Why? S

Lecture 3, ECE 225

Kaustav Banerjee

MOS Transistor ‰

Important transistor physical characteristics ƒ Channel length L ƒ Channel width W ƒ Thickness of oxide tox

W tox L

Lecture 3, ECE 225

Kaustav Banerjee

MOS Transistor Operation ‰

Simple case: VD = VS = VB = 0 ƒ Operates as MOS capacitor

‰

When VGS
‰

VT0 is known as the threshold voltage Vg < VT0 Vs=0

Vd=0

source

drain

depletion region

P-substrate VB = 0 Lecture 3, ECE 225

Kaustav Banerjee

MOS Transistor Operation When VGS > VT0, inversion layer forms ‰ Source and drain connected by conducting ntype layer (for NMOS) ‰

Vg > VT0 Vs=0

Vd=0

source

drain

depletion region

P-substrate inversion layer

VB = 0 Lecture 3, ECE 225

Kaustav Banerjee

Physical Parameters that Affect VT0 ‰

Threshold voltage (VT0): voltage between gate and source required for inversion ƒ NMOS Transistor is “off” when VGS < VT0

‰

Components: ƒ Work function difference between gate and channel (Flat-band voltage) ƒ Gate voltage to change surface potential ƒ Gate voltage to offset depletion region charge ƒ Gate voltage to offset fixed charges in gate oxide and in silicon-oxide interface Lecture 3, ECE 225

Kaustav Banerjee

Threshold voltage, summary ‰

If VSB = 0 (no substrate bias): VT 0 = Φ GC

‰

QB 0 Qox − 2φ F − − Cox Cox

If VSB ≠ 0 (non-zero substrate bias) VT = VT 0 + γ

‰

(

− 2φ F + VSB − 2φ F

Body effect (substrate-bias) coefficient: 2qN Aε Si γ= Cox

‰

)

+ for NMOS - for PMOS

Threshold voltage increases as VSB increases! Lecture 3, ECE 225

Kaustav Banerjee

Threshold Voltage (NMOS vs. PMOS) NMOS

PMOS

Substrate Fermi potential

φF < 0

φF > 0

Depletion charge density

QB < 0

QB > 0

Substrate bias coefficient

γ>0

γ<0

Substrate bias voltage

VSB > 0

VSB < 0

Threshold voltage

VT0 > 0

VT0 < 0

(enhancement devices)

Lecture 3, ECE 225

Kaustav Banerjee

Threshold voltage adjustment ‰ ‰

Threshold voltage can be changed by doping the channel region with donor or acceptor ions For NMOS: ƒ VT increased by adding acceptor ions (p-type) ƒ VT decreased by adding donor ions (n-type) ƒ Opposite for PMOS

‰

Approximate change in VT0: ƒ Density of implanted ions = NI [cm-2] ƒ Assume all implanted impurities are ionized

∆VT 0

qN I = Cox Lecture 3, ECE 225

Kaustav Banerjee

Example: VT0 Adjustment ‰

Consider an NMOS device: ƒ ƒ ƒ ƒ ƒ

P-type substrate: NA = 2 x 1016 cm-3 Polysilicon gate: ΦGC = -0.92V tox = 600 Å (1Å = 1 x 10-8 cm) Nox = 2 x 1010 cm-2 εSi = 11.7 ε0, εox = 3.97 ε0

‰

(a) Find VT0

‰

(b) Find amount and type of channel implant to get VT0 = 0.4 V Lecture 3, ECE 225

Kaustav Banerjee

The Body Effect 0.9 0.85 0.8 0.75

0.65

T

V (V)

0.7

0.6 0.55 0.5 0.45 0.4 -2.5

-2

-1.5

-1

V

BS

-0.5

0

(V)

Lecture 3, ECE 225

Kaustav Banerjee

Transistor Currents (NMOS) Cutoff Region: Ids = 0, Vgs
v = µE

Linear Region: Vgs> Vt, Vds< Vgs-Vt

E = Vds/L

Ids = µ Cox W/L (Vgs-Vt-Vds/2)Vds

β = µ Cox W/L

Saturation Region: Vgs>Vt, Vds > Vgs – Vt Ids = β/2 (Vgs-Vt)2 Note: for PMOS Vtp = Vtn

µp < µn, hence (W/L)PMOS ~ 2 (W/L)NMOS Lecture 3, ECE 225

Kaustav Banerjee

NMOS Characteristics

Quadratic Relationship

Lecture 3, ECE 225

Kaustav Banerjee

PMOS Characteristics

Lecture 3, ECE 225

Kaustav Banerjee

Channel Length Modulation ‰

In saturation, pinch-off point moves ƒ As VDS is increased, pinch-off point moves closer to source ƒ Effective channel length becomes shorter ƒ Current increases due to shorter channel

L = L − ∆L '

W 2 I D = µ nCox (VGS − VTN ) (1 + λVDS ) L 1 2

λ = channel length modulation coefficient Lecture 3, ECE 225

Kaustav Banerjee

Summary: MOS I/V I/V curve for NMOS device: VDS = VGS-VT

Drain current IDS

VGS3

Linear

VGS2 VGS1

with channel-length modulation without channellength modulation (λ=0)

Saturation Drain voltage VDS Lecture 3, ECE 225

Kaustav Banerjee

Current-Voltage Relations Short-Channel Transistors 2.5

x 10

-4

VGS= 2.5 V

Early Saturation 2

VGS= 2.0 V ID (A)

1.5

VGS= 1.5 V

1

0.5

0

Linear Relationship

VGS= 1.0 V

0

0.5

1

1.5

2

2.5

VDS (V)

Lecture 3, ECE 225

Kaustav Banerjee

υ n (m/s)

Velocity Saturation υsat = 105 Constant velocity

Constant mobility (slope = µ)

ξc = 1.5 Lecture 3, ECE 225

ξ (V/µm) Kaustav Banerjee

Perspective ID Long-channel device VGS = VDD Short-channel device

V DSAT

VGS - V T Lecture 3, ECE 225

VDS Kaustav Banerjee

ID versus VGS -4

6

x 10

-4

x 10 2.5

5

2

4

linear

quadratic

ID (A)

ID (A)

1.5

3

1

2

0.5

1 0 0

quadratic 0.5

1

1.5

2

2.5

0 0

VGS(V)

0.5

1

1.5

2

2.5

VGS(V)

Long Channel

Short Channel

Lecture 3, ECE 225

Kaustav Banerjee

ID versus VDS -4

6

-4

x 10

VGS= 2.5 V

x 10 2.5

VGS= 2.5 V

5

2

Resistive Saturation

ID (A)

VGS= 2.0 V

3

VDS = VGS - VT

2

1

VGS= 1.5 V

0.5

VGS= 1.0 V

VGS= 1.5 V

1 0 0

VGS= 2.0 V

1.5

ID (A)

4

VGS= 1.0 V 0.5

1

VDS(V)

1.5

2

2.5

0 0

Long Channel

0.5

1

VDS(V)

1.5

2

Short Channel Lecture 3, ECE 225

Kaustav Banerjee

2.5

Simple Model versus SPICE 2.5

x 10

VDSAT = L vsat/µn

-4

VDS=VDSAT 2

Velocity Saturated

ID (A)

1.5

Linear 1

VDSAT=VGT 0.5

VDS=VGT 0

0

0.5

Saturated 1

1.5

2

2.5

Spice

VDS (V) Lecture 3, ECE 225

Kaustav Banerjee

A PMOS Transistor (short-channel) -4

0

x 10

VGS = -1.0V -0.2 VGS = -1.5V

ID (A)

-0.4

-0.6

-0.8

-1 -2.5

VGS = -2.0V

Assume all variables negative!

VGS = -2.5V

-2

-1.5

-1

-0.5

0

VDS (V)

Lecture 3, ECE 225

Kaustav Banerjee

Dynamic Behavior of MOS Transistor G

‰

Oxide Capacitance ƒ Gate to Source overlap ƒ Gate to Drain overlap ƒ Gate to Channel/Bulk

‰

CGS

CGD D

S

Junction Capacitance ƒ Source to Bulk junction ƒ Drain to Bulk junction

Lecture 3, ECE 225

CGB

CSB

CDB

B

Kaustav Banerjee

Oxide capacitances

Overlap

source

Ldrawn

drain

XD ‰

Overlap capacitances ƒ ƒ ƒ ƒ

gate electrode overlaps source and drain regions XD is overlap length on each side of channel Leff = Ld – 2XD Total overlap capacitance:

Coverlap = CGSO + CGDO = 2CoxWX D

Lecture 3, ECE 225

Kaustav Banerjee

Oxide capacitances Channel ‰

Channel capacitances ƒ Gate-to-source: Cgs ƒ Gate-to-drain: Cgd ƒ Gate-to-bulk: Cgb

‰

Cgs source

Cgd Cgb

drain

Cutoff: ƒ ƒ ƒ ƒ

No channel connecting source and drain Cgs = Cgd = 0 Cgb = CoxWLeff Total channel capacitance CGC = CoxWLeff

Lecture 3, ECE 225

Kaustav Banerjee

Oxide capacitances Channel

‰Linear mode ƒ Channel spans from source to drain ƒ Capacitance split equally between S and D 1 CGS = C oxWLeff 2

1 CGD = C oxWLeff 2

CGB = 0

– Total channel capacitance CGC = CoxWLeff

‰Saturation mode – Channel is pinched off: CGD = 0

2 CGS = C oxWLeff 3

CGB = 0

– Total channel capacitance CGC = 2/3 CoxWLeff Lecture 3, ECE 225

Kaustav Banerjee

Gate-to-Channel Capacitance (summary) G

G CGC

CGC D

S

G

Cut-off

S

CGC D

CGC = CResistive gb + Cgs + Cgd

D

S

Saturation

Resistive

Lecture 3, ECE 225

Kaustav Banerjee

Gate-to-Channel Capacitance

CG C

WLC ox

WLC ox 2

CGC B

VT

C G CS = CG CD

WLC ox

CG C 2WLC ox

CG CS

3

WLC ox CGCD

2

VG S

Capacitance as a function of VGS (with VDS = 0)

0

1

VDS /( VG S-VT)

Capacitance as a function of the degree of saturation

Bottom Line: Cap. components are non-linear Lecture 3, ECE 225

Kaustav Banerjee

Diffusion Capacitance Channel-stop implant N A+ Side wall Source ND

W

Bottom

xj

Side wall LS

Channel Substrate N A

Lecture 3, ECE 225

Kaustav Banerjee

Junction Capacitance

Lecture 3, ECE 225

Kaustav Banerjee

Linearizing the Junction Capacitance Replace non-linear capacitance by large-signal equivalent linear capacitance which displaces equal charge over voltage swing of interest

Lecture 3, ECE 225

Kaustav Banerjee

Capacitances in 0.25 µm CMOS process

Lecture 3, ECE 225

Kaustav Banerjee

Data Dependency

Lecture 3, ECE 225

Kaustav Banerjee

MOS Cap. Summary

Lecture 3, ECE 225

Kaustav Banerjee

Alpha-Power MOSFET Model Ids ∝ (Vgs – Vt)α 1<α<2

Lecture 3, ECE 225

Kaustav Banerjee

Subthreshold Leakage

• Dominant leakage mechanism • Increases exponentially with temperature and Vt

Lecture 3, ECE 225

Kaustav Banerjee

Gate Leakage •Increases with gate oxide (SiO2) scaling •High-k gate oxides can be used to lower gate leakage •Independent of temperature

Lecture 3, ECE 225

Kaustav Banerjee

Junction Leakage

•Less significant than gate and subthreshold leakage •Increases with temperature

Lecture 3, ECE 225

Kaustav Banerjee

Temperature Effects •Mobility decreases with increase in T •Vt decreases linearly with T

Lecture 3, ECE 225

Kaustav Banerjee

Temperature Effects

Lecture 3, ECE 225

Kaustav Banerjee

Temperature Effects Chip Cooling can: 1. Improve Circuit performance •

speed up transistors

•

decrease the delay of interconnects since metal resistance decreases with temperature

•

Lowers junction capacitance (increases depletion width)

2. Decrease leakage (mainly subthreshold) 3. Improve reliability of the chip

Lecture 3, ECE 225

Kaustav Banerjee

The Sub-Micron MOS Transistor ‰ Threshold

Variations ‰ Subthreshold Conduction/Leakage ‰ Parasitic Resistances

Lecture 3, ECE 225

Kaustav Banerjee

Threshold voltage variation ‰

Until now, threshold voltage assumed constant ƒ VT changed only by substrate bias VSB

‰ ‰

‰

In threshold voltage equations, channel depletion region assumed to be created by gate voltage only Depletion regions around source and drain neglected: valid if channel length is much larger than depletion region depths In short-channel devices, depletion regions from drain and source extend into channel

Lecture 3, ECE 225

Kaustav Banerjee

Threshold voltage variation Short-channel effects cause threshold voltage variation: ‰

VT rolloff

ƒ As channel length L decreases, threshold voltage decreases

‰

Drain-induced barrier lowering ƒ As drain voltage VDS increases, threshold voltage decreases

‰

Hot-carrier effect

ƒ Threshold voltages drift over time ‰

Negative-Bias Temperature Instability (NBTI) ƒ ƒ ƒ ƒ

Issue in PMOS transistors Vt drifts over time Typical stress temperature 100-150 C Typical oxide electric fields of 5-6 MV/cm

Lecture 3, ECE 225

Kaustav Banerjee

Threshold voltage variation Source depletion region

N+ source

N+ drain

Drain depletion region

Gate-induced depletion region

Even with VGS=0, part of channel is already depleted ‰ Bulk depletion charge is smaller in shortchannel device → VT is smaller ‰

Lecture 3, ECE 225

Kaustav Banerjee

Threshold voltage variation ‰ Change

in VT0:

ƒ xdS, xdD: depth of depletion regions at S, D ƒ xj: junction depth 1 ∆VT 0 = Cox

⎞⎤ ⎞ ⎛ x j ⎡⎛⎜ x 2 xdS 2 dD ⎢ 1+ − 1 ⎟⎥ 2qε Si N A 2φ F • −1⎟ + ⎜ 1+ ⎟⎥ ⎟ ⎜ xj xj 2 L ⎢⎜⎝ ⎠⎦ ⎝ ⎠ ⎣

• ∆VT0 is proportional to (xj/L) – For short channel lengths, ∆VT0 is large – For large channel lengths, term approaches 0 Lecture 3, ECE 225

Kaustav Banerjee

Threshold voltage variations Graphically: VT0 versus channel length L VT0

Long-channel VT

Lnom

L

VT Roll-off: VT decreases rapidly with channel length Lecture 3, ECE 225

Kaustav Banerjee

DIBL ‰

Drain-induced barrier lowering (DIBL) ƒ Drain voltage VDS causes change in threshold voltage ƒ As VDS is increased, threshold voltage decreases

‰

Cause: depletion region around drain ƒ Depletion region depth around drain depends on drain voltage ƒ As VDS is increased, drain depletion region gets deeper and extends further into channel ƒ For very large VDS, source and drain depletion regions can meet → punch-through!

‰

Issue: results in uncertainty in circuit design

Lecture 3, ECE 225

Kaustav Banerjee

Threshold Variations VT

VT

Low VDS threshold

Long-channel threshold

VDS

L Threshold as a function of the length (for low VDS )

Drain-induced barrier lowering (DIBL) (for low L)

Lecture 3, ECE 225

Kaustav Banerjee

Threshold voltage variation ‰ Hot-carrier

effect

ƒ increased electric fields causes increased electron velocity ƒ high-energy electrons can tunnel into gate oxide ƒ This changes the threshold voltage (increases VT for NMOS) ƒ Can lead to long-term reliability problems

Lecture 3, ECE 225

Kaustav Banerjee

Threshold voltage variation ‰

Hot electrons ƒ High-velocity electrons can also impact the drain, dislodging holes ƒ Holes are swept towards negatively-charged substrate → cause substrate current ƒ Called impact ionization ƒ This is another factor which limits the process scaling → voltage must scale down as length scales

Lecture 3, ECE 225

Kaustav Banerjee

Threshold voltage variations ‰

Summary of threshold variations in shortchannel devices ƒ VT rolloff: threshold voltage reduces as channel length L reduces ƒ DIBL: threshold voltage reduces as VDS increases ƒ Hot-carrier effect: threshold voltage drifts over time as electrons tunnel into oxide ƒ NBTI—causes Vt increase in PMOS transistors, strong dependence on Temperature.

Lecture 3, ECE 225

Kaustav Banerjee

Sub-threshold conduction (1) ‰

When VGS < VT, transistor is “off”

ƒ However, small drain current ID still flows ƒ Called subthreshold leakage current

‰

Model for subthreshold current:

I D ( subthreshold ) = I SWe

q ( AVGS + BVDS ) kT

ƒ Increases as VGS increases (potential barrier lowered) ƒ Increases as VDS increases (DIBL)

Lecture 3, ECE 225

Kaustav Banerjee

Sub-Threshold Conduction (2) -2

The Slope Factor

10

Linear -4

I D ~ I 0e

10

-6

ID (A)

10

Quadratic

qVGS nkT

CD , n = 1+ Cox

S is ∆VGS for ID2/ID1 =10

-8

10

-10

Exponential

-12

VT

10

10

0

0.5

1

1.5

2

VGS (V)

Lecture 3, ECE 225

2.5

Typical values for S: 60 .. 100 mV/decade Kaustav Banerjee

Sub-Threshold ID vs VGS I D = I 0e

qVGS nkT

qV − DS ⎛ ⎜1 − e kT ⎜ ⎝

⎞ ⎟ ⎟ ⎠

VDS from 0 to 0.5V

Lecture 3, ECE 225

Kaustav Banerjee

Sub-Threshold ID vs VDS I D = I 0e

qVGS nkT

qV − DS ⎛ ⎜1 − e kT ⎜ ⎝

⎞ ⎟(1 + λ ⋅ VDS ) ⎟ ⎠

VGS from 0 to 0.3V

Lecture 3, ECE 225

Kaustav Banerjee

Leakage ‰

Effect of leakage current ƒ “Wasted” power: power consumed even when circuit is inactive ƒ Leakage power raises temperature of chip ƒ Can cause functionality problem in some circuits: memory, dynamic logic, etc.

‰

Reducing transistor leakage ƒ Long-channel devices ƒ Small drain voltage ƒ Large threshold voltage VT Lecture 3, ECE 225

Kaustav Banerjee

Leakage ‰

Leakage vs. performance tradeoff: ƒ For high-speed, need small VT and L ƒ For low leakage, need high VT and large L

‰

Process scaling ƒ VT reduces with each new process (historically) ƒ Leakage increases ~10X!

‰

One solution: dual-VT process ƒ Low-VT transistors: use in critical paths for high speed ƒ High-VT transistors: use to reduce power Lecture 3, ECE 225

Kaustav Banerjee

Latchup ‰ ‰

‰ ‰ ‰

CMOS process contains parasitic bipolar transistors Under certain conditions, these parasitic transistors can turn on, shorting power and ground rails and usually destroying the chip → latchup Avoiding latchup requires certain layout design rules, and careful control of process Latchup was a major problem in early CMOS processes Now, latchup is mainly issue for I/O circuits, with high current demands and possibly noisy voltages

Lecture 3, ECE 225

Kaustav Banerjee

Latchup substrate tap NMOS

‰ ‰ ‰ ‰

PMOS

n-well tap

Current flowing in well or substrate can forward-bias bipolar transistor Positive feedback between transistors: when one turns on, Vdd and Gnd are connected Solution: reduce Rnwell and Rpsubs: use many substrate taps in layout High-current circuits use guard rings Lecture 3, ECE 225

Kaustav Banerjee

Parasitic Resistances Polysilicon gate LD

G

Drain contact

W

VGS,eff D

S RS

RD Drain

Problem can be alleviated by silicided source/drain contacts © Digital Integrated Circuits2nd

Lecture 3, ECE 225

Kaustav Banerjee

Future Perspectives……

25 nm FINFET MOS transistor (Berkeley) © Digital Integrated Circuits2nd

Lecture 3, ECE 225

Kaustav Banerjee