#high-level Simulation Of Substrate Noise Generation In Complex Digital Systems
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High-Level Simulation of Substrate Noise Generation in Complex Digital Systems Mustafa Badaroglu, Marc van Heijningen, Stephane Donnay IMEC - DESICS - MIRA Kapeldreef 75, B-3001 Leuven, Belgium
Outline +
+
+
Substrate noise coupling problem Verification of SPICE models with measurements Macro-level modeling and simulation methodology - Overview - Library characterization - Equivalent circuit extraction
+
Verification of SWAN with measurements
+
Extensions to SWAN
+
Conclusions
IMEC - DESICS - MIRA
Workshop on Substrate Noise-Coupling in Mixed-Signal ICs, Imec, Belgium, Sep. 2001
3 aspects of substrate noise coupling digital
analog Vdd
Vdd
Vss
Vss
1
1
generation
2 1
2 IMEC - DESICS - MIRA
propagation through conducting substrate
impact
3
Workshop on Substrate Noise-Coupling in Mixed-Signal ICs, Imec, Belgium, Sep. 2001
Package types shape the noise. L
package L IC
Vss pin
1
wo =
ζ =
pin
Vdc
<1 ohm
Vsubstrate
trace
IMEC - DESICS - MIRA
Rc CC
CD
Vdc bondwire
Vdd
2 L (C D + C C Rc 2
1 Qs = Rc
)
CD + CC 2L 2L CD + CC
Workshop on Substrate Noise-Coupling in Mixed-Signal ICs, Imec, Belgium, Sep. 2001
Verification of SPICE models with measurements AuE 0.5um 3.3V CMOS
7x D
Noise Generator Clocked ring oscillator
Q
CLK 4 or 6 x
4 or 6 x
in Vss
4 or 6 x
Vdd
out p+
n+
n+
p+
P- epi
p+
n+
n-well
SPICE model for the inverter ANALOG NOISE SENSORS
P+ substrate
Substrate contact resistance
Bulk node to contact resistance
IMEC - DESICS - MIRA
Bulk node to substrate resistance
Well capacitances
Well to substrate resistance
DIGITAL NOISE GENERATORS
[Heijningen et. al, IEEE JSSC2000]
Workshop on Substrate Noise-Coupling in Mixed-Signal ICs, Imec, Belgium, Sep. 2001
Comparison of SPICE model in Test Chip1 Vsub [mV] 25
measurement SPICE
20 15 10 5 0 -5 -10 -15
0
5
10
15
20
25
30
time [ns]
IMEC - DESICS - MIRA
Workshop on Substrate Noise-Coupling in Mixed-Signal ICs, Imec, Belgium, Sep. 2001
Ringing is also visible in the spectrum. Vsub [dB] -60 40 dB -80
-100
-120
-140
-160
Ringing 0
50
100
150
200
250
300
350
400
450
500
Freq [MHz]
IMEC - DESICS - MIRA
Workshop on Substrate Noise-Coupling in Mixed-Signal ICs, Imec, Belgium, Sep. 2001
How can we simulate such a complex system for substrate noise in SPICE?
DIGITAL MULTIRATE UP/DOWN CONVERTER substrate noise sensors
power region 1 power region 2
ROBO4 Chip IMEC - DESICS - MIRA
Technology CMOS 0.5µm,3.3 V Master Clock 163.84 MHz Internal Clocks 40.94, 20.48 and 10.24 MHz IO Word 12 bits Internal Word 14 bits Gate Count 86k Core Area 24.22 mm2 Chip Area 38.40 mm2 Package 120 pin CPGA Substrate Type EPI (4 µm thick) EPI Resistivity 10 Ω.cm Bulk Resistivity 10 mΩ.cm
ANALOG NOISE SENSORS Workshop on Substrate Noise-Coupling in Mixed-Signal ICs, Imec, Belgium, Sep. 2001
Substrate Waveform ANalysis Flow
INPUT: VHDL netlist
VHDLSWITCH (for switching event detection)
SUBMACRO (macro model library)
gate-level VHDL simulation
Chip-level substrate model extraction
IMEC - DESICS - MIRA
switching event database
Substrate noise simulation
OUTPUT: substrate noise voltage
Workshop on Substrate Noise-Coupling in Mixed-Signal ICs, Imec, Belgium, Sep. 2001
Overview of macro cell characterization in Vss
Vdd
out p+
n+
n+
p+
P- epi
p+
Ivss
n+
Vss1
n-well
Ivdd Vdd1 Cc
Rw
Rs Substrate
Substrate
Cw Ibulk
P+ substrate Substrate contact resistance
Bulk node to contact resistance
Bulk node to substrate resistance
Well capacitances
Well to substrate resistance
0$&52&(//02'(/
63,&(02'(/
IMEC - DESICS - MIRA
Workshop on Substrate Noise-Coupling in Mixed-Signal ICs, Imec, Belgium, Sep. 2001
VHDLSWITCH library is used for recording the switching activities. VHDL models are extended to record the input switching. Switching activity sensor for A A
OR VHDL model
B Switching activity sensor for B
IMEC - DESICS - MIRA
Glitch Filter
Z
Switching recorder
Glitch Filter
Workshop on Substrate Noise-Coupling in Mixed-Signal ICs, Imec, Belgium, Sep. 2001
Equivalent chip-level substrate model extraction Rwire
Lwire
“Vssx”
Power Supply
Lwire
Rwire
}
Chip-Level Substrate Model
Supply Parasitics
Lwire
“Vddx”
Lwire
Vdc
Rwire
Rwire
Gate } Substrate Model
Ipow,t “Vss”
“Vdd” Ccir,t
} Resistive Mesh
Rs,t
Ibulk,t
Vsubstrate
Approximated as a single node in low-ohmic substrates. IMEC - DESICS - MIRA
Workshop on Substrate Noise-Coupling in Mixed-Signal ICs, Imec, Belgium, Sep. 2001
Cw,t Rw,t
Comparison of results for Test Chip2 Vsub [mV]
0 -20
20
circuit operation: 16 times upconversion from 3.125 MHz to 50 MHz - master clock Fclk = 50 MHz - time period = 5 - measurement bandwidth = 1 GHz
measurement
40
measurement simulation error simulation
20
Vsub RMS
13.3 mV
12.0 mV
9.8 %
Vsub PP
80.6 mV
96.0 mV
19 %
0 -20 -40
12.55
12.60
12.65
12.70
12.75
time [us] IMEC - DESICS - MIRA
Workshop on Substrate Noise-Coupling in Mixed-Signal ICs, Imec, Belgium, Sep. 2001
Comparison of noise spectrum between SWAN and measurements -40
Vsub [dBV] measurement
-60
-80
-100 -40
simulation
-60
-80
-100 0
25
50
75
100 freq [MHz]
125
150
175
200
Difference in total substrate noise power only 1 dB, largest difference at a single 50 MHz clock multiple is 5 dB . IMEC - DESICS - MIRA
Workshop on Substrate Noise-Coupling in Mixed-Signal ICs, Imec, Belgium, Sep. 2001
SWAN shows >80% of noise power is generated from switching of core cells Vsub [mV] 40
20
0
-20 core switching -40
20
20.1
output switching 20.2
20.3
20.4
20.5
time [us] IMEC - DESICS - MIRA
Workshop on Substrate Noise-Coupling in Mixed-Signal ICs, Imec, Belgium, Sep. 2001
Increase of substrate noise at clock multiples and due to ringing Vsub [dBV] data input clock
data output clock
-40
+40 dB at clock multiples +20 dB from ringing
-60
-80
-100
0
50
ringing IMEC - DESICS - MIRA
100
150
200
Freq [MHz]
Workshop on Substrate Noise-Coupling in Mixed-Signal ICs, Imec, Belgium, Sep. 2001
Overview of simulation times
Simulated time No. switching events Clock frequency Full SPICE-level simulation VHDL gate-level simulation Substrate noise simulation Speedup + +
Robo4 86 Kgates 1 V 150000 50 MHz --11:27 min 12:30 min ---
multiplier 994 gates 5 V 63500 42 MHz 37 hours 29 sec 55 sec 1586 x
Speedup of 3 orders of magnitude for small circuits Simulation time is at the same order of magnitude as a gate-level VHDL simulation for large circuits
IMEC - DESICS - MIRA
Workshop on Substrate Noise-Coupling in Mixed-Signal ICs, Imec, Belgium, Sep. 2001
Extensions to SWAN methodology
external power supplies package parasitics model power supply pad models
+
Multiple supply domains
+
IO cell macro modeling
+
Modeling of input transition time and the load
CORE cell models
IO pad models
substrate node IMEC - DESICS - MIRA
Workshop on Substrate Noise-Coupling in Mixed-Signal ICs, Imec, Belgium, Sep. 2001
Test circuit for the accuracy from extensions Supply-2
Supply-1
IO Pad vdd2- vss2, vdde4-vsse4
1.0Ω 1.5nH 0.15Ω 1.0nH Counter8 vdd1-vss1
7-SegDisp vdd2- vss2 4 4
Counter Enable
7-SegDisp vdd3-vss3
8
2.0nH
2.0nH
0.5Ω
0.5Ω Supply-3
IMEC - DESICS - MIRA
8
0.15Ω 1.0nH
IO Pad Enable
Supply-4
100 MHz clock
Workshop on Substrate Noise-Coupling in Mixed-Signal ICs, Imec, Belgium, Sep. 2001
Chip-level extraction in multiple supply domains Vdc3
Vdc2
Vdc1
Package and Supply Pads Model Vss1
Vdd1 Ivsse3
Ivss1
Ivdd1
Ivss2
Core part Isub1 within supply-1
IMEC - DESICS - MIRA
Ivdde3
Ivss4
Ivdd4
Ivdd2
Isub2
Core part within supply-2 Substrate
Isub3
IO part within supply-2,3
Workshop on Substrate Noise-Coupling in Mixed-Signal ICs, Imec, Belgium, Sep. 2001
Experimental results with multiple supply domains, input slope, load, and/or IOs RMS-Vsub Error Speedup SPICE (wo. IOs) 4.852mV 0% x1 (~1h) SWAN (no extension) 3.525mV 27.3% x357 SWAN (w. inp./load) 4.006mV 17.4% x198 SWAN (m. pow.) 3.858mV 20.5% x155 SWAN (m. pow + inp./load) 4.554mV 6.1% x120 (29s) ___________________________________________________________________ SPICE (w. IOs) SWAN (w. IOs + pow. + inp./load)
6.922mV 0% 7.361mV
x1 (~4h) 6.3%
--x373 (40s)
[Badaroglu et. al, DATE2001] IMEC - DESICS - MIRA
Workshop on Substrate Noise-Coupling in Mixed-Signal ICs, Imec, Belgium, Sep. 2001
Overview of simulation times with extensions counter8disp Gate complexity Clock Frequency Clock Cycles Model Ext. Time SPICE Sim. Time SWAN Speed-up
IMEC - DESICS - MIRA
728 50 MHz. 25 0.10 sec. 249 min. 40.05 sec. 373x
Mult8
Robo4
994 40 MHz. 200 0.13 sec. 152 min. 30.79 sec. 296x
89132 50 MHz. 50 6.02 sec. --33 min. ---
Workshop on Substrate Noise-Coupling in Mixed-Signal ICs, Imec, Belgium, Sep. 2001
Chips for studying the impact and the reduction of the noise
BANDIT project partners: - IMEC - Ericsson - K.U. Leuven
%$1',7 &+,3
CHIP3: AuE 0.35um CMOS, 3.3 V Low-noise IQ demodulator circuits with embedded comparators and noise sensors IMEC - DESICS - MIRA
Workshop on Substrate Noise-Coupling in Mixed-Signal ICs, Imec, Belgium, Sep. 2001
Conclusions + +
+
+
+
Substrate noise is harmful for analog circuits, Gate-level analysis of the substrate noise (SWAN) is necessary in large digital circuits, RMS value of the substrate noise predicted with high-level SWAN simulation differs less than 10% from measurements, High-level simulation is orders of magnitude faster than full SPICE simulation, Switching noise from the IO buffers contribute only 20-30% of the total noise.
IMEC - DESICS - MIRA
Workshop on Substrate Noise-Coupling in Mixed-Signal ICs, Imec, Belgium, Sep. 2001
Outline +
+
+
Substrate noise coupling problem Verification of SPICE models with measurements Macro-level modeling and simulation methodology - Overview - Library characterization - Equivalent circuit extraction
+
Verification of SWAN with measurements
+
Extensions to SWAN
+
Conclusions
IMEC - DESICS - MIRA
Workshop on Substrate Noise-Coupling in Mixed-Signal ICs, Imec, Belgium, Sep. 2001
3 aspects of substrate noise coupling digital
analog Vdd
Vdd
Vss
Vss
1
1
generation
2 1
2 IMEC - DESICS - MIRA
propagation through conducting substrate
impact
3
Workshop on Substrate Noise-Coupling in Mixed-Signal ICs, Imec, Belgium, Sep. 2001
Package types shape the noise. L
package L IC
Vss pin
1
wo =
ζ =
pin
Vdc
<1 ohm
Vsubstrate
trace
IMEC - DESICS - MIRA
Rc CC
CD
Vdc bondwire
Vdd
2 L (C D + C C Rc 2
1 Qs = Rc
)
CD + CC 2L 2L CD + CC
Workshop on Substrate Noise-Coupling in Mixed-Signal ICs, Imec, Belgium, Sep. 2001
Verification of SPICE models with measurements AuE 0.5um 3.3V CMOS
7x D
Noise Generator Clocked ring oscillator
Q
CLK 4 or 6 x
4 or 6 x
in Vss
4 or 6 x
Vdd
out p+
n+
n+
p+
P- epi
p+
n+
n-well
SPICE model for the inverter ANALOG NOISE SENSORS
P+ substrate
Substrate contact resistance
Bulk node to contact resistance
IMEC - DESICS - MIRA
Bulk node to substrate resistance
Well capacitances
Well to substrate resistance
DIGITAL NOISE GENERATORS
[Heijningen et. al, IEEE JSSC2000]
Workshop on Substrate Noise-Coupling in Mixed-Signal ICs, Imec, Belgium, Sep. 2001
Comparison of SPICE model in Test Chip1 Vsub [mV] 25
measurement SPICE
20 15 10 5 0 -5 -10 -15
0
5
10
15
20
25
30
time [ns]
IMEC - DESICS - MIRA
Workshop on Substrate Noise-Coupling in Mixed-Signal ICs, Imec, Belgium, Sep. 2001
Ringing is also visible in the spectrum. Vsub [dB] -60 40 dB -80
-100
-120
-140
-160
Ringing 0
50
100
150
200
250
300
350
400
450
500
Freq [MHz]
IMEC - DESICS - MIRA
Workshop on Substrate Noise-Coupling in Mixed-Signal ICs, Imec, Belgium, Sep. 2001
How can we simulate such a complex system for substrate noise in SPICE?
DIGITAL MULTIRATE UP/DOWN CONVERTER substrate noise sensors
power region 1 power region 2
ROBO4 Chip IMEC - DESICS - MIRA
Technology CMOS 0.5µm,3.3 V Master Clock 163.84 MHz Internal Clocks 40.94, 20.48 and 10.24 MHz IO Word 12 bits Internal Word 14 bits Gate Count 86k Core Area 24.22 mm2 Chip Area 38.40 mm2 Package 120 pin CPGA Substrate Type EPI (4 µm thick) EPI Resistivity 10 Ω.cm Bulk Resistivity 10 mΩ.cm
ANALOG NOISE SENSORS Workshop on Substrate Noise-Coupling in Mixed-Signal ICs, Imec, Belgium, Sep. 2001
Substrate Waveform ANalysis Flow
INPUT: VHDL netlist
VHDLSWITCH (for switching event detection)
SUBMACRO (macro model library)
gate-level VHDL simulation
Chip-level substrate model extraction
IMEC - DESICS - MIRA
switching event database
Substrate noise simulation
OUTPUT: substrate noise voltage
Workshop on Substrate Noise-Coupling in Mixed-Signal ICs, Imec, Belgium, Sep. 2001
Overview of macro cell characterization in Vss
Vdd
out p+
n+
n+
p+
P- epi
p+
Ivss
n+
Vss1
n-well
Ivdd Vdd1 Cc
Rw
Rs Substrate
Substrate
Cw Ibulk
P+ substrate Substrate contact resistance
Bulk node to contact resistance
Bulk node to substrate resistance
Well capacitances
Well to substrate resistance
0$&52&(//02'(/
63,&(02'(/
IMEC - DESICS - MIRA
Workshop on Substrate Noise-Coupling in Mixed-Signal ICs, Imec, Belgium, Sep. 2001
VHDLSWITCH library is used for recording the switching activities. VHDL models are extended to record the input switching. Switching activity sensor for A A
OR VHDL model
B Switching activity sensor for B
IMEC - DESICS - MIRA
Glitch Filter
Z
Switching recorder
Glitch Filter
Workshop on Substrate Noise-Coupling in Mixed-Signal ICs, Imec, Belgium, Sep. 2001
Equivalent chip-level substrate model extraction Rwire
Lwire
“Vssx”
Power Supply
Lwire
Rwire
}
Chip-Level Substrate Model
Supply Parasitics
Lwire
“Vddx”
Lwire
Vdc
Rwire
Rwire
Gate } Substrate Model
Ipow,t “Vss”
“Vdd” Ccir,t
} Resistive Mesh
Rs,t
Ibulk,t
Vsubstrate
Approximated as a single node in low-ohmic substrates. IMEC - DESICS - MIRA
Workshop on Substrate Noise-Coupling in Mixed-Signal ICs, Imec, Belgium, Sep. 2001
Cw,t Rw,t
Comparison of results for Test Chip2 Vsub [mV]
0 -20
20
circuit operation: 16 times upconversion from 3.125 MHz to 50 MHz - master clock Fclk = 50 MHz - time period = 5 - measurement bandwidth = 1 GHz
measurement
40
measurement simulation error simulation
20
Vsub RMS
13.3 mV
12.0 mV
9.8 %
Vsub PP
80.6 mV
96.0 mV
19 %
0 -20 -40
12.55
12.60
12.65
12.70
12.75
time [us] IMEC - DESICS - MIRA
Workshop on Substrate Noise-Coupling in Mixed-Signal ICs, Imec, Belgium, Sep. 2001
Comparison of noise spectrum between SWAN and measurements -40
Vsub [dBV] measurement
-60
-80
-100 -40
simulation
-60
-80
-100 0
25
50
75
100 freq [MHz]
125
150
175
200
Difference in total substrate noise power only 1 dB, largest difference at a single 50 MHz clock multiple is 5 dB . IMEC - DESICS - MIRA
Workshop on Substrate Noise-Coupling in Mixed-Signal ICs, Imec, Belgium, Sep. 2001
SWAN shows >80% of noise power is generated from switching of core cells Vsub [mV] 40
20
0
-20 core switching -40
20
20.1
output switching 20.2
20.3
20.4
20.5
time [us] IMEC - DESICS - MIRA
Workshop on Substrate Noise-Coupling in Mixed-Signal ICs, Imec, Belgium, Sep. 2001
Increase of substrate noise at clock multiples and due to ringing Vsub [dBV] data input clock
data output clock
-40
+40 dB at clock multiples +20 dB from ringing
-60
-80
-100
0
50
ringing IMEC - DESICS - MIRA
100
150
200
Freq [MHz]
Workshop on Substrate Noise-Coupling in Mixed-Signal ICs, Imec, Belgium, Sep. 2001
Overview of simulation times
Simulated time No. switching events Clock frequency Full SPICE-level simulation VHDL gate-level simulation Substrate noise simulation Speedup + +
Robo4 86 Kgates 1 V 150000 50 MHz --11:27 min 12:30 min ---
multiplier 994 gates 5 V 63500 42 MHz 37 hours 29 sec 55 sec 1586 x
Speedup of 3 orders of magnitude for small circuits Simulation time is at the same order of magnitude as a gate-level VHDL simulation for large circuits
IMEC - DESICS - MIRA
Workshop on Substrate Noise-Coupling in Mixed-Signal ICs, Imec, Belgium, Sep. 2001
Extensions to SWAN methodology
external power supplies package parasitics model power supply pad models
+
Multiple supply domains
+
IO cell macro modeling
+
Modeling of input transition time and the load
CORE cell models
IO pad models
substrate node IMEC - DESICS - MIRA
Workshop on Substrate Noise-Coupling in Mixed-Signal ICs, Imec, Belgium, Sep. 2001
Test circuit for the accuracy from extensions Supply-2
Supply-1
IO Pad vdd2- vss2, vdde4-vsse4
1.0Ω 1.5nH 0.15Ω 1.0nH Counter8 vdd1-vss1
7-SegDisp vdd2- vss2 4 4
Counter Enable
7-SegDisp vdd3-vss3
8
2.0nH
2.0nH
0.5Ω
0.5Ω Supply-3
IMEC - DESICS - MIRA
8
0.15Ω 1.0nH
IO Pad Enable
Supply-4
100 MHz clock
Workshop on Substrate Noise-Coupling in Mixed-Signal ICs, Imec, Belgium, Sep. 2001
Chip-level extraction in multiple supply domains Vdc3
Vdc2
Vdc1
Package and Supply Pads Model Vss1
Vdd1 Ivsse3
Ivss1
Ivdd1
Ivss2
Core part Isub1 within supply-1
IMEC - DESICS - MIRA
Ivdde3
Ivss4
Ivdd4
Ivdd2
Isub2
Core part within supply-2 Substrate
Isub3
IO part within supply-2,3
Workshop on Substrate Noise-Coupling in Mixed-Signal ICs, Imec, Belgium, Sep. 2001
Experimental results with multiple supply domains, input slope, load, and/or IOs RMS-Vsub Error Speedup SPICE (wo. IOs) 4.852mV 0% x1 (~1h) SWAN (no extension) 3.525mV 27.3% x357 SWAN (w. inp./load) 4.006mV 17.4% x198 SWAN (m. pow.) 3.858mV 20.5% x155 SWAN (m. pow + inp./load) 4.554mV 6.1% x120 (29s) ___________________________________________________________________ SPICE (w. IOs) SWAN (w. IOs + pow. + inp./load)
6.922mV 0% 7.361mV
x1 (~4h) 6.3%
--x373 (40s)
[Badaroglu et. al, DATE2001] IMEC - DESICS - MIRA
Workshop on Substrate Noise-Coupling in Mixed-Signal ICs, Imec, Belgium, Sep. 2001
Overview of simulation times with extensions counter8disp Gate complexity Clock Frequency Clock Cycles Model Ext. Time SPICE Sim. Time SWAN Speed-up
IMEC - DESICS - MIRA
728 50 MHz. 25 0.10 sec. 249 min. 40.05 sec. 373x
Mult8
Robo4
994 40 MHz. 200 0.13 sec. 152 min. 30.79 sec. 296x
89132 50 MHz. 50 6.02 sec. --33 min. ---
Workshop on Substrate Noise-Coupling in Mixed-Signal ICs, Imec, Belgium, Sep. 2001
Chips for studying the impact and the reduction of the noise
BANDIT project partners: - IMEC - Ericsson - K.U. Leuven
%$1',7 &+,3
CHIP3: AuE 0.35um CMOS, 3.3 V Low-noise IQ demodulator circuits with embedded comparators and noise sensors IMEC - DESICS - MIRA
Workshop on Substrate Noise-Coupling in Mixed-Signal ICs, Imec, Belgium, Sep. 2001
Conclusions + +
+
+
+
Substrate noise is harmful for analog circuits, Gate-level analysis of the substrate noise (SWAN) is necessary in large digital circuits, RMS value of the substrate noise predicted with high-level SWAN simulation differs less than 10% from measurements, High-level simulation is orders of magnitude faster than full SPICE simulation, Switching noise from the IO buffers contribute only 20-30% of the total noise.
IMEC - DESICS - MIRA
Workshop on Substrate Noise-Coupling in Mixed-Signal ICs, Imec, Belgium, Sep. 2001
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