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Analog Integrated Circuits and Signal Processing, 25, 85±91, 2000 # 2000 Kluwer Academic Publishers. Manufactured in The Netherlands.

High Volume RF/Microwave SOI-CMOS Integrated Circuits A. J. AUBERTON-HERVE, T. BARGE AND C. MALEVILLE Soitec SA, Bernin, France

A. WITTKOWER Soitec USA, Peabody, MA, USA

Received June 28, 1999; Revised February 24, 2000; Accepted February 25, 2000

Abstract. Building RF/microwave SOI-CMOS integrated circuits has significant speed and power advantages over circuits built on bulk materials. High quality SOI material exists today which will meet today's device requirements; on-going development efforts will improve the material available for subsequent device generations. Key Words: SOI material, unibond, low power, SOI volume production, CMOS-SOI, high resistivity, SOI roadmap

1.

Circuit Issues

Advances in technologies for conserving energy will deliver enormous system bene®ts. Soon, most portable microsystems will operate at 1 V. With a single battery or solar cell energy supply, low voltage, low power circuits will make possible a truly personal portable system, enhancing communication and information servicing. SOI can operate in the GHz range with only 1 V of supply voltage and a few milliwatts of power consumption, suitable for pagers, cellular phones and personal digital assistants (see Fig. 1). In addition to the general low power market, this capability makes SOI best suited to portable communications systems. Here, the competition with BiCMOS silicon technology favors SOI for two reasons: power consumption and process complexity. For example, phase lock loop ICs (PLLs) using 0.24 mm CMOS-SOI are able to operate at GHz frequencies with a power consumption of 1 mW at only 1.2 V. The power consumption is one decade lower than BiCMOS circuits at the same frequency. As the power consumption is P*CV 2 ? f ‡ V ? Ileak where C ˆ total capacitance, V ˆ supply voltage, f ˆ frequency and Ileak ˆ standby current, the supply

voltage must be reduced to obtain low power ICs. This power supply reduction has to follow the systems industry's evolution in battery voltage and capacity. The target (i.e. SIA-SEMATECH roadmap) is to reach 0.9 V using a single battery by year 2000. However, at such a low voltage, performance is also reduced because of lower transistor drivability. SOI provides many advantages for low voltage IC operation: * It reduces junction capacitance, thereby inducing a reduction of the total capacitance by 15±30%, depending on the circuit design. * It increases the switching behavior of MOS devices, providing a sharper sub-threshold slope. This allows a reduction in threshold voltage, thus increasing the current driveability at low voltage and reducing leakage current. * It reduces junction area by at least two decades, which also decreases leakage current. * It lowers threshold voltage temperature sensitivity. One proposed alternative to reduce power consumption is to change circuit architecture. This could be done, for example, by switching off some parts of a circuit based on real-time system needs and by reducing internal clock frequency in some noncritical circuit parts. However, the ef®-

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Fig. 1. Sub-halfmicron CMOS prescaler and phase lock loop (PLL) ICs fabricated on SOI wafers operate at low voltage and low power consumption, making them suitable for portable communications applications, such as pagers, cellular phones and personal digital assistants.

ciency of such solutions depends on design. The more appealing alternative is to create a generic improvement at the silicon or SOI technology level and then use a circuit design or software solution as an add-on. 1.1.

Microwave Applications

Battery-operated cellular radios require digital circuits that function in the gigahertz range at very low power. CMOS SOI technology with a 0.4 mm design rule was used for divide by 128/129, dual modulus prescalers operating at 2 GHz, 2 V, and 7.2 mW [1]. In other work, microwave SOI technology on highly resistive substrates has demonstrated cutoff frequencies of 32 and 20 GHz for n- and p-channel MOSFETs, respectively [2]. With such performance, GaAs hybrids could be replaced by SOI monolithic microwave ICs, thereby providing an opportunity to integrate high-speed RF and digital circuits on the same substrate with lower cost and higher yield. 1.2.

that of 0.3 mm bulk Si devices. This suggests, of course, that the performance of advanced 0.18 mm devices may be achieved by using, in great part, the more rapidly maturingÐand hence more costeffectiveÐ0.18 mm microfabrication technology. The small substrate bias effect in SOI-MOSFETs allows low voltage operation in the 1.5 V regime. Stable operation of a 256-kbit SRAM/SOI was demonstrated at 1.2 V [4], while a bulk Si cell fabricated with the same mask set was not active below 2 V. The SRAM/SOI employed a partially depleted, n-channel MOSFET. DRAMs set the pace for packing density more than any other device. Three-dimensional structures, such as trench and stacked capacitors, have been introduced to realize suf®cient storage capacitance, Cs . An advanced vertical structure in bulk Si, the surrounding gate transistor DRAM, is shown in Fig. 2 [5]. However, the SOI substrate is more tolerant of small Cs values due to its soft, error-free characteristics and small bit line capacitance, CB . The simply stacked planar transistor cell using high-dielectric material [6] (Fig. 3) will be available for 1 Gbit DRAMs instead of more complicated cell structures. Sony also showed an advanced cell concept employing bonded and etched SOI [7,8]. Since the capacitor is fabricated on the other side of the plane consisting of the transistor and wiring, the structure

ULSI CMOS Applications

A major application for SOI lies in commercial CMOS-ULSI. SOI's reduced power consumption and its 1.1 to 36speed advantage vis-aÁ-vis bulk Si devices have been demonstrated with CMOS-SOI gate arrays [3]. The improved speed is a direct consequence of the smaller junction and wiring capacitance of SOI structures. This essential feature of SOI prevails at any scaling factor. The SOI devices with 0.18 mm design rule offer speed performance comparable to

Fig. 2. A surrounding gate transistor cell for 64-/256 Mbit DRAM.

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Fig. 3. Simply stacked planar capacitor cell on SOI using a high-E material for 1 Gbit DRAM.

simpli®es the surface topography for the bit line and relaxes the lithographic alignment error tolerance. Implementation of a 0.15±0.10 mm SOI technology will require the use of fully depleted, accumulation mode transistors. Since these devices will operatewith channel dopant concentrations in the 1016 rangeÐ 106less than required for their bulk counterpartsÐ scaling differs completely from that for enhancement mode transistors. The key factor in optimizing such devices is silicon ®lm thickness. Transistors processed with ®lm thicknesses as low as 50 nm demonstrate hot electron behavior, short channel effects, and breakdown voltages better than on bulk silicon [9,10].

Buried oxide (BOX) thickness must also be reduced for deep-submicron optimization. Devices with 0.1 mm channel lengths in 50 nm SIMOX Si ®lms on top of 80 nm BOX layers exhibited a 10 year lifetime at Vd ˆ 1:6 V [11,12]. Such ultrathin devices suppress short channel effects and are very attractive due to their high-speed performance. 2.

Material Issues

The material issues are driven, clearly, by device requirements. As the devices become smaller, faster,

Table 1. SOI material roadmap.

Design rule Device type Wafer size SOI thickness SOI uniformity Buried oxide thickness Buried oxide uniformity Dislocations density Pipes density Roughness Metal contamination

1995

1999

0.35mm Partially depleted 150±200 mm 100 mm 10 nm 400 nm 20 nm 510,000=cm2 50.2=cm2  3A  (max±min 20 A) 11 2 510 =cm

0.18mm Partially depleted 200 mm 50 nm 5 nm 200±800 nm 4 nm 5100=cm2 5 0.1=cm2  2A  (max±min 10 A) 10 2 5 5.10 =cm

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closer to the surface, lower voltage, etc., the material requirements become more stringent (Table 1). Preparation of the SOI material takes two distinct forms: the manufacture of the material and routine characterization with strict statistical process control (SPC). Recently a new manufacturing technology called Smart Cut has been introduced which allows large scale manufacturing of thin ®lm SOI (Unibond wafers) to be achieved economically for the ®rst time.

2.1.

Material Manufacturing

Smart Cut technology is based both on ion implantation and wafer bonding technologies. While the process starts with two wafers, the second wafer is not sacri®ced, but reused to create a subsequent SOI wafer. The ion implantation step assures uniformity of the SOI ®lm. The bonding step assures use of thermally grown buried oxides and the perfect crystalline quality of the top silicon ®lm. * Starting with two wafers, one is oxidized to form what will become the buried oxide layer of the SOI structure. Thermal oxide as the buried oxide ensures very high insulation integrity without any leakage paths. * Ion implantation through the oxide forms the Smart Cut layer. (The dose is proprietary, but in the range of standard implantation processes used in semiconductor manufacturing.) * Both wafers go through a modi®ed RCA cleaning step; this is an important step to prevent voids at the subsequent bonded interface. * The two wafers are bonded together using hydrogen bonds (hydrophilic bonding). * The top wafer is cut away using the implanted region as a reference. * The SOI wafer is then annealed at 1100 C in argon to increase the quality of the bonding interface. After this step, neither chemical revelation nor mechanical tests can reveal any weak point at the bonding interface which exhibits the same properties as a thermally formed silicon/oxide interface. * Finally, a touch chemical mechanical polish (CMP) step ®nishes the top surface to a roughness   5 1.5 A (rms); this step removes a few 100 A from the top surface.

The remaining wafer is reclaimed with a touch polish process and can be used both as support wafer or the seed wafer in the next process ¯ow. This wafer is nearly identical in thickness to the original starting wafer and stays in silicon speci®cations (725 + 25 mm for 8 in wafers). The two limitations of conventional bonding technique are solved by this new technology: First, the uniformity of the SOI ®lm is ®xed by the uniformities of the implantation and touch polish steps. These two processes induce a total on-wafer  and wafer-to-wafer dispersion better than 100 A, independent of the silicon ®lm thickness and wafer size. Second, since the process is done at low temperature, the thin SOI ®lm is already formed before the annealing process. (In conventional bonding, during annealing, the bonded interface is strained by 725 mm of silicon, but with the Smart Cut process the annealed interface is only capped by a  few 1000 A of silicon and oxide, which easily conforms to the base structure without strain.) Thus, micro voids can be easily detected on as-split wafers. XTEM analysis has been used after the cutting steps and again on the ®nal SOI structure, but no crystalline defects were observed. In addition, tests  have shown that the intrinsic breakdown ®eld of 40 A gate oxide is 16±17 MV, which is comparable to the best silicon material. The CMP step improves the  breakdown ®eld on SOI products with a 40 A gate oxides and is the key of gate oxide reliability issues on silicon wafers. Gate oxide integrity tests under constant current stress show no difference between gate oxide grown on Unibond SOI substrates and epi wafers, even for a large cell size of 1 cm2 . *

2.2.

Volume Production

Key equipment used to perform the process are a standard high current implanter and a chemical mechanical polisher. Fig. 4 shows a comparison in terms of process capacity between Smart Cut and Simox process. High volume production is allowed by the drastic reduction of implantation time, with more than 15 wafers an hour for a beam current of 25 mA; this translates roughly into a manufacturing capacity of 100,000 8 inch (200 mm) wafers per year (taking into account uptimes, . . .). Wafer bonding appears as a new and speci®c technological step in the front end microelectronic

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Fig. 4. Comparison of implanter capacity for Smart Cut and SIMOX.

®eld. Fully automatic wet cleaning and bonding tools are used to guarantee defect free contacting of the wafers. By reducing particle contamination and automatic bonding, this step becomes a very reliable step, with yield comparable to thermal treatment or implantation steps. In terms of production capacity, automatic wafer bonding demonstrates high throughput and no limitation for volume production. The end of the Unibond process involves polishing and ®nal sorting which are also performed with standard equipment. SOI polishing differs from current silicon polishing by the addition of tough uniformity requirements while the same defectivity control is needed. Optimization of pad, slurry and machine set-up is needed to obtain good quality and reproducibility. Final control is made using laser scattering tools with speci®cations comparable to that of bulk silicon. At each control step, characterization equipment is used to measure the appropriate texture. A typical SPC chart, showing upper and lower control limits for surface silicon and buried oxide thickness, is shown in Fig. 5. Only if all processes are within control limits, is the material acceptable.

Fig. 5. Surface silicon and Buried Oxide thickness SPC.

facturability of high quality SOI on highly resistive base wafer allows one to extend the bene®ts of SOI to microwave applications. Concerning the cost comparison, SOI becomes more competitive as we go to larger diameters. SOI material quality signi®cantly improved these last year with aggressive and realistic roadmaps satisfying SIA requirements. There is no longer a barrier for high volume RF/ microwave SOI-CMOS integrated circuits production.

References 3.

Conclusion

While entering the 21st century, it appears clearly that SOI material is the appropriate material for advance CMOS applications, combining performance and lowpower/low voltage operation mode. Manu-

1. Y. Kado, M. Suzuki, K. Koike, Y. Omura, and K. Izumi, ``A 1 GHz 0.9-mA/1 V CMOS/SIMOX * 128/129 dual modulus prescaler using a newly developed counter,'' Digest, 1992 Symp. on VLSI Circuits, p. 44. 2. A. K. Agawal, M. C. Driver, M. H. Hanes, H. M. Hobgood, P. G. McMullin, H. C. Nathanson, T. W. O'Keefe, T. J. Smith, J. R. Szedon, and R. N. Thomas, ``MICROXÐAn advanced

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A. Auberton-Herve et al. silicon technology for microwave circuits up to X-band.'' IEDM Tech. Digest, p. 687, 1991. Y. Yamaguchi, A. Ishibashi, M. Shimizu, T. Nishimura, K. Tsukamoto, K. Horie, and Y. Akasaka, ``A high-speed 0.6 mm 16K CMOS gate array on a thin SIMOX ®lm.'' IEEE Trans. Elect. Dev. 40, p. 179, 1993. Y. Inoue, Y. Yamaguchi, T. Yamaguchi, J. Takahashi, T. Iwamatsu, T. Wada, Y. Nishimura, T. Nishimura, and N. Tsubouchi, ``Selection of operation mode on SOI/MOSFETs for high-resistivity load static memory cell,'' in IEEE Intl. SOI Conf., 1993. K. Sunouchi, H. Takato, N. Okabe, T. Yamada, T. Ozaki, S. Inoue, K. Hashimoto, K. Hieda, A. Nitayama, F. Horiguchi, and F. Masuoka, ``A surrounding gate transistor (SGT) cell for 64/ 256 Mbit DRAMs.'' IEDM Tech. Digest, p. 23, 1989. H. Komiya, ``Future technological and economic prospects for VLSI.'' ISSCC Dig. of Tech. Papers, p. 16, 1993. T. Nishihara, ``A buried capacitor DRAM cell with bonded SOI for 256-Mbit and 1 Gbit DRAMs.'' IEDM Tech. Digest, p. 803, 1992. T. Nishihara, N. Ikeda, H. Aozasa, and Y. Miyazawa, ``A buried capacitor cell with bonded SOI for 256-Mbit and 1 Gbit DRAMs.'' Solid State Technology, 37(6), p. 89, 1994. O. Faynot, A. J. Auberton-Herve, and S. Cristoloveanu, ``Experimental analysis of the thin-®lm thickness in¯uence on the performance of accumulation mode SIMOX NMOSFETs,'' in IEEE Intl. SOI Conf., p. 114, 1992. O. Faynot, S. Cristoloveanu, A. J. Auberton-Herve, and G. Reimbold, ``Hot carrier deradation in ultrathin fully depleted accumulation mode SIMOX NMOSFETs,'' in Proc. 8th Biennial Conf on Insulating Films on Semiconductors, INFOS 93, Elsevier, 1993. Y. Omura and K. Izumi, ``Hot carrier immunity of a 0.1 mm gate ultrathin ®lm MOSFET/SIMOX,'' in Ext. Abst. Intl. Conf. SSDM, p. 496, 1992. W. F. Krause, B. R. Doyle, J. E. Clark, K. L. Jones, and D. M. Thornberry, ``A 20-ns multiple architecture 256K SIMOX SRAM designed for harsh radiation environments,'' in Proc. 1992 IEEE Intl. SOI Conf., p. 168.

A. J. Auberton-Herve is Corporate President of SOITEC (Silicon-On-Insulator Technologies) founded in 1992. He has over 17 years of experience in SOI technologies and the semiconductor industry.

He holds a Ph.D. in Semiconductor Physics from Ecole Centrale de Lyon and a MS in Material Science and Physics from Ecole Centrale de Lyon. From 1983 to 1992, he was in charge of several European projects including 3D integration and SOI high speed VLSI. He also managed a joint development program between LETI and THOMSON-CSF on SOI-CMOS technologies. He is a member of the IEEE and the Electrochemical Society and received a 1999 European SEMI Award.

T. Barge is a process engineering manager. He holds a Ph.D. in Materials Science from Universite de Marseille and has been working for CNRS. During the three years he spent in ES2, Le Rousset FR (now an ATMEL company), he was in charge of implementation of silicide processes for 0.5 mm technology. He joined SOITEC in 1993 to participate in collaboration with CEA/LETI to the ®rst developments of the Smart-Cut process and its applications to the manufacturing of SOI wafers.

C. Maleville is a process engineering researcher. He holds a Ph.D. in Microelectronics from the Institut Polytechnique de Grenoble (INPG). Since 1993, he has been involved in collaboration with CEA/LETI to the ®rst developments of the Smart-Cut process and its applications to the manufacturing of SOI wafers.

RF/Microwave SOI-CMOS Integrated Circuits

A. Wittkower an atomic physicist with a Ph.D. from University College, London, has extensive

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experience in the semiconductor industry. His work in the ®eld of ion implantation was recognized by the industry in 1996 when he received a prestigious award from Semiconductor Equipment and Material International (SEMI) for his contributions to wafer fabrication equipment. His credentials include the founding and management of several ion implant-related companies, including Extrion Corporation (now Varian) and Nova Associates (now Eaton). Since 1992, he has been President of SOITEC USA Inc.