Fpgas In Digital Communications

FPGAs in Digital Communications Dr Chris Dick DSP Chief Architect Director, Signal Processing Engineering

Digital Comm Examples • Channelized receiver to support – QAM – OFDM

• Examine – Channelizer implementation – QAM demodulator architecture – OFDM modulator/demodulator

Channelization 2

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Passband Polyphase Filters channels

S( f )

f

fc

fc

fc

fc

fc

• In a FDM digital communication system a common requirement is, for each channel: – translate the channel to baseband – shape the channel spectrum – reduce the sample rate to match the channel bandwidth

• This is the function of a channelizer • When the channel spacing is equal a computationally efficient structure for performing the above functions is the carrier centered polyphase transform Channelization 3

Baseband Polyphase Filter h0 ( n) h1 (n )

x (n)

h2 ( n)

y ( Mn)

hM −1 ( n)

h0 (n) =

h0

hM

!

h1 (n) = "

h1 "

hM +1 "

! hN − M +1 ! "

hM −1 (n) = hM −1 h2 M −1 !

hN − M

hN −1

Channelization 4

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Passband Polyphase Filters Express the filter coefficient set in terms of a course and vernier index r1 and r2 respectively h(n) = h(r1 + Mr2 )

r1 =0,… , M − 1, r2 =0,… ,

N −1 M

Invoke the modulation theorem to convert a prototype baseband filter to its equivalent carrier centered, or spectrally shifted version if

h(n) ⇔ H (θ )

then

h(n)e jθ 0n ⇔ H (θ − θ 0 )

Channelization 5

Passband Polyphase Filters The coefficients of the carrier centered filter are g ( n) = h( n)e jθ0 n | G (θ ) |

| H (θ ) |

−π

θ0

π

θ

Now perform a polyphase partition on the modulated coefficients g r1 (r2 ) = h(r1 + Mr2 )e jθ 0 ( r1 + Mr2 ) = h(r1 + Mr2 )e jθ0 r1 e jθ 0 Mr2 Select θ 0 so that a single period of the series e jθ0 n is harmonically related to M Channelization 6

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Passband Polyphase Filters θ0 = k

Carrier centered polyphase filter the one structure • Translates the channel to baseband • Shapes the signal • Reduces the sample rate

2π M

g r1 ( r2 ) = h( r1 + Mr2 )e jθ 0 r1 e = h( r1 + Mr2 )e

jk

jk

2π Mr2 M

2π r1 M

e j 0θ k

h0 ( n) e j1θ k

x ( n)

h1 (n) y ( Mn, k ) e

j ( M − 2)θ k

hM −2 (n) e j ( M −1)θ k

hM −1 ( n) Channelization 7

Passband Polyphase Filters h0 (n) h1 (n)

y ( Mn, 0)

hM −2 (n) x ( n)

hM −1 (n) e j 0θ k

h0 (n) e j1θ k

Recovering 2 channels from FDM spectra The two sets of filters employ identical coefficients Note: the two sets of filters contain the same data

h1 (n)

y (Mn, k ) e j ( M − 2)θ k

hM − 2 ( n) e j ( M −1)θ k

hM −1 ( n)

Channelization 8

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Polyphase Transform Recall that the IDFT of an M -point sequence Y (k ) is M −1

y (n) = ∑ Y ( k )e j 2π nk / M

n = 0,1,… , M − 1

k =0

If the M phase rotators are sequenced over all of the M values of k we recognize that this is the same as computing an IDFT

x ( n)

h0 ( n)

y ( Mn, 0)

h1 (n)

y ( Mn,1)

M-Point IDFT hM −2 (n)

y ( Mn, M − 2)

hM −1 ( n)

y ( Mn, M − 1)

Channelization 9

Channelizer Filter Bank 0 dB

-2 0 -4 0 -6 0 -8 0 -0 .5

0 F re q ue nc y

0 .5

dB

0 -2 0 -4 0 -6 0 -0 .0 6

-0 .0 4

-0 .0 2 0 0 .0 2 F re q ue nc y

0 .0 4

0 .0 6

Channelization 10

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Phase Response of Paths in Ten Stage Polyphase Filter S pe ctra l P ha s e Res pons e of Te n P olypha s e Filte rs 0

-1

-2

Norma liz ed P ha s e (φ /2 π)

-3

-4

-5

-6

-7

-8

-9 0

0.05

0.1

0.15

0.2 0.25 0.3 Normale d Fre que nc y (f/fs )

0.35

0.4

0.45

0.5

Channelization 11

Group Delay of Paths in Ten-Stage Polyphase Filter S pe c tra l Group De la y Res pons e of Ten P olyphas e Filte rs -7

-7.2

-7.4

Norma liz e d Delay (∆ T/Ts )

-7.6

-7.8

-8

-8.2

-8.4

-8.6

-8.8

-9 0

0.05

0.1

0.15

0.2 0.25 0.3 Norma le d Fre que nc y (f/fs )

0.35

0.4

0.45

0.5

Channelization 12

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40 Channel Polyphase Receiver Time Series Waterfall from 40-Channel Polyphase Receiver

0. 8

m a g n itud e

0. 6 0. 4 0. 2 0 40 35 30 25 20 15 10 c e n te r fre qu e n c y

5 0

0

10

20

40

30

50

60

70

80

90

1 00

tim e

Channelization 13

Channelized Receiver Example • Design a channelized receiver channels

X(f )

f

fc

fc

sample rate fs = 100 MHz, 12b samples 16 channels f c = 6.25 MHz M-ary QAM modulation concatenated decoder

fc

fc

fc

Filter requirements 60 dB stopband ripple 0.2 dB passband ripple

Channelization 14

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Polyphase Channelizer ADC

x ( n)

h0 ( n)

Receiver 0

h1 (n)

Receiver 1

M-Point IDFT

VCO

Receiver n

Matched Filter

hM −2 (n)

Receiver M-2

hM −1 ( n)

Receiver M-1

Equalizer

FEC Dec

Det

Privacy Dec

Source Dec

Carrier Recovery Timing Recovery

Viterbi Dec

Deint.

RS Dec

Channelization 15

Channelizer Filter Design • Design the prototype filter fs = 100 MHz

|H(f)| PdB = 0.2 dB AdB = 60 dB f

f s = 0.0375 f p = 0.0250 ∆f = 0.0375 − 0.0250 = 0.0125 Filter length approximation due to Prof. fred harris San Diego State University

f s AdB ⋅ ∆f 22 1 60 = ⋅ = 219 0.0125 22 N≈

Channelization 16

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Channelizer Implementation

Channelizer

Input Stimulus

Capture data to Matlab workspace for post analysis/display

Channelization 17

System Generator Implementation

quantize

1:16 decimator Physical level module generator is used to produce a highly efficient FPGA implementation of each block

Re-assemble filter outputs onto TDM bus for presentation to FFT

Polyphase Filter partition

Channelization 18

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System Generator Implementation

Channelization 19

System Generator Implementation

Channelization 20

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Filter Module

Channelization 21

System Generator Implementation -The Hardware Over-Sampling Rate (folding factor) field of the FIR filter block allows the designer to tradeoff throughput with FPGA area -The filter throughput is fclk/R where R is the Hardware Over-Samlping Rate and fclk is the filter clock rate … which is not necessarily the same as the filter sample rate -When R=1 a new filter output is generated on each clock cycle -For R=2 a new output is generated every second clock cycle -With this control the designer can realize a filter that best matches the requirements of the system

Channelization 22

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System Generator Implementation • In this design the input sample rate is 100 MHz (12b samples) • The sample rate presented to each filter in the filter bank is 100e6/16 = 6.25 MHz • The most efficient implementation for the filters is to employ a folding factor equal to the input sample precision • The filters will be clocked at a frequency of 12 x 6.25e6 = 75 MHz • The digital clock manager (DCM) can be used to generate the various clock frequencies Channelization 23

System Generator Implementation

An FFT Core highly optimized for the FPGA is used in the design

Channelization 24

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Implementation Statistics • Distributed arithmetic implementation employed in this example • Virtex-II Pro 2vp50-7 – Filter Bank: 6500 slices – fclk (max) = 200 MHz 2$

COMPLEX

×

×

16 $

14 $

SUB FILTER LENGTH

RE-SAMPLING RATIO

× 200 e6 = 90 GMACs $ CLOCK

• 448 mpys @ 200 MHz would be required to meet this performance using a MAC FIR approach • Use right algorithm for the problem • Explore the FPGA/algorithmic design space Channelization 25

Channelized Receiver Example (2) • Design a channelized receiver channels

X(f )

f

fc

– – – –

fc

fc

fc

fc

sample rate fs = 1 GHz, 12b samples 16 channels M-ary QAM modulation concatenated decoder

Channelization 26

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Wide-Band Channelized Receiver • In this case the challenge is to deliver the samples from the 1 Giga-sample/s ADC to the DSP engine • Utilize the double data rate (DDR) capability of the Virtex-2 input/output blocks (IOBs) • Use the DCM to generate the required clocks

Channelization 27

High-Speed 1GHz ADC

Channelization 28

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ADC Timing

Channelization 29

1GHz ADC-FPGA Interface Virtex-II FPGA DDR IOB

P0-P7

ADC

x (t )

DQ

DQ

x( n − 1)

DQ

DQ

x( n + 3)

DQ

DQ

x( n + 1)

DQ

DQ

x (n + 5)

DQ

DQ

x ( n)

DQ

DQ

x (n + 4)

250 MHz

DQ

DQ

x (n + 2)

DCM 125 MHz

DQ

DQ

x (n + 6)

DQ

A0-A7

f s = 1 GHz

DREADY 500 MHz

÷2

DQ DDR IOB DQ

P0-P7 = ADC Primary Data Port A0-A7 = ADC AUX Data Port DDR = Double Data Rate 250 MHz

DQ

Channelization 30

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1 GHz Channelizer ADC

x ( n)

h0 ( n)

Receiver 0

h1 (n)

Receiver 1

M-Point IDFT

f s = 1 GHz

hM −2 (n)

Receiver M-2

hM −1 ( n)

Receiver M-1

f s1 = 1e9 /16 = 62.5 MHz

• Each polyphase sub-filter must support a throughput of 1e9/16 = 62.5 Ms/s • A 1 Giga-sample/s 16-point FFT is required Channelization 31

Implementation Statistics • Filter bank arithmetic requirements – 32 x 14 x 62.5e6 = 28 GMACs

• Distributed arithmetic filters used for polyphase filter bank

– Hardware folding factor = 2 • Each subfilter is allocated a 2 clock cycle schedule to execute • Filter bank fclk = 2 x 1e9/16 = 125 MHz • 2vP50-6 – 11,155 slices 47% of the device

• Interesting figure of merit: 28e9/11155 = 2.5 MMACs/logic slice Channelization 32

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1 Giga-sample FFT in System Generator A very high-speed FFT is required for the channelizer 1 Giga-samples/s Built in System Generator

Channelization 33

1 Gs/s FFT in System Generator Butterfly network

Radix-4 butterfly

4-point FFT kernel

Channelization 34

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Implementation Statistics • Vectorized interface – 1 vector delivered/produced each clock cycle

• FPGA utilization – 1,812 slices – 36 embedded multipliers

• • • •

In this design required FFT fclk = 62.5 MHz One transform every 16 ns FFT will support fclk = 210 MHz 8 radix-4 dragonflies – 64 complex additions • 128 x 210e6 = 26.9 GOPs/sec.

– 9 complex multiplications • 7.56 MMACs/sec. Channelization 35

Modified Channelizer • Conventional polyphase transform channelizer produces N maximally decimated output time series • Many comm systems like to operate on multiple samples/symbol – e.g. many timing recovery loops in QAM demodulators

• Could interpolate each channelizer output time-series • Alternative modify channelizer to embed (programmable) rate change

Channelization 36

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On Multichannel Receivers With Arbitrary Uncoupled Selection of ... e j 2π ( f1 / fs ) n

Channel

P:Q Low Pass

Spacing

e j 2π ( f 2 / f s ) n

(P/Q)fs P:Q

Low Pass (P/Q)fs

fs

e

j 2π ( f 3 / f s ) n

P:Q

Low Pass

channel bandwidth and channel sample rate

(P/Q)fs

e

j 2π ( f 4 / f s ) n

P:Q

Low Pass (P/Q)fs

Channelization 37

Conventional Channelizer Application • Channelize • Downsample to Nyquist rate • Interpolate to two times symbol rate

Channelization 38

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Enhanced Channelizer Solution • Replace Interpolator Function With Buffer Addressing

Channelization 39

Performance Specifications for 50-Channel Polyphase Channelizer

Channelization 40

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Time and Frequency response of Remez Filter Design with Modified End Points Impuls e Res pons e, P rototype Filter 0.025

10

x 10

-4

Impuls e Res pons e, Detail

0.02 0.015

5

0.01 0.005

0

0 -0.005 0

100

200

300

400

500

-5 -10

0

10

20

30

40

50

60

Frequency Res pons e, P rototype Filter 10 0 log magnitude (dB)

-10 -20 -30 -40 -50 -60 -70 -80 -30

-20

-10

0 Normalized Frequency f/fChanne l

10

20

30

Channelization 41

Commutators for Standard Input Buffer and for Circular Input Buffer

Channelization 42

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Standard Polyphase Channelizer and Modified Channelizer with Circular Buffers

Channelization 43

Shifting Time Origin for Input Data of Polyphase Filter and of Resetting FFT

Channelization 44

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Content of 64-Point Circular Input Buffer for Two Successive 48 Point Input Blocks

Channelization 45

Shifting Time Origin for Input Data of Polyphase Filter and of Resetting FFT

Channelization 46

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Contents of Transfer Circular Buffer Aligning Origins for Successive Input Blocks

Channelization 47

Implementation

Channelization 48

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Implementation Statistics • 64 Channel channelizer • Arbitrary re-sampling – 1000 slices – 5 embedded mpy – 6 block Virtex-II block memories

Channelization 49

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25