Final Report Ashutosh Jaiswal

Evaluation and Real Time Implementation of Different Techniques for a Wireless Indoor Communication Channel and a Comparative Study of their effect on the BER Ashutosh Jaiswal Master Degree Project Report Aug 2007

Abstract A lot of research has already been done on various coding techniques for an indoor communication channel to improve the performance and reliability. This project focuses on three different communication schemes, their implementation and a comparative evaluation of performance based on the Bit Error Rate (BER). BER is used as a measure because it is directly proportional to the characteristics of the channel and these characteristics pose challenges for transmitting data over space, for which various schemes to transmit and receive data are required. In this project the main schemes being studied and implemented are convolutional encoding, Viterbi decoding and block interleaving. Keywords: Convolutional encoding, Viterbi decoding, channel performance, BER, Interleaving

1 . Introduction Forward Error Correction or channel coding techniques form an essential block in the digital communication system design. This area has been well researched and efficient codes have been developed for various applications. The performance of various codes for digital wireless applications has also been well researched. Indoor wireless networking applications have become very popular as they provide flexibility of location with low infrastructural and maintenance costs. Proper modeling of the wireless indoor channel is critical to evaluate the performance of the end-toend system. The main focus of this masters project was to evaluate the performance of indoor point-to-point wireless data transmission system with channel 1

coding techniques and then comparative evaluation combined with block interleaving technique. Most of the indoor channel are characterized by low Doppler Spreads implying a time invariant channel. In this project the Doppler spread is negligible as the transmitter, receiver and the underlying channel are stationary. The performance of the system was evaluated with convolutional coding and block interleaving for a fading Indoor Rician Channel. BER was evaluated for various Signal to noise ratio’s. However, because there was no means to measure the signal to noise ratio, distance between the transmitter and receiver was varied as it is directly proportional to the SNR. The various steps that were carried out for evaluation of performance are, i)

Transmission and reception of the data over the channel without any coding/decoding. ii) Transmission and reception of the data over the channel with convolutional encoding and Viterbi decoding. iii) Transmission and reception of the data over the channel with encoding/decoding and with block interleaving. For each of these configurations the BER was determine and a plot between the BER and the distance (between transmitter and receiver) was used to evaluate the performance. Real time embedded system implementation of convolutional encoding, Viterbi decoding and block interleaving was accomplished using Texas Instruments TRF6903 bi-directional RF Transceiver and MSP430 Ultra Low Power Baseband Microcontroller.

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2 . TRF 6903 Transceiver The TRF 6903 single chip solution is an integrated circuit intended for use as a low-cost multiband FSK or OOK transceiver to establish a frequency programmable, half duplex, bi-directional RF link. The multichannel transceiver is intended for digital modulated applications in the North American and European 315-MHz, 433-MHz, 868-MHz and 915MHz ISM bands. It operated down to 2.2 V and is designed for low power consumption. Two fully programmable operation modes, Mode0 and Mode1, allow fast switching between two preprogrammed settings without reprogramming the device.

common data rates, is provided by the TRF6903. This feature reduces the need for extensive oversampling and data decisions in the microcontroller during receive. During transmit, the data clock can be used to clock the transmit data from the microcontroller to the TRF6903 at predefined data rates. Figure 1 shows all the interface definitions between the MSP 430 and the TRF6903. Some of these interface pins are optional and may not be needed to establish a functional wireless link.

2.1. Transmitter The transmitter consists of an integrated VCO and tank circuit, a complete synthesizer, and a power amplifier. The dividers, pre-scaler, and a reference oscillator require only the addition of an external crystal and a loop filter to provide a complete PLL with a typical frequency resolution of better than 200 kHz. Since the typical RF output power is approximately 8 dBm, no additional external RF power amplifier is necessary in most applications.

2.2. Receiver The integrated receiver is intended to be used as a single-conversion FSK/OOK receiver. It consists of low noise amplifier, mixer, limiter FM/FSK demodulator with an external LC tank circuit.

2.3. Baseband Interface The TRF 6903 can easily be interfaced to a baseband processor such as the Texas Instruments MSP430 ultralow-power microcontroller. The TRF6903 serial control registers are programmed by the MSP430 and the MSP430 performs baseband operations in the software. A synchronized data clock, programmable for most 2

Figure 1: System Block Diagram for Interfacing to the MSP430

2.4. TRF6903 Evaluation Board The evaluation kit has two circuit boards, where each of them can be used as a transceiver. Each unit has a TRF6903 RF transceiver and a MSP430F449 microcontroller. Each board is capable of sending and receiving half duplex wireless data. The MSP430 MCU flash memory can be repeatedly erased and reprogrammed. The on-chip emulation logic allows real-time debugging and fast code development. The MCU can be programmed via a USB-JTAG interface and the data to transmit and receive uses the RS-232 port. The set up used to carry out the evaluation will be discussed in latter sections.

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3 . System and Protocol Definition 3.1. System Definition The overall wireless UART system setup implemented in the firmware consists of two computers exchanging data wirelessly. The data transmission is half-duplex and bi-directional. The various phases of data transmission are illustrated in Figure 2.

The MAX3232 3-V to 5.5-V RS232 line driver is used for logic level voltage conversion between the computer and the MSP-430 microcontroller. The signal at the UART TX line of the microcontroller is shown in Figure 3. The start bit is a high pulse, 26.04 micro-secs long (38.4 kbps). Then the first data bit is sent beginning with the LSB. After 8 data bits, the stop bit arrives generating a low pulse on the RS-232 line.

3.2. Protocol Definition The RS-232 protocol used to transfer data to and from the computer and the RF protocol used to transmit packets wirelessly is explained in the following sub-sections. Figure 3: RS-232 Protocol

3.2.2. Wireless Protocol The protocol used for wireless packet transmission is illustrated in Table 1. Table 1: Wireless Protocol used for Packed Data Transfer

Bit Rate (kbps) 19.2 38.4 51.2

Bit Duration (us) 52.06 26.04 19.53

Training Sequence (ms) 6 3 2.5

Start Bit Duration (us) 156.18 78.12 58.59

CODING NRZ NRZ NRZ

The entire wireless protocol consists of three parts: i) Training sequence ii) Start Bit iii) Data packet that includes 32 bytes of data and 2 bytes of checksum Figure 2: Various phases of data transmission

3.2.2.1. Training Sequence

3.2.1. RS-232 Protocol The default protocol used for RS-232 serial transmission and reception is 38.4 kbps data rate with eight data bits, one stop bit and no parity. The firmware has been written to support this protocol. 3

Besides the ability to receive return to zero coded signals, the TRF 6903 features the availability to receive NRZ coded signals. This doubles the maximum achievable data transmission rate.

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Master Degree Project Report, Aug 2007 The training sequence is a square wave signal of equal high and low pulses. The voltage across the sample-and-hold capacitor is charged up to the dc value of the received and demodulated signal. After a long enough period to achieve good accuracy of this reference voltage value, the TRF6903 is switched from reception in learning mode, to reception in hold-mode. In the hold mode, the voltage across the sample-and-hold capacitor is maintained. Typically the hold time is several seconds. This makes the reception of a signal with many successive ones or zeros possible. It has two purposes: The first is to enable the receiver to adapt to the transmitted signal, charge the sample-and-hold capacitor to dc value of the signal, and thereby enable reception of NRZ coded signals. The second is to enable the receiver to distinguish between noise or invalid signals and the valid data. Achieving these purposes allows the minimum length of the training sequence to be calculated. The factors to be considered are run-in-time of the receiver (from standby to receive modes), the time during which the microcontroller on the receiver side needs to recognize the training sequence, and some overhead to minimize the number of training sequences that are unrecognized because of timing problems. The firmware implemented in this project uses a training sequence of 3ms long. Figure 4 shows the training sequence used in the firmware.

3.2.2.2. Start Bit The start bit is shown in Figure 4. The purpose of the start bit is to enable the reception of data by marking the beginning of the actual data package and to synchronize the receiver. The length of the start bit can be within a wide range, but it must enable a distinction to be easily made between the pulses of the training sequence and the pulse of the start bit. In this firmware the pulse width is set to three times the pulse length of the training sequence, giving a start bit of 78.12 us duration for a bit rate of 38.4 kbps. 3.2.2.3 Data Packet The data packet is that part of the RF protocol that contains the actual data to be transmitted. The firmware implements a data link for transmitting 32 bytes, as well as for transmitting two additional bytes containing the checksum for these 32 bytes. For data transmission the first two transmitted bytes are checksum of the transmitted data package as calculated by the sender, followed by 32 bytes of actual data. These 34 bytes in the data package are not separated by start and stop bits. Figure 5 shows the data package when sending the 32 bytes of data bytes.

Figure 5: Data Packet- Sending 32 Bytes of Data

4. TRF6903 Register Setup Figure 4: Training Sequence

The TRF6903 is controlled through a serial interface. There are five 24 bit control words (A, B, C, D and

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Master Degree Project Report, Aug 2007 E). The A and B words are almost identical and set the device for two modes, designated as Mode0 and Mode1, which are used to configure the transmit and receive states. The C word sets the reference dividers, the power amplifier bias, and contains various reset bits. The D word is used to trim the external crystal frequency and tune the demodulator. The E word contains the bit-rate select, data clock control bits and the power amplifier bias control registers. The registers used with the wireless UART firmware are shown in Table 2.

5. The Graphic User Interface (GUI) A GUI provided by Texas Instruments is being used for transmission and reception of data for test purposes. A snapshot of the GUI is shown in Figure 6. The GUI provides a means to set the baud rate, select the COM port from where data is to be sent/received and also displays the receive and sent data. If the transmit data is acknowledged, the received packet stream will be displayed in the Received Data list box.

Figure 6: Wireless UART GUI to transmit and receive

6. Implementation of Wireless Transmission

process is depicted in Figure 7. Each step shown in the flowchart is implemented as a function in the firmware. Table 2: TRF6903 Register Settings REGISTER PARAMETER VALUE A PA Attenuation 0 dB Mode 0 TX Charge Pump 0.5mA Frequency Band 915Mhz B PA Attenuation 0dB Mode 0 RX Modulation FSK Brownout Threshold 2.2V Brownout Detector OFF C Reference Divider 48 Reference Frequency 409.6 KHz D Crystal Tune 20.23 pF Reset Signal for PFD Derived from prescaler Crystal Switch Closed E Receive Data Mode Self Train (RXM) Dividers D1, D2, D3 38.4 kbps Transmit Capture select Set Table 3: MSP430 Port Configuration MSP430 Port PURPOSE DIRECTION P1.0 to P1.3 Buttons Output P1.4 to P1.7 LED’s Output P2.0 RXDATA Input P2.1 DCLK Input P2.2 TXDATA Output P2.3 RX-FLAG Input P2.4 USART0 TX DATA Output P2.5 USART0 RX DATA Input P2.6 LOCKDET Input P2.7 BROWN-OUT DET Input P3.0 to P3.3 DIP SWITCH Input P3.4 LN/HOLD Output P3.5 STDBY Output P3.6 CLK Output P3.7 MODE Output P4.0 DATA Output P4.1 STROBE Output P6.0 to P6.3 LED’s Output

The firmware details used to implement wireless transmission is explained in this section. The firmware has been written using IAR embedded workbench. The flowchart of the transmission 5

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6.1. Configure Input Output Ports The MSP430 ports configured for input and output are shown in Table 3. All the ports are configured as general purpose input/output ports except USART0 TXDATA, USART0 RXDATA, RXDATA and DCLK. These pins are configured as peripheral module pins. This is accomplished using the Function Select Register Pxsel. This peripheral module selection configures RXDATA as Timer A Capture Input and DCLK as Timer B Capture Input.

system cost and ultralow-power consumption. The FLL+ features digital frequency-locked loop (FLL) hardware. The FLL operates together with a digital modulator and stabilizes the internal digitally controlled oscillator (DCO) frequency to a programmable multiple of the LFXT1 watch crystal frequency. The FLL+ clock module can be configured under full software control. After a PUC, MCLK and SMCLK are sourced from DCOCLK at 32 times the ACLK frequency. When a 32,768-Hz crystal is used for ACLK, MCLK, and SMCLK stabilizes to 1.048576 MHz. The SCFQCTL, SCFI0, SCFI1, FLL_CTL0, and FLL_CTL1 registers configure the FLL+ clock module. The FLL+ can be configured or reconfigured by software at any time during program execution. In the firmware, the DCO frequency is set to 75 times the watch crystal frequency = 75 x 32,768 = 2.4576 MHz. Thus the MCLK and SMCLK are sourced by a 2.4576-MHz clock.

6.3. Configure the UART

Figure 7: Transmit Flowchart

The ports 2.4 and 2.5 of MSP430 are configured to transmit and receive data to/from the serial port. The USART is configured for UART mode by clearing the SYNC bit in the UCTL0 register. The character length is chosen to be 8 bits by setting the CHAR bit in the UCTL0 register. Initially, the UART is disabled by clearing the SWRST bit setting in the UCTL0 register. SMCLK is configured to source the Baud rate Clock BRCLK by configuring the UTCTL0 register. The UART baud rate control register UBR00 is set to 64 so that the baud rate generated is 2.4576 MHz/64 = 38.4 kbps. Thus, the UART is configured to operate at 38.4 kbps.

6.2. Configure Baseband clock 6.4. Configure TRF6903 A 32.768-kHz watch crystal is used as a clock source for MSP430. The watch crystal is connected to pins 8 and 9 of the MSP430. The frequency locked loop (FLL+) clock module supports low

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The firmware routines used to program the TRF6903 is explained in this section. Depending on the transceiver bit rate chosen in the wireless

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Master Degree Project Report, Aug 2007 UART GUI, the clock recovery bit rate dividers D1, D2, and D3 is chosen to program register E. The transceiver baud rate is set by DR_DLY_CNT, a global parameter used across all files in the project. The formula used for calculation is: Transceiver Bit Rate =

2.4576 DR DLY CNT + 1

If the bit rate is 38.4 kbps DR_DLY_CNT = 63; if the bit rate is 19.2 kbps DR_DLY_CNT = 127; If bit rate is 51.2 kbps DR_DLY_CNT = 47.

7. Implementation of Wireless Reception Once the TRF6903 is initialized and configured, it operates in the receive mode waiting for a training sequence. The wireless receive protocol has three stages, • Training sequence recognition • Start bit recognition • Data bits recognition

7.1. Detection of Training sequence The MSP430 on the EVK board programs the TRF6903 for reception in learn mode at the selected frequency. The TRF6903 is then switched to active mode. The MSP430 scans the received signal for a valid data package. Because the band always contains noise, the data slicer output necessarily always delivers a digitized signal component. Another cause for a signal at the data slicer output is another application using the same frequency band. In any case, the TRF6903 always delivers a signal to RXDATA when it is active and in receive mode. The MSP430 must distinguish between valid and invalid signals. The MSP430 uses the Timer_A module to make this distinction. The clock source for Timer_A is MCLK and is clocked at 2.4576 MHz. The selected mode is the continuous-up mode. In this mode Timer_A counts continuously from 0 to FFFFh, then generates an

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interrupt and restarts. The RXDATA signal is applied to a capture-compare block. In recognizing the training sequence, the code distinguishes between three different states: • No valid pulse is detected. • Fewer than 16 valid consecutive pulses are detected. • More than 16 valid consecutive pulses are detected—the training sequence is recognized.

7.2 Detection of Start Bit The principle of start-bit recognition is similar to the detection of the training-sequence pulse except that the start bit consists of a single pulse. To distinguish between the pulses of the training sequence and the pulse of the start bit, the length of the start bit was set to three times 26.04 s, i.e., three times as long as the pulses of the training sequence. The falling edge of the start-bit pulse is the trigger for the scanning and reading of the data package.

7.3 Detection of Data Bits Data reception is handled using the TRF6903 clock recovery feature. The field RXM in register E determines the clock recovery mode used in TRF6903. If RXM is set to Self Train Mode, the data clock circuitry provides an output at terminal 27 (DCLK) a data clock based on a programmable bit rate. DCLK is programmed at the configured transceiver bit rate. The received data RXDATA is synchronous to the bit rate clock at DCLK. The RXDATA transition is timed to coincide with the falling edge of DCLK, thus the rising edge of DCLK is exactly at the center of the RXDATA bit. The MSP430 can then latch RXDATA on the rising edge of DCLK. In the wireless UART firmware the MSP430 is programmed to latch RXDATA on the falling edge of DCLK rather than the rising edge as indicated before. This is recommended for data rates 30 kbps and higher. This is because the ISR

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Master Degree Project Report, Aug 2007 that services the DCLK trigger has latency of about 6-8 s. This when added to the actual code execution latency, results in a total latency of about 10 s from the triggering of DCLK to the time RXDATA value is latched by the MSP430. For data rates of the order of 38.4 kbps (a pulse width of 26.04 s), there is about 13.02 s from the positive edge of DCLK (pulse width center) to the next data bit. Thus, if the MSP430 is triggered on the rising edge of DCLK, there is a chance that due the jitter of the RXDATA signal incorrect bit may be latched resulting in bit errors. This is illustrated by the timing diagram for a 38.4-kbps bit rate system in Figure 8

Figure 9: Actual Project Set-up

transmit data waits until it is full, as the data from PC comes into it. Once it is full this data is transferred over the air via TF6903. In Figure 10, there is a USB cable that interfaces the EVM via a USB-JTAG converter. This is used to write the program on the MCU’s flash memory.

Figure 8: Receive data reception using DCLK

The BLUE arrow (point 1) indicates the time when the MSP430 is triggered. Due to the latency in the interrupt servicing and execution, the RXDATA is actually sampled at point 3 indicated by RED arrow. This occurs about 10 s after the MSP430 is triggered.

8. Project Set Up Figure 10: Block Diagram of Project Set-up

The actual project set-up is shown in Figure 9. A block diagram of the set-up is depicted in Figure 10. As shown in the figure, the EVM is interfaced with the PC via RS-232 cable. This RS-232 cable is used to transmit and receive data to and from the MSP430. While receiving MSP430 fills a buffer until all 32 bytes are full. As soon as the overflow occurs, the data in the buffer is sent to the PC via the RS-232 serial interface. The serial port of the PC can be configured used a hyper terminal to read the data received by the MSP430. On the other hand, while transmitting, the buffer used to 8

9. Transmission without encoding/decoding The first step was implementation of a wireless link for sending and receiving data. The first step was to make sure that the RS-232 protocol and the wireless protocol are implemented appropriately and the data is being transmitted over the link correctly. In order to implement this, the data being sent from the PC to the transmitter was directly put into the transmit buffer without any modification. At this point the RS-232 protocol was implemented St. Mary’s University, San Antonio

Master Degree Project Report, Aug 2007 to make sure that the data is being accumulated in the transmitting buffer. Once the data was successfully exchanged between the PC and the MCU, the next step was to program the TRF6903 to transmit the data as it is, without any encoding decoding. On the receiving side, the data is directly stored in the receiving buffer until all 32 bytes are received. On arrival of all the 32 bytes, the data is then sent via the RS-232 line to the receiving PC. This data is displayed on the GUI or the hyper terminal. For this case the data is transmitted as it is, without any encoding. Measurements of BER were taken for this case and the results were evaluated. The results are summarized in latter sections.

10. Transmission using Encoding/Decoding The encoding scheme used for the project is Convolutional Encoding. The decoding scheme used is Viterbi Decoding. A detailed explanation of these schemes and their implementation will be discussed in this section.

The ratio k/n is called the code rate of the encoder. It represents the amount of information per coded bit. The integer K is called the constraint length of the code. It represents the number of k-tuple stages in the encoding shift register. An important characteristic of convolutional codes, unlike block codes, is that the encoder has memory. The n-tuple emitted by the convolutional encoding procedure is not only a function of an input k-tuple, but is also a function of the previous K-1 input k-tuples. In practice n and k are small integers and K is varied to control the capability and complexity of the code. The convolutional encoder used in this project is shown in Figure 11. The figure illustrates a convolutional encoder with a constraint length of K = 3. There are n = 2 modulo-2 adders; thus the code rate k/n is ½. At each input bit time, a bit is shifted into the leftmost stage and the bits in the register are shifted one position to the right. Next, the output switch samples the output of each modulo-2 adder (i.e. first the upper adder and then the lower adder), thus forming the code symbol

10.1. Convolutional Encoding Convolutional Encoding is a Forward Error Correction (FEC) technique used in continuous one-way and real time communication links. It can provide substantial improvement in BER so that small, low power, inexpensive transmitters can be used in such applications as satellites and handheld communication devices. It is a method of adding redundancy to a data stream in a controlled manner to give the destination the ability to correct bit error without asking the source to retransmit. Convolutional codes add reliability to the link while eliminating the need for a reverse channel. They are used in applications where retransmission of data is impractical or impossible, such as in real time speech transmissions. A convolutional encoder is a linear finite state machine described by three integers n, k and K. 9

Figure 11: Convolutional Encoder

pair making up the branch word associated with the bit that was at the input. The sampling is repeated for each input bit. The choice of connections between the adders and the stages of register give rise to the characteristics of the code. Any change in the choice of connections results in a different code. The connections are, of course, not chosen or changed arbitrarily. The problem of choosing connections to yield good distance properties is complicated and has not been solved in general; however, good codes have been found St. Mary’s University, San Antonio

Master Degree Project Report, Aug 2007 by computer search for all constraint lengths less than about 20. Now consider that input bits, m = 101 is convolutionally encoded with the encoder shown in Figure 11. The three message bits are inputted, one at a time, at times t1, t2 and t3. Subsequently, (K-1) = 2 zeros are inputted at times t4 and t5 to flush the register and thus ensure that the tail end of the message is shifted the full length of the register. The output sequence in this case will be 11 10 00 10 11, where the leftmost symbol represents the earliest transmission. The entire output sequence, including the code symbols as a result of flushing, is needed to decode the message. To flush the message from the encoder requires one less zero than the number of stages in the register or (K-1) flush bits. 10.1.1. Trellis Diagram The convolution encoding process can be represented using a diagram called the Trellis diagram. This diagram will form the basis for decoding of the sequence on the receiving side. The trellis diagram for a convolutional encoder with code rate ½ and K=3 is shown in Figure 12.

Figure 12: Encoder Trellis Diagram (rate= ½, K=3)

In drawing the trellis diagram, we use the convention – a solid line denotes the output generated by an input bit zero, and a dashed line denotes the output generated by input bit one. The nodes of the trellis characterize the encoder states; the first row nodes correspond to the state a=00, the second and subsequent rows correspond to the

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state b=10, c=01 and d=11. At each unit of time the trellis requires 2k-1 nodes to represent the 2k-1 possible encoder states. The trellis in this example assumes a fixed periodic structure after a trellis depth 3 is reached (at time t4). In the general case, the fixed structure prevails after a depth K is reached. At this point and thereafter, each of the states can transition to one of the two states. Of the two outgoing branches, one corresponds to an input bit zero and the other corresponds to an input bit one. In Figure 12, the output branch words corresponding to the state transitions appear as labels on the trellis branches. One time-interval section of a fully formed encoding trellis structure completely defines the code. The only reason for showing several sections is for viewing a code-symbol sequence as a function of time. The state of convolutional encoder is represented by the contents of the right most (K-1) stages in the encoder register. 10.1.2 . Implementation of Convolutional Encoding The packet size of the coded system was 288 bytes since the input data bytes per packet was chosen as 96 bytes. For the tests, 2000 packets are sent from the PC to the TRF6903 valuation kit through the serial port using the RS-232 protocol. The total number of user data bits sent over the air is 1.536 million. The convolutional encoding algorithm is designed to work with a data size of 2 bytes. Rate ½ convolutional encoding results in data size of 4 bytes. The encoding also results in 4 flush bits (2 for each byte). The MSP430 registers operate in terms of 2 bytes or a word. Thus 2 additional bytes are needed to store the flush bits. Encoding operation results in generating an output of 6 bytes for every 2 bytes input, 2 bytes input => 4 bytes encoded output + 2 bytes flush bits. The flowchart for implementation of convolutional encoding is shown in Figure 13. The program first waits for the 96 bytes of the data to be available. Once the buffer is full, the first two

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Master Degree Project Report, Aug 2007 bytes are taken into consideration. These bytes are convolutionally coded using the XOR function (see the Appendix code) and the byte counter is incremented by two in order to keep a track of the number of bytes that have been processed. The byte counter is then checked to see if all 96 bytes are processed. In case all 96 bytes are processed, the packet counter is incremented and checked until 2000 packets are transmitted. On the receiver side the same process is carried out for decoding and the BER is evaluated.

of Viterbi decoding is that the complexity of the Viterbi decoder is not a function of the number of symbols in the codeword sequence. The algorithm involves calculating a measure of similarity, or distance, between the received signal, at a time ti , and all the trellis paths that could not possibly be the candidates for maximum likelihood choice. When two paths enter the same state then the one having the best metric is chosen; this path is called as the surviving path. This selection of surviving paths is performed for all states. The decoder continues in this way to advance deeper into the trellis, making decisions by eliminating the least likely paths. The early rejection of the unlikely paths reduces the decoding complexity. 10.2.1. Decoding using Trellis diagram

Figure 13: Flowchart for Convolutional Encoding

10.2 Viterbi Decoding The Viterbi decoding algorithm was discovered and analyzed by Viterbi in 1967. The Viterbi algorithm essentially performs maximum likelihood decoding; however reduces the computational load by taking advantage of the special structure in the code trellis. The advantage

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In order to understand the decoding process using the trellis diagram, let us consider an example. In the decoding process the Hamming distance is used as a measure of the likelihood of a code word/symbol. Hamming distance is nothing but the number of bits by which a code differs from another. For example if we consider two code words 00 and 01, then the hamming distance between them is 1 since only one bit differs when both are compared. On other hand the code words 00 and 11 will have a hamming distance of 2. A trellis diagram similar to that shown in Figure 12 can be used to represent the decoder. This is shown in Figure 14. The figure shows how a bit error is corrected using the viterbi decoding algorithm. An input sequence of 1 1 0 1 1 is being considered. On performing convolutional encoding, the transmitted code word becomes 11 01 01 00 01. Assuming that due to channel characteristics, a bit error is added to the transmitted sequence and the received sequence is 11 01 01 10 01. There is a bit error in the fourth code word. Each branch in the decoder trellis diagram has been labeled with the Hamming distance between

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Figure 14: Decoder Trellis Diagram (rate= ½, K=3)

the received code symbol and the branch word corresponding to the same branch from the encoder trellis. The branch words seen on the encoder trellis branches are known a priori to both the encoder and the decoder. The encoder branch words are the code symbols that would be expected to come from the encoder output as a result of each of the state transitions. The labels on the decoder trellis branches are accumulated by the decoder on the fly i.e. as the code symbols are received; each branch of the decoder is labeled with a metric of similarity between the received code symbols and each of the branch words for that time interval. From the received sequence, shown in Figure 14, we see that the code symbols received at time t1 are 11. In order to label the decoder branches at time t1 with the appropriate Hamming distance metric, we look at the trellis of Figure 12 (encoder trellis). Here we see that a state 00 00 transition yields an output branch word of 00. But we received 11. Therefore, on the decoder trellis we label the state 00 00 transition with hamming distance between them, namely 2. Looking at the encoder trellis again, we see that the state 00 10 transition yields an output branch word of 11, which corresponds exactly with the code symbols we received at time t1. Therefore on the decoder trellis, we label the state 00 10 transitions with a Hamming distance of 0. In summary, the metric entered on a decoder trellis branch represents the difference (distance) between what was received and what “should have

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been” received had the branch associated with that branch been transmitted. In effect, these metrics describe a correlation-like measure between a received branch word and each of the candidate branch words. We continue labeling the decoder trellis this way as the symbols are received at each time ti. The decoding algorithm uses these hamming distance metrics to find the most likely path through the trellis. At time t1 the received code symbols are 11. From the state 00 the only possible transition is to state 00 or state 10. State 00 00 transition has branch metric 2; the state 00 10 transition has a path metric 0. At t2 there are two possible branches leaving each state. The corresponding metrics of these transitions would be 3, 3, 2 and 0 (from top to down) as shown in Figure 15, corresponding to

Figure 15: Survivors at t3

the terminating state. At time t3 there are again two branches from each state. As a result there are two paths entering each state at time t4. One path entering each state can be eliminated, namely the path having a higher metric. Should the metrics of two paths be same then one is chosen using an arbitrary rule. At this point in the decoding process, there is only a single surviving path, termed as the common stem, between the times t1 and t2. Therefore the decoder can now decide that the state transition, which occurred between times t1 and t2, was 00 01. Since this transition is produced by an input bit one, the decoder outputs a one as the first decoded bit.

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Master Degree Project Report, Aug 2007 10.2.2. Implementation of Viterbi Decoding Encoding is done in chunks of 2 bytes in order to perform optimum Viterbi Decoding. The delay in decoding a longer information sequence is usually too long for most practical applications. Moreover, the memory required to store the entire length of surviving sequences is large and expensive. The solution is to modify the Viterbi algorithm to produce a fixed decoding delay without significantly affecting the optimal performance of the algorithm. The modification is to retain at any given time t only the most recent ‘x’ decoded information bits (symbols) in each surviving sequence. As each new information bit is received, a final decision is made on the bit (symbol) received ‘x’ branches back on the trellis, by comparing the metrics in the surviving sequences

Figure 16: Flowchart for Viterbi decoding

and deciding in favor of the bit in the sequence having the largest metric. It ‘x’ is chosen sufficiently large, all surviving sequences will

contain the identical decoded bit (symbol) ‘x’ branches back in time. That is, with high probability, all surviving sequences at time t stem from the same node at t-x. The flowchart for Viterbi decoding is shown in Figure 16. The first 6 bytes are processed at a time from the received packet and Viterbi decoding is performed until all 288 bytes are processed. The decoded sequence is stored in a buffer in order to compare it with the known transmitted sequence for determining the BER.

11. Transmission using Block Interleaving In case of bit errors, encoding and decoding schemes implement necessary error correction technique. However, in case there is burst of errors (like in a fading channel), then the encoding and decoding schemes do not solve the problem. Interleaving is implemented in order to distribute a burst of errors over the bits and appear the error to look like bit errors rather than a burst of errors. In other words interleaving transforms these error bursts into statistically independent errors. On the receiving side de-interleaving takes place before decoding the received data. A simple block interleaver is utilized in this project. The encoded symbols are written column by column into a matrix of I rows and J columns. The number of rows is termed the interleaving depth and the number of columns is termed the interleaving span. The channel symbols to be transmitted are then read row by row, and the received coded symbols are reordered in the reverse manner. Thus, two adjacent coded symbols are separated by (J-1) symbols during transmission. Since the receiver must wait until it has full matrix before reordering the symbols, interleaving introduces a transmission delay.

11.1 Implementation of Block Interleaving A simple 16X144 (2304 bits) block interleaver is

13

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Master Degree Project Report, Aug 2007 used to spread the burst errors. The entire coded packet of 288 bytes (2304 bits) is stores in RAM and then block interleaved. This operation is illustrated in Figure 17.

Figure 17: The 16X144 block interleaver

The incoming data bits are stored in the matrix form with 16 rows and 144 columns. The data bits are written column by column. Then RF transmission takes place row by row. Thus the order of transmission of bits for the above arrangement shown in the figure is 1, 17, 33…..2289, 2…etc. It can be seen that the adjacent bits are separated by 144 bits when transmitted. Exactly the reverse operation takes place at the deinterleaver. The received bits are then written row by row and read column-wise.

12. Bit Error Rate The Bit Error Rate (BER) may be defined as the ratio of the number of error bits received over a period of time to the total number of bits received over that period of time. It can be written in equation form as, BER = Number of error bits received over time T Total number of bits received over time T BER is being used in this project as a measure of performance of the system because it is directly proportional to the channel characteristics as channel characteristics are responsible for inducing errors into a stream of bits transmitted over the channel. External noise, interference etc are some of the channel characteristics.

14

12.1. Implementation of BER measurement The BER measurement was performed by running the program in a loop and comparing the received data with a known transmitted data. Hyper Terminal was used to transmit data in a loop for number of iterations and the size of data was kept 3 times larger than the original data (3X 32 bytes= 96 bytes) in order to have a larger sample size. The reason to have a large sample size is to determine the BER of sufficient magnitude. On the receiving side, each bit is compared with the known data bits, bit by bit and a counter keeps track of the number of error bits. So if there are 100 error bits for 2000 iterations of 96 bytes of data (288 bytes of coded data), then the BER would be 100/ (2000X288X8) = 21.7X10-6. Based on this a code was written for measuring the BER for various distances between the transmitter and the receiver. The results are summarized in the following section.

13. Results Extensive measurements were conducted in an apartment complex building. The goals of the measurement were to obtain a graph of the distance between the transmitter and receiver against the bit error rate. A Hyper Terminal software called ‘Eltima - Advanced Serial Port Software’ was used to transmit the data bytes. The software had means to set parameters such as the number of iterations for which the data should be transmitted, the delay between each iteration and definition of the data itself that has to be transmitted. The number of iterations was set to 2000 and a data packet of 96 bytes was used for transmission. This data was encoded and the encoded data resulted into 288 bytes. On the receiving side a small code was written that would compare the received data bit by bit with the transmitted data (after decoding and de-interleaving). A counter would keep track of the number of bits differing from the original data.

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Master Degree Project Report, Aug 2007 This process was iterated for 2000 times, while the counter maintaining the error bits count was incremented outside this loop. At the end, the number of error bits was extracted from the program. The measurements were made for an uncoded system, coded system and for coded + interleaved system. The BER values attained during the test measurement are shown in Table 4. Table 4: BER values at various distances for different schemes Un-coded Coded Coded + Distance (m) Interleaved 25 142.8X10-3 125X10-3 72.5X10-3 -3 -3 20 50X10 21.7X10 11.1X10-3 -3 -3 15 12.5X10 4.5X10 1.72X10-3 -3 -3 10 5X10 1.08X10 1.15X10-3 -3 -3 5 10 0.2X10 0.11X10-3

The BER vs. Distance plot is shown in Figure 18. The nature of the various curves is as expected and can be explained. The plot was generated using MATLAB program. The BER values have been plotted on a logarithmic scale in order to see the change in BER more clearly.

Figure 18: BER (vs.) Distance Plot

From the plot it is clear that the BER for the uncoded data would be the maximum, hence making the system prone to higher error rate. The BER for

15

the coded signal and the BER of the coded + interleaved signal is almost the same for distances between 20m~5m. However, at greater distance we can see that the BER of the coded + interleaved data is better than the BER of the coded data alone. The reason for this is that at greater distance the fading effects of the channel are more, hence affecting the S/N ratio of the system by a greater factor, and hence increasing error bursts. Therefore, with these results it can be clearly stated that communication scheme such as encoding/decoding improve the BER by forward error correction, when compared to the un-coded system where the BER is high. However, interleaving technique adds more robustness to bit errors by distributing the burst of errors as statistically independent errors.

14. Conclusion A wireless communication system for indoor channel was successfully implemented along with various schemes such as convolutional encoding, viterbi decoding and block interleaving. Successful measurements of BER were made for different schemes and the performance of the system was evaluated. A good understanding of protocols such as RS-232 and wireless protocol was achieved. The project served as means to explore and learn programming techniques for a wireless system using a transceiver and a microcontroller. During the course of project a lot of amendments were made to the original proposed plan, in order to consider practical situations. One example was using distance as a measure for S/N ratio due to lack of means to measure the S/N of the received signal and due to its complexity. However, the results obtained were very consistent with the theoretical counterparts and helped in understanding the behavior of a practical wireless system.

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Master Degree Project Report, Aug 2007

15. References [1] Andrew H. Snelgrove, The Design of a Programmable Convolutional Encoder using VHDL and FPGA, Thesis Report – Naval Postgraduate School, Monterey, California, December 1994. [2] Xun Liu, Marios C. Papaefthymiou, Design of a High-Throughput Low Power IS95 Viterbi Decoder, Advanced Computer Architecture Laboratory, Dept. of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, Michigan, June 2002. [3] Harsha Rao, Implementing a Bidirectional Wireless UART Application with TRF6903, Application Note, Digital Radio RF Applications, Texas Instruments, September 2004. [4] User Guide: TRF6903 with MSP430 – Demonstration and Development Evaluation Kit [5] User Guide: MSP430x4xx Family – Texas Instruments. [6] Data Sheet: MSP430x4xx Family – Texas Instruments [7] Data Sheet: TRF6903 Transceiver – Texas Instruments

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Master Degree Project Report, Aug 2007

APPENDIX Some parts of the code were provided by Texas Instruments ;******************************************************************************************************* ;; ; This code supports the transmition and reception of 32 data bytes and 2 checksum bytes. ; It supports an acknowledge. ; The data transmission rate is 38.4 kbit/s on the RF side ; The data transmission rate at the RS232 port is 19.2 kbit/s ; ; Written by: Ashutosh Jaiswal ; St. Mary's University, San Antonio ; Master Degree Project ; ;******************************************************************************************************* #include "MSP430X14X.H" RAM_orig FLASH_orig

EQU EQU

00200h 0F000h

NAME

TRF6903_EVK RSEG

CODE

; RAM start ; F1121 FLASH start

; beginning of the code

START ;*********************************** main ************************************************************** ; Calls all the subroutines ; Is the frame for the whole program ;******************************************************************************************************* main MOV

#0300h,SP

; initialize system stack pointer

;;;;;;;;;;;;;;;;;;;;;;; MOV #5468h,&0x0220 MOV #6973h,&0x021E MOV #2069h,&0x021C MOV #7320h,&0x021A MOV MOV MOV MOV

#7465h,&0x0218 #7374h,&0x0216 #696Eh,&0x0214 #6720h,&0x0212

MOV MOV MOV MOV

#6174h,&0x0210 #2066h,&0x020E #756Ch,&0x020C #6C20h,&0x020A

MOV MOV MOV MOV

#7377h,&0x0208 #696Eh,&0x0206 #6720h,&0x0204 #2020h,&0x0202

CALL

#encode

DINT MOV CALL

#WDTPW+WDTHOLD,&WDTCTL #initialization

; initialization of the TRF6900 and

; ; ; ;

general Interrupt disable write with password 5A00h, WDT off initialization of the TRF6900 and MSP430 settings

loop_main

17

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Master Degree Project Report, Aug 2007 CALL BIC BIC CLR CALL BIC BIC BIS BIS

#receive_RF #TAIE,&TACTL #CCIE,&CCTL1 counter #rs232_send #CCIFG,&CCTL1 #TAIFG,&TACTL #TAIE,&TACTL #CCIE,&CCTL1

; ; ; ; ; ; ; ; ;

receive 10x8bits disable Timer_A interrupt disable CCR1 interrupt set counter value to 0 transmits the received data via RS232 Port reset interrupt flag reset interrupt flag enable interrupt enable interrupt

JMP

loop_main

; end of the main routine

reset_wdt

end_main ;********************************* Intialization ******************************************************* ; affects: clock settings ; intializes the hardware ; clearing oscillator fault flag !!! necessary for MSP430 ;******************************************************************************************************* initialization ;****************************** Clock Settings ********************************************************* ; 1. LFXT1CLK-signal is driven by the external 2.4576Mhz crystal ; 2. ACLK is 1/8*LFXT1CLK ; 3. MCLK directly coupled to LFXT1CLK (used only for the CPU) ; 4. SMCLK directly coupled to LFXT1CLK (used for timer_A during code reception) ;******************************************************************************************************* test ; BIS initialize_clock MOV.B

#OSCOFF, SR ; #0C0h,&BCSCTL1

MOV

#000Fh,wait_r

CALL

#wait_x_cycles

;BIC

#OSCOFF, SR ;

MOV

#0FFFh,wait_r

CALL

#wait_x_cycles

initialize_port1 MOV.B

turn off ; ACLK/1 ; ; ; ; ; turn on

#txd,&P1OUT

MOV.B

#stdb_rs232+data+clk+tx+txd,&P1DIR

MOV.B

#rx+rxd,&P1SEL

initialize_port2 MOV.B

MOV.B

high frequency oscillator selected oscillator on for programming purpose MSP430P112 wait routine, waits 3+x*13 cycles

#LED3,&P2OUT

#stdb_trf6903+mode+cts+LED3,&P2DIR

; for programming purpose ; MSP430P112 ; wait routine, waits 3+x*13 cycles

; ; ; ; ; ; ; ;

set TXD_MSP(P1.1), TXD_MSP by default high reset TXDATA(P1.4), DATA(P1.7), CLK(P1.6), STROBE(P1.5) switch DATA(P1.7), CLK(P1.6), TXDATA(P1.4), TXD(P1.1) and stdb_rs232(P1.0) to output dir. select the module function for P1.3 (TA2), RXD P1.2 (TA1)

; ; ; ; ;

reset P2.0,CTS (-> CTS set!), STANDBY_TRF6903(P2.5), MODE(P2.1) -> receive, set LED3(P2.3), System Mode switch STANDBY_TRF6903(P2.5), MODE(P2.1), CTS(P2.0) to output, LOCKDET(P2.4) input

initialize_receive_status CLR &data_rx_state

; reset receive status

oscillator_flag BIC.B MOV CALL

; reset the oscillator fault flag ; wait 3 + Fx13 cycles ; call the wait routine

2

#02h,&IFG1 #0Fh,wait_r #wait_x_cycles

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Master Degree Project Report, Aug 2007 BIT.B JNZ BIC.B

initialize_Clock BIS MOV.B

#02h,&IFG1 oscillator_flag #02h,&IFG1

#SCG1,SR #0C8h,&BCSCTL2

; test the oscillator fault flag ; clear oscillator fault flag

; SELS = 1 LFXT1CLK source for SMCLK

;------------------------------------------------------------------------------------------------------; programming the 4 words to TRF6903 CALL #program_DDS0_receive_learn CALL #program_DDS1_send CALL #program_send_FSK CALL #program_receive_FSK_learn initialize_CCR1_interrupt MOV

#CCIE+CAP+CMNEG,&CCTL1

; interrupt enable, capture mode, neg. edge ; for RS232 reception

end_intialization RET ;**************************** Programming the TRF6903 ************************************************** ;******************************* program_DDS0_receive_learn ******************************************** ; purpose: programs the DDS_0 for FSK Reception in learn mode (see further settings below) ; (Mode 0, A-word), changed settings for the US ISM band !!! ; ;******************************************************************************************************* program_DDS0_receive_learn MOV #023h,word_h MOV #05029h,word_l

CALL

; frequency for Mode 0, receive FSK in learn ; mode, DDS_0 settings for 904.3MHz, ; 25.6MHz system crystal, 10.7MHz IF

#program_TRF6903

end_program_DDS0_receive_learn RET ;******************************* program_DDS1_send ***************************************************** ; ; purpose: programs the DDS_1 for Transmision (see further settings below) ; (Mode 1, B-word), changed settings for the US ISM band !!! ; ;******************************************************************************************************* program_DDS1_send MOV MOV

CALL

#063h,word_h #0BB21h,word_l

; frequency for Mode 1, send ; DDS_1 settings for 915MHz, ; 25.6MHz system crystal, 10.7MHz IF

#program_TRF6903

end_program_DDS1_send RET ;******************************* program_send_FSK ****************************************************** ; ; purpose: programs the module Mode 1 for FSK transmission (see further settings below) ; (Enable register for PLL, Data Slicer and Mode 1 settings, C-word) ; ;******************************************************************************************************* program_send_FSK MOV MOV ; ; ; ;

3

1_LNAM 1_MIX 1_IF 1_DEM

[bit [bit [bit [bit

#0BCh,word_h #09E00h,word_l

0..1] 2] 3] 4]

00b 0b 0b 0b

disabled disabled disabled disabled

; Module Mode 1, send Low noise amplifier operation mode Enable Mixer Enable 1st IF Amplifier Enable Limiter/Demodulator

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Master Degree Project Report, Aug 2007 ; ; ; ; ; ; ; ; ; ; ; ; ; ;

1_RSSI 1_DSW 1_LPF 1_SLC 1_PA

[bit [bit [bit [bit [bit

1_VCO 1_PLL

SLCTL MS NPLL APLL

5] 6] 7] 8] 9..10]

0b 0b 0b 0b 11b

disabled conn. to Demod. disabled disabled 0dB att.

[bit 11] [bit 12]

1b 1b

enabled enabled

[bit [bit [bit [bit [bit

00b 1b 0b 0b 111b

learning mode FSK 256 140

13..14] 15] 16] 17] 18..20]

CALL

Enable Limiter/RSSI Data Switch (Demodulator or RSSI) Enable LPF Amplifier Enable Data Slicer Power Amplifier gain value in TX mode (see also MS bit) Enable VCO Enable PLL ( DDS System, RF divider, Phase Comparator and Chargepump) not used Slicer mode select bit modulation mode select RF divider ratio for PLL acceleration factor for the charge pump

#program_TRF6903

end_program_send_FSK RET ;******************************* program_receive_FSK_learn ********************************************* ; purpose: programs the module Mode 0 for FSK reception in learn mode (see further settings below) ; (modulation and mode 0 settings, D-word) ; ;******************************************************************************************************* program_receive_FSK_learn ; MOV #0C6h,word_h ; MOV #0D99Fh,word_l MOV MOV ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;

#0C7h,word_h #0199Fh,word_l

0_LNAM

[bit 0..1]

11b

normal

0_MIX 0_IF 0_DEM 0_RSSI 0_DSW

[bit [bit [bit [bit [bit

2] 3] 4] 5] 6]

1b 1b 1b 0b 0b

enabled enabled enabled disabled con. to Dem.

0_LPF 0_SLC 0_PA

[bit 7] [bit 8] [bit 9..10]

1b 1b 00b

enabled enabled disabled

0_VCO 0_PLL

[bit 11] [bit 12]

1b 1b

enabled enabled

MR

[bit 13..20] 0010 0110b

CALL

; Modulation, Module Mode 0, receive

; Modulation, Module Mode 0, receive Low noise amplifier operation mode operation Enable Mixer Enable 1st IF Amplifier Enable Limiter/Demodulator Enable Limiter/RSSI LPF Amplifier input routed to Demodulator (FSK) or to RSSI (OOK) Enable LPF Amplifier Enable Data Slicer Power Amplifier gain value in TX mode (see also MS bit) Enable VCO Enable PLL (DDS System, RF divider, Phase comparator and Chargepump) FSK frequency deviation register (corresponds with 60kHz modulation)

#program_TRF6903

end_program_receive_FSK_learn RET

;******************************* program_receive_FSK_hold ********************************************** ; purpose: programs the module Mode 1 for FSK reception in hold mode (see further settings below) ; (enable register for PLL, Data Slicer and Mode 1 settings, C-word) ; ;******************************************************************************************************* program_receive_FSK_hold MOV #0BCh,word_h MOV #01E00h,word_l ; ; ; ;

4

1_LNAM 1_MIX 1_IF 1_DEM

[bit [bit [bit [bit

0..1] 2] 3] 4]

00b 0b 0b 0b

disabled disabled disabled disabled

; Modulation, Module Mode 1, receive Low noise amplifier operation mode Enable Mixer Enable 1st IF Amplifier Enable Limiter/Demodulator

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Master Degree Project Report, Aug 2007 ; ; ; ; ; ; ; ; ; ; ; ; ; ;

1_RSSI 1_DSW 1_LPF 1_SLC 1_PA

[bit [bit [bit [bit [bit

1_VCO 1_PLL

SLCTL MS NPLL APLL

5] 6] 7] 8] 9..10]

0b 0b 0b 0b 11b

disabled conn. to Demod. disabled disabled 0dB att.

[bit 11] [bit 12]

1b 1b

enabled enabled

[bit [bit [bit [bit [bit

00b 0b 0b 0b 111b

hold mode FSK 256 140

13..14] 15] 16] 17] 18..20]

CALL

Enable Limiter/RSSI Data Switch (Demodulator or RSSI) Enable LPF Amplifier Enable Data Slicer Power Amplifier gain value in TX mode (see also MS bit) Enable VCO Enable PLL ( DDS System, RF divider, Phase Comparator and Chargepump) not used Slicer mode select bit modulation mode select RF divider ratio for PLL acceleration factor for the charge pump

#program_TRF6903

end_program_receive_FSK_hold RET

;**************************** program_TRF6903 ********************************************************** ; purpose: ; programs a word to A, B, C or D word register of the TRF6903 ; gets the settings from the calling routine in R6 and R7 ; suppresses the strobe pulse in receive_RF routine, to support shorter trainings sequence ; ;******************************************************************************************************* program_TRF6903 init_high_byte DINT BIC.B BIS.B MOV MOV MOV SWPB JMP

#strobe,&P1OUT #strobe,&P1DIR #02h,counter #08h,bits_r word_h,word_trf word_trf

; ; ; ; ; ; ;

reset Strobe port switch Strobe to output direction initialize the counter for high and low byte initialize bitcounter push the high byte to the programming buffer push the low byte to the high byte, only the data in the low byte is relevant

program_word

init_low_byte MOV MOV

#010h,bits_r word_l,word_trf

; initialize bitcounter ; push the low byte to the programming buffer

program_word RLC JNC

word_trf program_low

; push the msb of the programming buffer to carry

program_high BIS.B

#data,&P1OUT

; set data(P1.7)

program_clock BIS.B BIC.B

#clk,&P1OUT #clk,&P1OUT

; generate a pulse on the clock line

program_next_bit DEC JNZ DEC JNZ

bits_r program_word counter init_low_byte

; ; ; ;

decrement bit counter have already all bits been sent? decrement counter for low byte recognition low byte is to be programmed

generate_strobe BIC.B BIT JNZ BIS.B BIC.B BIC.B

#data,&P1OUT #08h,&data_rx_state end_program_TRF6903 #strobe,&P1OUT #strobe,&P1OUT #strobe,&P1DIR

; ; ; ; ; ;

reset data (P1.7) shall the strobe pulse be suppressed? yes suppress it set strobe(P1.5) clear strobe(P1.5) set strobe(P1.5) to input direction

5

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Master Degree Project Report, Aug 2007 end_program_TRF6903 EINT RET

; back to calling routine

program_low BIC.B JMP

#data,&P1OUT program_clock

; clear data(P1.7)

;*********************************** send_RF *********************************************************** ; purpose: sends the received 40 bytes package from RS232 via RF as NRZ code, without receiving an ; acknowledge ; features a shorter training sequence ; counter value comes from the calling routine ; ;******************************************************************************************************* send_RF

send_RF_init DINT

BIS.B BIC.B BIS.B BIS.B BIC.B CALL MOV MOV MOV.B MOV BIS.B

#stdb_rs232,&P1OUT #rxd,&P1IE #stdb_trf6903,&P2OUT #mode,&P2OUT #tx,&P1OUT #wait_lockdet #WDTPW+WDTHOLD,&WDTCTL 02FEh(counter),data_r #0C0h,&BCSCTL1 #WDTPW+WDTTMSEL+WDTCNTCL+07h,&WDTCTL #01h,&IE1

; ; ; ; ; ; ; ; ; ; ;

RS232 driver in standby mode disable P1.2 Interrupt TRF6903 active, STANDBY(P2.5) is high Mode 1 is set -> Send mode TXDATA(P1.4) is reset wait for the lockdetect signal Password, Watchdog Timer hold push data to the send register ACLK/1 Reset, Timer Mode, Password, every 26,04µsec enable Watchdog Timer interrupt

; ; ; ;

the entire length ca. 4ms, 154 pulses 1.56ms, 60 pulses 1ms, 38 pulses initialize the training sequence counter

EINT

send_RF_training_sequence ; MOV #03Ch,tr_counter MOV #026h,tr_counter ; MOV #09Ah,tr_counter send_RF_toggle BIS ;-----------------XOR.B DEC JNZ

#CPUOFF+GIE,SR ; CPU off Start of the training sequence ---------------------------------------------------#tx,&P1OUT ; toggle TXDATA(P1.4) tr_counter ; decrement counter for the training sequence send_RF_toggle ; length of the loop exactly 26,04µsec

send_RF_long_bit BIS #CPUOFF+GIE,SR ; CPU off ;------------------ Start of the start bit ------------------------------------------------------------BIS.B #tx,&P1OUT ; start of the long start-bit 78,12µsec ; (end by the transmission of the 1st data bit) BIS #CPUOFF+GIE,SR ; CPU off BIC #04h,&data_rx_state ; the RS232 buffer is ready for reception BIS #CPUOFF+GIE,SR ; CPU off BIS #CPUOFF+GIE,SR ; CPU off ;----------------- End of the start bit ---------------------------------------------------------------BIC.B #tx,&P1OUT ; reset TXDATA(P1.4) BIS #CPUOFF+GIE,SR ; CPU off send_RF_data MOV

#010h,bits_r

; init bitcounter, transmit first 16 bits

send_RF_bit_test RLC JC

data_r send_RF_high

; push the next data bit to carry

6

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send_RF_low BIS #CPUOFF+GIE,SR ; CPU off ;-------------------------------- Start of the Databit ------------------------------------------------BIC.B #tx,&P1OUT ; reset TXDATA(P1.4) send_RF_next_word? DEC JNZ DECD JZ JN MOV JMP

bits_r send_RF_bit_test counter send_RF_LED3_on send_RF_reset_ackn 02FEh(counter),data_r send_RF_data

; decrement bit counter ; ; ; ; ;

decrement word counter all data has been transmitted acknowledge has been transmitted get the next data word send next word

send_RF_high BIS #CPUOFF+GIE,SR ; CPU off ;-------------------------------- Start of the Databit ------------------------------------------------BIS.B #tx,&P1OUT ; set TXDATA(P1.4) JMP send_RF_next_word? send_RF_reset_ackn BIC

#020h,&data_rx_state

; reset acknoledge state

send_RF_LED3_on BIS BIS.B

#CPUOFF+GIE,SR #LED3,&P2OUT

; CPU off ; LED3 on

#WDTPW+WDTHOLD,&WDTCTL #stdb_rs232,&P1OUT #tx,&P1OUT #stdb_trf6903,&P2OUT #rxd,&P1IFG #rxd,&P1IE

; stop Watchdog Timer ; RS232 driver go active

end_send_RF MOV BIC.B BIC.B BIC.B ; BIC.B ; BIS.B

; clear STDBY(P2.5), TRF6903 standby mode ; reset the interrupt flag ; enable P1.2 Interrupt

RET ;********************************* receive_RF ********************************************************** ; main routine for code reception ; ; purpose: receives the 20 bytes data package and saves it to memory ; the reception is also supported by several interrupt routines ; checksum checking implemented (for Flash reprogramming) ; ;******************************************************************************************************* receive_RF BIT JNZ CALL

#02h,&data_rx_state end_receive_RF #program_send_FSK

MOV CLR CLR CLR CLR BIC.B BIS.B BIS.B CALL MOV.B MOV

#CCIE+CAP+CMNEG,&CCTL1 data_r wake_up_counter RSTAT res_old_r #mode,&P2OUT #01h,&IE1 #stdb_trf6903,&P2OUT #wait_lockdet #0C0h,&BCSCTL1 #TAIE+CLEAR+CONTUP+TASSEL_1,&TACTL

MOV

7

; ; ; ; ; ; ; ; ; ; ; ;

is the reception buffer full? yes the data has to be send to desktop first program the C-word for reception in learn mode interrupt enable, capture mode, neg. edge reset data_r reset wake_up_counter reset receive status register, RSTAT = 0, detecting the Trainingssequence receive FSK in learn mode enable Watchdog Timer interrupt TRF6903 active, STANDBY(P2.5) is high

; interrupt enable, clear Timer_A, ; continuous up mode, ACLK as clock source

#CCIE+CAP+CMANY,&CCTL2

BIS

#08h,&data_rx_state

BIS.B

#LED3,&P2OUT

; changed from BIS for suppressing strobe pulse at the end ; of the programming routine ; switch on the system mode LED

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Master Degree Project Report, Aug 2007 CALL BIC BIC.B

#program_receive_FSK_hold #08h,&data_rx_state #data,&P1OUT

; goto hold mode ; reset the the "suppressing mode" ; reset data 1919

loop_receive_training_seq ;--------------------- scanning the received signal for the training sequence -------------------------CMP #08h,wake_up_counter ; 8 equal pulses in succession JL loop_receive_training_seq ; no the result is less than 8 equal pulses ; in a row BIC #022h,&TACTL ; stop Timer_A and disable interrupt BIC #CCIE,&CCTL2 ; disable interrupt INCD RSTAT ; RSTAT = 4 start_bit_reception BIS.B #strobe,&P1OUT BIC.B #strobe,&P1OUT ;MOV #0106h,&TACTL ;BIS #20h,&TACTL MOV.B #0C0h,&BCSCTL1 MOV #TAIE+CLEAR+CONTUP+TASSEL_1,&TACTL ;MOV MOV

#TAIE+CLEAR+CONTUP+MCLK,&TACTL #CCIE+CAP+CMANY,&CCTL2

; waiting for the start_bit ; set strobe(P1.5) ; clear strobe(P1.5)

; ; ; ; ;

interrupt enable, clear Timer_A, continious up mode, MCLK as clock source interrupt enable, clear Timer_A, continuous up mode, MCLK as clock source interrupt enable, capture mode, both edges

loop_start_bit CMP #04h,RSTAT ; has the start bit been detected? JEQ loop_start_bit ; wait for the start bit JN receive_RF ; the received sequence is invalid BIC.B #rxd,&P1IE ; disable P1.2 interrupt ;----------------------------- start bit detected -----------------------------------------------------init_data_reception NOP NOP MOV.B #0C0h,&BCSCTL1 MOV #WDTPW+WDTTMSEL+WDTCNTCL+07h,&WDTCTL MOV #042h,counter init_rx_bit_counter CLR bits_r word_reception_loop BIS #CPUOFF+GIE,SR ; ; ; ; ; ; ; ; ;

NOP NOP NOP NOP NOP NOP NOP NOP XOR.B BIT.B

#LED3,&P2OUT #08h,&P1IN

; RSTAT = 6, Start Bit detected, Data Reception ; insert for the right timing

; Reset, Timer Mode, Password, every 26µs ; Initialize counter

; Reset bitcounter

; go to sleep! ; wake up from WDT (Timer Mode, every 26µs) ; insert for timing ; ; ; ;

; for test purpose ; is RXDATA high or low?

read_data RLC INC CMP JNE

data_r bits_r #010h,bits_r word_reception_loop

INV MOV DECD JNZ BIC.B BIS

data_r data_r,02FEh(counter) counter init_rx_bit_counter #LED3,&P2OUT #02h,&data_rx_state

BIS

#020h,&data_rx_state

; push carry into the data register ; receive 16 bits in row ; haven't received 8bits yet

store_data

8

; ; ; ; ; ; ; ;

the received data is inverted! store received data to RAM next storage register receive the next word system LED off for test purpose 2 stands for data received, has to be send to desktop via RS232 initialize the acknowledge state

St. Mary’s University, San Antonio

Master Degree Project Report, Aug 2007

end_receive_RF BIC BIC MOV ;CALL CALL BIC.B RET

#CCIE,&CCTL2 #022h,&TACTL #WDTPW+WDTHOLD,&WDTCTL #checksum_r #decode #stdb_trf6903,&P2OUT

; disable CCR2 interrupt ; stop Timer_A and disable interrupt ; stop Watchdog Timer ; built checksum of received data ; clear STDBY(P2.5), TRF6903 in standby mode

;************************************ rs232_send ******************************************************* ; purpose: the transmission of the received data from TRF6903 to the PC via RS232-Port ; ;******************************************************************************************************* rs232_send BIT

#02h,&data_rx_state

JZ BIC.B BIC.B MOV

end_rs232_send #cts,&P2OUT #stdb_rs232,&P1OUT #032Eh,wait_r

CALL MOV.B

#wait_x_cycles #0D0h,&BCSCTL1

MOV BIS.B MOV EINT rs232_send_init MOV.B MOV BIS CLRC RLC

; ; ; ; ; ; ; ; ; ;

is there any data in the reception buffer, which hasn't been sent to the desktop? no the reception buffer is empty reset CTS !!!! activate RS232 driver initialize wait register for ca. 1ms waiting loop wait for RS232 driver ready to transmit set the divider for ACLK to 2, high frequency oscillator

#020h,counter #01h,&IE1 #WDTPW+WDTTMSEL+WDTCNTCL+07h,&WDTCTL

; ; ; ;

Initialize counter enable Watchdog Timer interrupt Reset, Timer Mode, Password, every 52.08µs general Interrupt enable

0223h(counter),data_r

; ; ; ; ; ; ;

move the first received word into the output buffer send only 8bit in a row prepare stop bit set carry, prepare startbit prepare the output buffer for data transmission

#0Ah,bits_r #0100h,data_r data_r

rs232_send_loop RRC JNC

data_r rs232_send_low

; push next bit to carry for transmission

rs232_send_high BIS BIS.B DEC JNZ

#CPUOFF+GIE,SR #txd,&P1OUT bits_r rs232_send_loop

; CPU off ; set TXD ; decrement bitcounter

rs232_send_next_byte DEC counter JNZ rs232_send_init BIC #02h,&data_rx_state JMP

end_rs232_send_lp

rs232_send_low BIS BIC.B DEC JNZ JMP

#CPUOFF+GIE,SR #txd,&P1OUT bits_r rs232_send_loop rs232_send_next_byte

end_rs232_send_lp BIS BIS.B

#CPUOFF+GIE,SR #txd,&P1OUT

; ; ; ; ;

decrement byte counter get the next byte for transmission the buffer is ready to receive from TRF6903 the next data

; CPU off ; reset TXD ; decrement bitcounter

; generate the last change of the TXD ; CPU off ; TXD by default high, data toggles the TXD

end_rs232_send

9

St. Mary’s University, San Antonio

Master Degree Project Report, Aug 2007 DINT MOV BIS.B RET

#WDTPW+WDTHOLD,&WDTCTL #LED3,&P2OUT

; ; stop Watchdog Timer ; set System LED for test purpose

;************************************ checksum_s ******************************************************* ; used to built the checksum of the received data package from RS232, for secure data transmission ; (Flash reprogramming via RF) ; ;******************************************************************************************************* checksum_s MOV CLR checksum_s_loop ADD DECD JNZ MOV

#020h,counter chcksum_s

; initialize counter ; reset checksum

0200h(counter),chcksum_s counter checksum_s_loop chcksum_s,&0222h

; build checksum over all data to send

; save checksum

end_checksum_s RET ;************************************ checksum_r ******************************************************* ; used to built the checksum of the received data package from RF, for secure data transmission ; (Flash reprogramming via RF) ; ;******************************************************************************************************* checksum_r BIT JNZ MOV CLR checksum_r_loop ADD DECD JNZ MOV

#040h,&data_rx_state end_checksum_r #020h,counter chcksum_r

; ; ; ;

expecting acknowledge? no need to built the checksum initialize counter reset checksum

0222h(counter),chcksum_r counter checksum_r_loop chcksum_r,&0200h

; build checksum over all data to send

; save checksum

end_checksum_r RET ;************************************ check_chcksm_s *************************************************** ; purpose: compares the received checksum from the receiver, with the checksum of the received data ; from the PC via RS232 ; ;******************************************************************************************************* check_chcksm_s BIT JZ CMP JNE

#040h,&data_rx_state end_check_chcksm_s &0222h,&0244h end_check_chcksm_s

check_chcksm_s_ok MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV

#06F6Bh,&0242h #06F6Bh,&0240h #06F6Bh,&023Eh #06F6Bh,&023Ch #06F6Bh,&023Ah #06F6Bh,&0238h #06F6Bh,&0236h #06F6Bh,&0234h #06F6Bh,&0232h #06F6Bh,&0230h #06F6Bh,&022Eh #06F6Bh,&022Ch #06F6Bh,&022Ah

10

; ; ; ; ;

renamed check if waiting for an acknowledge

; ; ; ; ; ;

renamed move "ok" to the first word test test test test

compare the both checksums no the received data isn't valid

St. Mary’s University, San Antonio

Master Degree Project Report, Aug 2007 MOV MOV MOV

#06F6Bh,&0228h #06F6Bh,&0226h #06F6Bh,&0224h

BIS CALL BIC BIC BIC

#02h,&data_rx_state #rs232_send #040h,&data_rx_state #020h,&data_rx_state #02h,&data_rx_state

end_check_chcksm_s RET

; ; ; ; ;

set the data package received state send the "ok" to the PC reset the state "waiting for acknowledge" reset the state "acknowledge to send" reset the state "data_package_received"

; renamed

;********************************** check_chcksm_r ***************************************************** ; purpose: - Compares the received checksum, that was built by the sender of the received data ; package via RS232, with the checksum built on the receiver side of the received data ; package. ; - If the two checksums are equal, the received data package is send of via RS232, and the ; checksum is send as an acknowledge back to the sender. ; - IF the checksums aren't equal the package is not send via RS232 to the PC, and no ; acknowledge will be send to the sender. ;******************************************************************************************************* check_chcksm_r BIT #040h,&data_rx_state ; check if waiting for an acknowledge JNZ end_check_chcksm_r BIT #02h,&data_rx_state ; is there any data in the reception buffer, ; which hasn't been sent to the desktop? JZ end_check_chcksm_r ; no, no new data package CMP &0200h,&0244h ; are the checksums equal? JEQ end_check_chcksm_r ; yes the data is valid check_chcksm_r_inv BIC BIC

#02h,&data_rx_state #020h,&data_rx_state

; reset the data package received state ; reset the acknowledge to send state

end_check_chcksm_r RET ;************************************ wait loops ******************************************************* ; used for various timings, e.g. NRZ reception and transmission ; ;******************************************************************************************************* wait_x_cycles DEC JNZ RET

; waits 13 + x times 3 cycles wait_r wait_x_cycles

end_wait_x_cycles

;************************************ wait for lockdetect ********************************************** ; wait routine for the Lockdetect signal ; ;******************************************************************************************************* wait_lockdet BIT.B JZ

#lockdet,&P2IN wait_lockdet

; is the LOCKDET(P2.4) set? ; not yet

end_wait_lockdet RET

;************************************** Timer_A Interrupt routine ************************************** ; used by CC1_INT/RS232 reception and receive_RF ;******************************************************************************************************* TA_INT ADD RETI

11

&TAIV,PC

St. Mary’s University, San Antonio

Master Degree Project Report, Aug 2007 JMP

CC1_INT

JMP

CC2_INT

; ; ; ;

RS232 reception -> falling edge of the startbit RF reception -> every edge of the rx-signal

RETI RETI RETI

;****************************** Capture Compare 1 Register ********************************************* ; ; used for RS232-Reception ; ;******************************************************************************************************* CC1_INT BIC

#CCIE,&CCTL1

; disable CCR1 interrupt

BIT JNZ MOV MOV BIC BIC EINT

#04h,&data_rx_state end_CC1_INT #08h,bits_r #020h,counter #022h,&TACTL #CCIE,&CCTL2

; ; ; ; ; ;

rs232_init_WDT ; MOV.B MOV.B MOV

#clock_neu_3,&BCSCTL2

is the RS232 buffer full? yes, do not receive further data init bit counter init byte counter stop Timer_A and disable interrupt disable interrupt

; set the divider for ACLK to 2, ; high frequency oscillator

#0D0h,&BCSCTL1 #WDTPW+WDTTMSEL+WDTCNTCL+07h,&WDTCTL

; Reset, Timer Mode, Password, every 52.08µs

rs232_rec_data BIS BIC.B BIT.B

#CPUOFF+GIE,SR #LED3,&P2OUT #rxd,&P1IN

; CPU off ; LED3 off ; is the rx line high, or low?

rs232_push_buffer RRC DEC JNZ

data_r bits_r rs232_rec_data

; push carry to reception buffer ; decrement bit counter ; read the next bit

rs232_stop_bit BIS BIS MOV

#CPUOFF+GIE,SR #04h,&data_rx_state #WDTPW+WDTHOLD,&WDTCTL

; CPU off ; set the data reception state to received! ; stop watchdog timer

rs232_start_bit BIT.B

#rxd,&P1IN

; waits for the next start bit ; wait for the falling edge of the ; start bit for synchronization

JNZ MOV CALL MOV MOV SWPB MOV.B

rs232_start_bit #08h,wait_r #wait_x_cycles #WDTPW+WDTTMSEL+WDTCNTCL+07h,&WDTCTL #08h,bits_r data_r data_r,0201h(counter)

DEC JNZ

counter rs232_rec_data

; ; ; ; ; ; ;

MOV BIS

#WDTPW+WDTHOLD,&WDTCTL #040h,&data_rx_state

; stop watchdog timer ; set the status on waiting for acknowledge

; init wait parameter 10h for aclk init bit counter swap high and low byte of the receive buffer store the received data to RAM for RF-Transmission decrement the byte counter get the next byte

end_CC1_INT

;CALL #checksum_s CALL #encode MOV #042h,counter PUSH R7 MOV #400h,R7 ;MODIFICATION TO SEND 128 BYTES 1024 TIMES

12

; built checksum over received data ; init counter ; STORE THE VALUE OF R7

St. Mary’s University, San Antonio

Master Degree Project Report, Aug 2007

keep_sending CALL ;BIS MOV MOV CALL MOV CALL MOV CALL ; MOV ; CALL

#send_RF #04h,&data_rx_state #108h,counter

; send the received data out ; the RS232 buffer is ready for reception ; init counter

#0FFFFh,wait_r #wait_x_cycles #0FFFFh,wait_r #wait_x_cycles #0FFFFh,wait_r #wait_x_cycles #0FFFFh,wait_r #wait_x_cycles

DEC

R7

JNZ

keep_sending

POP

R7

BIC MOV

#CPUOFF+GIE,0(SP) #receive_RF,2(SP)

; ; ; ; ;

wake up from sleep mode do not return to the original address before the interrupt request, but start at the beginning of the receive_RF subroutine

RETI ;****************************** Capture Compare 2 Register ********************************************* ; ; used for RF-Reception ; ;******************************************************************************************************* CC2_INT ;MOV.B MOV.B MOV ; MOV MOV

RRFTAB

DW DW DW

#0F0h,&BCSCTL1 ;ACLK/8 #0C0h,&BCSCTL1 ;ACLK/1 #WDTPW+07h+WDTCNTCL+WDTTMSEL,&WDTCTL ; ACLK, ca.106ms, Timer Mode, Reset #WDTPW+WDT26MS+WDTCNTCL+WDTTMSEL,&WDTCTL ; ACLK, ca.106ms, Timer Mode, Reset RRFTAB(RSTAT),PC ; conditional jump depends on RSTAT ; RSTAT = 0, detecting the Trainingsequence ; RSTAT = 1, Trainingsquence detected, waiting ; for the Start Bit ; RSTAT = 2, Start Bit detected, Data Reception RSTAT00 RSTAT01 RSTAT10

MOV MOV SUB

&CCR2,res_new_r res_new_r,res_r res_old_r,res_r

MOV

res_new_r,res_old_r

RSTAT00

test_res_r00 SUB CMP JHS INCD INC BIC RETI no_valid_pulse CLR CLR ;BIC

13

#038h,res_r #010h,res_r no_valid_pulse RSTAT wake_up_counter #CPUOFF,0(SP)

RSTAT wake_up_counter #CPUOFF,0(SP)

; ; ; ; ;

save Reference Capture value copy Timer_A value subtract the current Timer_A value from the old one -> Bitwidth in cycles in res_r current value now -> old value later

; subtract the average value from the ; measured value ; is the detected signal 51-63 cycles long? ; first valid pulse detected ; count this valid pulse ; wake up!

; no the signal doesn't fit the wakeup sequence ; reset the wake_up_counter, received an ; invalid pulse ; wake up!

St. Mary’s University, San Antonio

Master Degree Project Report, Aug 2007 RETI RSTAT01 MOV MOV SUB

&CCR2,res_new_r res_new_r,res_r res_old_r,res_r

MOV

res_new_r,res_old_r

test_res_r01 SUB

#038h,res_r

CMP JHS INC RETI

#010h,res_r no_valid_pulse wake_up_counter

MOV MOV SUB

&CCR2,res_new_r res_new_r,res_r res_old_r,res_r

MOV

res_new_r,res_old_r

; ; ; ; ;

save Reference Capture value copy Timer_A value subtract the current Timer_A value from the old one -> Bitwidth in cycles in res_r current value now -> old value later

; subtract the average value from the ; measured value ; is the detected signal 51-63 cycles long? ; next valid pulse

RSTAT10 ; ; ; ; ;

save Reference Capture value copy Timer_A value subtract the current Timer_A value from the old one -> Bitwidth in cycles in res_r current value now -> old value later

test_res_r10 SUB

#0ACh,res_r

; subtract the average value from the ; measured value

CMP JGE

#028h,res_r invalid_bit

; is the detected signal x cycles long? ; restart detection, this is not a valid ; sequence

JHS INCD

no_start_bit RSTAT

BIC BIC

#CCIE,&CCTL2 #022h,&TACTL

no_start_bit INC

;

wake_up_counter

; ; ; ;

go to RSTATE 2, Data Reception, Start Bit detected disable CCR2 interrupt stop Timer_A and disable interrupt

count the pulses of the trainings sequence, to terninate at least after 8ms compare the value of the counter with the maximum value of the pulses of the trainings sequence

CMP

#02Fh,wake_up_counter

JGE BIC RETI

invalid_bit #CPUOFF,0(SP)

; ; ; ; ; ; ;

CMP

#08h,wake_up_counter

; to avoid errors during the first run

JEQ

invalid_bit_end

; skip clearing RSTAT

CLR

RSTAT

CLR

wake_up_counter

; restart the detection, this is not a valid ; sequence ; initialize the wake_up_counter

#CPUOFF,0(SP)

; wake up!

wake up!

2.5.2000

27.4.2000

invalid_bit 27.4.2000 27.4.2000

invalid_bit_end ; BIC RETI

27.4.2000

;***************************************************************************************** ;***************************************************************************************** ;***************************************************************************************** ;CONVOLUTIONAL ENCODING IMPLEMENTATION ;This routine implements convolutinal encoding before transmitting the data over the air ;***************************************************************************************** ;***************************************************************************************** ;***************************************************************************************** encode MOV SP, &9F6h ; preliminary housekeeping

14

St. Mary’s University, San Antonio

Master Degree Project Report, Aug 2007 MOV #9F6h, SP PUSH SR PUSH R4 PUSH R5 PUSH R6 PUSH R7 PUSH R8 PUSH R9 PUSH R10 PUSH R11 PUSH R12 PUSH R13 PUSH R14 PUSH R15

MOV #40h,R12 MOV #20h, R15 MOV #20h, R14 loop1 MOV 0200h(R15),R4 CMP R14, R15 JNE okay MOV R4,R5 RLA R5 MOV R4,R6 RLA R6 RLA R6 XOR R4,R6 XOR R6,R5 JMP okay_1

; prep R5 4 XOR ; prep R6 4 XOR

; makes CO LSB in R6 ; makes CO MSB in R5

okay MOV R4, R5 MOV 0200h(R14),R13 DECD R14 RLA R5 RLC R13 ADC R5 MOV R5, R6 RLA R6 RLC R13 ADC R6 XOR R4, R6 XOR R6, R5 okay_1 MOV #8h,R11 loop2 RRC RRC RRC RRC DEC JNZ loop2

R6 R7 R5 R7 R11

; makes 1st output word ; in R7 ; R5 holds 7 encode ; R6 holds 5 encode

R6 R8 R5 R8 R11

; makes 2nd output word ; in R8

MOV #8h, R11 loop3 RRC RRC RRC RRC DEC JNZ loop3

MOV R7,300h(R12)

15

; puts 1st OW in mem to send

St. Mary’s University, San Antonio

Master Degree Project Report, Aug 2007 ;MOV R7,342h(R12) DECD R12 MOV R8,300h(R12) ;MOV R8,342h(R12) DECD R12 DECD R15 JNZ loop1

; ; ;

MOV R4,R5 MOV R4,R6 RRA R4 RRA R4 RRA R5 CLRC RRC R4 CLRC RRC R4 CLRC RRC R5 XOR R4,R6 XOR R6,R5 CLR R7 RLC R5 RLC R7 RLC R6 RLC R7 RLC R5 RLC R7 RLC R6 RLC R7 MOV R7,&300h ;MOV R7,&342h POP POP POP POP POP POP POP POP POP POP POP POP POP POP

R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 SR SP

; puts 2nd OW in mem to send

; flush bits ; setting up to XOR for ; last 2 bits.

; clearing R7 to recv flush bits ; extracting 7 encoding ; extracting 5 encoding ; R5 holds 7 encode ; R6 holds 5 encode ; rotating left to put at front ; of R7

; wrapping up

CALL #decode RET ;*********************************** Viterbi Decoding ********************** ; ;**************************************************************************** decode MOV SP, &9F6h MOV #9F6h, SP PUSH SR PUSH R4 PUSH R5 PUSH R6 PUSH R7 PUSH R8 PUSH R9 PUSH R10 PUSH R11 PUSH R12 PUSH R13 PUSH R14 PUSH R15

16

; preliminary housekeeping

; end of housekeeping

St. Mary’s University, San Antonio

Master Degree Project Report, Aug 2007

CLR CLR CLR CLR

&9F8h &9FAh &9FCh &9FEh

MOV #0040h, R15

; 18x words in memory counter

MOV 0300h(R15), R10

; get encoded word to work on

MOV #0008h, R14

; 8x per word counter

wloop

inner1 MOV #0002h, R13 inner2

; begin calcuation of AE11(n+1) MOV &09FCh, R4 MOV &09FEh, R5 CLR R8

; get AE10(n) for calc AE11(n+1) ; get AE11(n) for calc AE11(n+1) ; empty R8, to rec C0(n) from R10 ; then move it into R6. ; ;

RRC RRC RRC RLC RLC RLC MOV MOV

R10 R6 R10 R8 R6 R8 R8, R6 R8, R9

XOR CLR RRC ADC RRC ADC MOV ADD

#0001h, R8 R12 R8 R12 R8 R12 R12, R8 R4, R8

; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;

XOR CLR RRC ADC RRC ADC MOV ADD

#0002h, R9 R12 R9 R12 R9 R12 R12, R9 R5, R9

CMP R8, R9 JL here0 RRC R8 RRC R7 RRC R8 RRC R7 RLA R11 RLA R11 ADD #0002h, R11 JMP here1

extracting C0(n) into * * * * * R8 collects AE 4 path R9 collects AE 4 path C0(n) in R8 and R9 counts digits diff w/ * * * * * * adds AE10(n) AE11(n+1) path1 in R8

R6

1 to AE11(n+1) 2 to AE11(n+1) PW into R8

; counts digits diff w/ PW into R9 ; * ; * ; * ; * ; * ; * ; adds AE10(n) ; AE11(n+1) path2 in R9 ; selecting min AE11(n+1) ; saving AE11(n+1) ; * ; * ; * ; capturing pred state for state 11 ; * ; *

here0 RRC R9 RRC R7

17

; saving AE11(n+1) ; *

St. Mary’s University, San Antonio

Master Degree Project Report, Aug 2007 RRC RRC RLA RLA ADD here1

R9 R7 R11 R11 #0003h, R11

; * ; * ; capturing pred state for state 11 ; * ; *

; begin calcuation of AE10(n+1) MOV &09F8h, R4 MOV &09FAh, R5

MOV R6, R8 MOV R8, R9

XOR CLR RRC ADC RRC ADC MOV ADD

#0003h, R8 R12 R8 R12 R8 R12 R12, R8 R4, R8

XOR CLR RRC ADC RRC ADC MOV ADD

#0000h, R9 R12 R9 R12 R9 R12 R12, R9 R5, R9

CMP R8, R9 JL here2 RRC R8 RRC R7 RRC R8 RRC R7 RLA R11 RLA R11 ADD #0000h, R11 JMP here3

; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;

get AE00(n) for calc AE10(n+1) get AE01(n) for calc AE10(n+1) R6 holds CO(n) put in R8 for calc put in R8 for calc R8 collects AE 4 path 1 to AE10(n+1) R9 collects AE 4 path 2 to AE10(n+1) counts digits diff w/ PW into R8 * * * * * * adds AE00(n) AE10(n+1) path1 in R8

; counts digits diff w/ PW into R9 ; * ; * ; * ; * ; * ; * ; adds AE01(n) ; AE10(n+1) path2 in R9 ; selecting min AE10(n+1) ; saving AE10(n+1) ; * ; * ; * ; capturing pred state for state 10 ; * ; *

here2 RRC RRC RRC RRC RLA RLA ADD here3

R9 R7 R9 R7 R11 R11 #0001h, R11

; begin calcuation of AE01(n+1) MOV &09FCh, R4 MOV &09FEh, R5

MOV R6, R8 MOV R8, R9

XOR #0002h, R8 CLR R12 RRC R8

18

; saving AE10(n+1) ; * ; * ; * ; capturing pred state for state 10 ; * ; *

; ; ; ; ; ; ; ; ; ; ; ;

get AE10(n) for calc AE10(n+1) get AE11(n) for calc AE10(n+1) R6 holds CO(n) put in R8 for calc put in R8 for calc R8 collects AE 4 path 1 to AE10(n+1) R9 collects AE 4 path 2 to AE10(n+1) counts digits diff w/ PW into R8 * *

St. Mary’s University, San Antonio

Master Degree Project Report, Aug 2007 ADC RRC ADC MOV ADD

R12 R8 R12 R12, R8 R4, R8

; * ; * ; * ; * ; adds AE10(n) ; AE01(n+1) path1 in R8

XOR CLR RRC ADC RRC ADC MOV ADD

#0001h, R9 R12 R9 R12 R9 R12 R12, R9 R5, R9

; counts digits diff w/ PW into R9 ; * ; * ; * ; * ; * ; * ; adds AE11(n) ; AE01(n+1) path2 in R9

CMP R8, R9 JL here4 RRC R8 RRC R7 RRC R8 RRC R7 RLA R11 RLA R11 ADD #0002h, R11 JMP here5

; selecting min AE01(n+1) ; saving AE01(n+1) ; * ; * ; * ; capturing pred state for state 01 ; * ; *

here4 RRC RRC RRC RRC RLA RLA ADD here5

R9 R7 R9 R7 R11 R11 #0003h, R11

; begin calcuation of AE00(n+1) MOV &09F8h, R4 MOV &09FAh, R5

MOV R6, R8 MOV R8, R9

XOR CLR RRC ADC RRC ADC MOV ADD

#0000h, R8 R12 R8 R12 R8 R12 R12, R8 R4, R8

XOR CLR RRC ADC RRC ADC MOV ADD

#0003h, R9 R12 R9 R12 R9 R12 R12, R9 R5, R9

CMP R8, R9 JL here6 RRC R8

19

; saving AE01(n+1) ; * ; * ; * ; capturing pred state for state 01 ; * ; *

; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;

get AE00(n) for calc AE10(n+1) get AE01(n) for calc AE10(n+1) R6 holds CO(n) put in R8 for calc put in R8 for calc R8 collects AE 4 path 1 to AE00(n+1) R9 collects AE 4 path 2 to AE00(n+1) counts digits diff w/ PW into R8 * * * * * * adds AE00(n) AE00(n+1) path1 in R8

; counts digits diff w/ PW into R9 ; * ; * ; * ; * ; * ; * ; adds AE01(n) ; AE00(n+1) path2 in R9 ; selecting min AE10(n+1) ; saving AE00(n+1)

St. Mary’s University, San Antonio

Master Degree Project Report, Aug 2007 RRC RRC RRC RLA RLA ADD JMP

R7 R8 R7 R11 R11 #0000h, R11 here7

; * ; * ; * ; capturing pred state for state 00 ; * ; *

RRC RRC RRC RRC RLA RLA ADD

R9 R7 R9 R7 R11 R11 #0001h, R11

; saving AE00(n+1) ; * ; * ; * ; capturing pred state for state 00 ; * ; *

CLR RLC RLC RLC RLC MOV

R4 R7 R4 R7 R4 R4, &9F8h

; saving AE00(n+1) ; * ; * ; * ; * ; *

CLR RLC RLC RLC RLC MOV

R4 R7 R4 R7 R4 R4, &9FAh

; saving AE01(n+1) ; * ; * ; * ; * ; *

CLR RLC RLC RLC RLC MOV

R4 R7 R4 R7 R4 R4, &9FCh

; saving AE10(n+1) ; * ; * ; * ; * ; *

CLR RLC RLC RLC RLC MOV

R4 R7 R4 R7 R4 R4, &9FEh

; saving AE11(n+1) ; * ; * ; * ; * ; *

here6

here7

DEC R13 JNZ inner2 PUSH R11 DECD R14 JNZ inner1 DECD R15 JNZ wloop

; counts 2 bytes per push

; counts 8 pushes per word ; counts 18 words

MOV &342h, R10 inner_1 MOV #0002h, R13 inner_2

20

; begin calcuation of AE11(n+1) MOV &09FCh, R4 MOV &09FEh, R5 CLR R8

; get AE10(n) for calc AE11(n+1) ; get AE11(n) for calc AE11(n+1) ; empty R8, to rec C0(n) from R10 ; then move it into R6. ; ;

RRC R10 RRC R6

; extracting C0(n) into R6 ; *

St. Mary’s University, San Antonio

Master Degree Project Report, Aug 2007 RRC RLC RLC RLC MOV MOV

R10 R8 R6 R8 R8, R6 R8, R9

XOR CLR RRC ADC RRC ADC MOV ADD

#0001h, R8 R12 R8 R12 R8 R12 R12, R8 R4, R8

XOR CLR RRC ADC RRC ADC MOV ADD

#0002h, R9 R12 R9 R12 R9 R12 R12, R9 R5, R9

CMP R8, R9 JL here_0 RRC R8 RRC R7 RRC R8 RRC R7 RLA R11 RLA R11 ADD #0002h, R11 JMP here_1

; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;

* * * * R8 collects AE 4 path 1 to AE11(n+1) R9 collects AE 4 path 2 to AE11(n+1) C0(n) in R8 and R9 counts digits diff w/ PW into R8 * * * * * * adds AE10(n) AE11(n+1) path1 in R8

; counts digits diff w/ PW into R9 ; * ; * ; * ; * ; * ; * ; adds AE10(n) ; AE11(n+1) path2 in R9 ; selecting min AE11(n+1) ; saving AE11(n+1) ; * ; * ; * ; capturing pred state for state 11 ; * ; *

here_0 RRC RRC RRC RRC RLA RLA ADD here_1

R9 R7 R9 R7 R11 R11 #0003h, R11

; begin calcuation of AE10(n+1) MOV &09F8h, R4 MOV &09FAh, R5

MOV R6, R8 MOV R8, R9

XOR CLR RRC ADC RRC ADC MOV ADD

#0003h, R8 R12 R8 R12 R8 R12 R12, R8 R4, R8

XOR #0000h, R9 CLR R12 RRC R9

21

; saving AE11(n+1) ; * ; * ; * ; capturing pred state for state 11 ; * ; *

; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;

get AE00(n) for calc AE10(n+1) get AE01(n) for calc AE10(n+1) R6 holds CO(n) put in R8 for calc put in R8 for calc R8 collects AE 4 path 1 to AE10(n+1) R9 collects AE 4 path 2 to AE10(n+1) counts digits diff w/ PW into R8 * * * * * * adds AE00(n) AE10(n+1) path1 in R8

; counts digits diff w/ PW into R9 ; * ; *

St. Mary’s University, San Antonio

Master Degree Project Report, Aug 2007 ADC RRC ADC MOV ADD

R12 R9 R12 R12, R9 R5, R9

CMP R8, R9 JL here_2 RRC R8 RRC R7 RRC R8 RRC R7 RLA R11 RLA R11 ADD #0000h, R11 JMP here_3

; * ; * ; * ; * ; adds AE01(n) ; AE10(n+1) path2 in R9 ; selecting min AE10(n+1) ; saving AE10(n+1) ; * ; * ; * ; capturing pred state for state 10 ; * ; *

here_2 RRC RRC RRC RRC RLA RLA ADD here_3

R9 R7 R9 R7 R11 R11 #0001h, R11

; saving AE10(n+1) ; * ; * ; * ; capturing pred state for state 10 ; * ; *

; begin calcuation of AE01(n+1) MOV &09FCh, R4 MOV &09FEh, R5

MOV R6, R8 MOV R8, R9

XOR CLR RRC ADC RRC ADC MOV ADD

#0002h, R8 R12 R8 R12 R8 R12 R12, R8 R4, R8

XOR CLR RRC ADC RRC ADC MOV ADD

#0001h, R9 R12 R9 R12 R9 R12 R12, R9 R5, R9

CMP R8, R9 JL here_4 RRC R8 RRC R7 RRC R8 RRC R7 RLA R11 RLA R11 ADD #0002h, R11 JMP here_5

; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;

get AE10(n) for calc AE10(n+1) get AE11(n) for calc AE10(n+1) R6 holds CO(n) put in R8 for calc put in R8 for calc R8 collects AE 4 path 1 to AE10(n+1) R9 collects AE 4 path 2 to AE10(n+1) counts digits diff w/ PW into R8 * * * * * * adds AE10(n) AE01(n+1) path1 in R8

; counts digits diff w/ PW into R9 ; * ; * ; * ; * ; * ; * ; adds AE11(n) ; AE01(n+1) path2 in R9 ; selecting min AE01(n+1) ; saving AE01(n+1) ; * ; * ; * ; capturing pred state for state 01 ; * ; *

here_4 RRC R9

22

; saving AE01(n+1)

St. Mary’s University, San Antonio

Master Degree Project Report, Aug 2007 RRC RRC RRC RLA RLA ADD here_5

R7 R9 R7 R11 R11 #0003h, R11

; * ; * ; * ; capturing pred state for state 01 ; * ; *

; begin calcuation of AE00(n+1) MOV &09F8h, R4 MOV &09FAh, R5

MOV R6, R8 MOV R8, R9

XOR CLR RRC ADC RRC ADC MOV ADD

#0000h, R8 R12 R8 R12 R8 R12 R12, R8 R4, R8

XOR CLR RRC ADC RRC ADC MOV ADD

#0003h, R9 R12 R9 R12 R9 R12 R12, R9 R5, R9

CMP R8, R9 JL here_6 RRC R8 RRC R7 RRC R8 RRC R7 RLA R11 RLA R11 ADD #0000h, R11 JMP here_7

; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;

get AE00(n) for calc AE10(n+1) get AE01(n) for calc AE10(n+1) R6 holds CO(n) put in R8 for calc put in R8 for calc R8 collects AE 4 path 1 to AE00(n+1) R9 collects AE 4 path 2 to AE00(n+1) counts digits diff w/ PW into R8 * * * * * * adds AE00(n) AE00(n+1) path1 in R8

; counts digits diff w/ PW into R9 ; * ; * ; * ; * ; * ; * ; adds AE01(n) ; AE00(n+1) path2 in R9 ; selecting min AE10(n+1) ; saving AE00(n+1) ; * ; * ; * ; capturing pred state for state 00 ; * ; *

here_6 RRC RRC RRC RRC RLA RLA ADD

R9 R7 R9 R7 R11 R11 #0001h, R11

; saving AE00(n+1) ; * ; * ; * ; capturing pred state for state 00 ; * ; *

CLR RLC RLC RLC RLC MOV

R4 R7 R4 R7 R4 R4, &9F8h

; saving AE00(n+1) ; * ; * ; * ; * ; *

CLR RLC RLC RLC RLC

R4 R7 R4 R7 R4

; saving AE01(n+1) ; * ; * ; * ; *

here_7

23

St. Mary’s University, San Antonio

Master Degree Project Report, Aug 2007 MOV R4, &9FAh

;

CLR RLC RLC RLC RLC MOV

R4 R7 R4 R7 R4 R4, &9FCh

; saving AE10(n+1) ; * ; * ; * ; * ; *

CLR RLC RLC RLC RLC MOV

R4 R7 R4 R7 R4 R4, &9FEh

; saving AE11(n+1) ; * ; * ; * ; * ; *

DEC R13 JNZ inner_2

*

; counts 2 bytes per push

PUSH R11 ; This section handles the predecessor state vectors ; FLUSH BITS MOV #0000h, R4 POP R5 MOV R5,R6 SWPB R6 AND #00FFh, R5 AND #00FFh, R6 CMP JNE AND MOV JMP

#0000h, R4 yippee #0003h, R5 R5, R7 woohoo

CMP JNE RRA RRA AND MOV JMP

#0001h, R4 yippee1 R5 R5 #0003h, R5 R5, R7 woohoo

CMP JNE RRA RRA RRA RRA AND MOV JMP

#0002h, R4 yippee2 R5 R5 R5 R5 #0003h, R5 R5, R7 woohoo

RRA RRA RRA RRA RRA RRA MOV

R5 R5 R5 R5 R5 R5 R5, R7

yippee

yippee1

yippee2

woohoo MOV R7, R4 CMP #0000h, R4 JNE yippee3

24

St. Mary’s University, San Antonio

Master Degree Project Report, Aug 2007 AND #0003h, R6 MOV R6, R7 JMP woohoo1 yippee3 CMP JNE RRA RRA AND MOV JMP

#0001h, R4 yippee4 R6 R6 #0003h, R6 R6, R7 woohoo1

CMP JNE RRA RRA RRA RRA AND MOV JMP

#0002h, R4 yippee5 R6 R6 R6 R6 #0003h, R6 R6, R7 woohoo1

RRA RRA RRA RRA RRA RRA MOV

R6 R6 R6 R6 R6 R6 R6, R7

yippee4

yippee5

woohoo1 MOV R7, R4 ; ENCODED BIT MOV #0020h, R15 MOV #0002h, R13

; Set to total number of bytes of original uncoded message

loopiest

loopy

MOV #0008h, R14 CLR R8 POP R5 MOV R5, R6 SWPB R6 AND #00FFh, R5 AND #00FFh, R6 CMP JNE AND MOV JMP

#0000h, R4 yippee_ #0003h, R5 R5, R7 woohoo_

CMP JNE RRA RRA AND MOV JMP

#0001h, R4 yippee1_ R5 R5 #0003h, R5 R5, R7 woohoo_

CMP JNE RRA RRA RRA RRA

#0002h, R4 yippee2_ R5 R5 R5 R5

yippee_

yippee1_

25

St. Mary’s University, San Antonio

Master Degree Project Report, Aug 2007 AND #0003h, R5 MOV R5, R7 JMP woohoo_ yippee2_ RRA RRA RRA RRA RRA RRA MOV

R5 R5 R5 R5 R5 R5 R5, R7

; collecting info bits woohoo_ CMP R7, R4 JNE not_equal CMP #0000h, R7 JNE equals_3 CLRC JMP done_is_done equals_3 SETC JMP done_is_done not_equal JL _less SETC JMP done_is_done _less CLRC done_is_done RLC R8 MOV R7, R4 ; Repeat R5 process on R6 CMP JNE AND MOV JMP

#0000h, R4 yippee3_ #0003h, R6 R6, R7 woohoo1_

CMP JNE RRA RRA AND MOV JMP

#0001h, R4 yippee4_ R6 R6 #0003h, R6 R6, R7 woohoo1_

CMP JNE RRA RRA RRA RRA AND MOV JMP

#0002h, R4 yippee5_ R6 R6 R6 R6 #0003h, R6 R6, R7 woohoo1_

yippee3_

yippee4_

yippee5_ RRA R6 RRA R6 RRA R6

26

St. Mary’s University, San Antonio

Master Degree Project Report, Aug 2007 RRA RRA RRA MOV

R6 R6 R6 R6, R7

woohoo1_ CMP R7, R4 JNE not_equal_ CMP #0000h, R7 JNE equals_3_ CLRC JMP done_is_done_ equals_3_ SETC JMP done_is_done_ not_equal_ JL _less_ SETC JMP done_is_done_ _less_ CLRC done_is_done_ RLC R8 MOV R7, R4 DEC R14 JNZ loopy MOV R8, 0222h(R13) INCD R13 DECD R15 JNZ loopiest

wrap_up POP POP POP POP POP POP POP POP POP POP POP POP POP POP

R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 SR SP

; wrapping up

RET ;**************************** WDT Interrupt Routine **************************************************** ; used for periodical wakeup during the listen phase ; ;******************************************************************************************************* WDT_INT BIC RETI

#CPUOFF,0(SP)

; reactivate CPU

;*********************************** Interrupt vector table ******************************************** ; ;*******************************************************************************************************

27

St. Mary’s University, San Antonio

Master Degree Project Report, Aug 2007 reset

28

RSEG DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW

INTVEC START START START START START TA_INT START START START START WDT_INT START START START START START

END

main

; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;

0FFE0h 0FFE2h 0FFF4h 0FFE6h 0FFE8h 0FFEAh 0FFECh 0FFEEh 0FFF0h 0FFF2h 0FFF4h 0FFF6h 0FFF8h 0FFFAh 0FFFCh 0FFFEh

not used not used P1_INT I/O Port P2 not used timer A1(CC1,CC2) not used not used not used CC0_INT Watchdog Timer in timer mode not used not used not used NMI, Oscillator fault Power On Reset, WDTIFG

St. Mary’s University, San Antonio