#experimental Results And Modeling Techniques For Substrate Noise In Mixed Signal Ics

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 28. NO. 4. APRIL 1993

420

Experimental Results and Modeling Techniques for Substrate Noise in Mixed-Signal Integrated Circuits David K. Su, Student Member, IEEE, Marc J. Loinaz, Student Member, IEEE, Shoichi Masui, Member, IEEE, and Bruce A. Wooley, Fellow, IEEE

Abstruct- Switching transients in digital MOS circuits can perturb analog circuits integrated on the same die by means of coupling through the substrate. This paper describes an experimental technique for observing the effects of such substrate noise. Various approaches to reducing substrate crosstalk (the use of physical separation of analog and digital circuits, guard rings, and a low-inductance substrate bias) are evaluated experimentally for a CMOS technology with a substrate comprised of an epitaxial layer grown on a heavily doped bulk wafer. Observations indicate that reducing the inductance in the substrate bias is more effective than either physical separation or guard rings in minimizing substrate crosstalk between analog and digital circuits fabricated on epitaxial substrates. To enhance understanding of the experimental results, two-dimensional device simulations are used to show how crosstalk propagates via the heavily doped bulk. Device simulations are also used to predict the nature of substrate crosstalk in CMOS technologies integrated in uniform, lightly doped bulk substrates, showing that in such cases the substrate noise is highly dependent on layout geometry. Finally, a method of including substrate effects in SPICE simulations for circuits fabricated on epitaxial, heavily doped substrates has been developed using a single-node substrate model.

I. INTRODUCTION

0

VER the past several years, the continued scaling of VLSI technologies has made possible the realization of complete monolithic systems that integrate complex, highspeed digital circuits together with high-performance analog circuits [ I ] , [2].In such mixed-signal systems, fast switching transients produced in the digital circuits can couple into sensitive analog components, thereby limiting the analog precision that can be achieved. As a result of the demands for higher clock rates and greater analog precision that accompany progress in the underlying semiconductor technology, switching noise is an increasingly serious concern in the design of mixed-signal integrated circuits [ 11, [3], [4]. Fast digital transients can produce switching noise in other circuits on the same die through both direct capacitive coupling between interconnect lines and interaction via the substrate. Manuscript received August 24, 1992; revised November 3 . 1992. This work was supported in part by the Semiconductor Rehearch Corporation under Contract 92-DJ-112 and by the Department of Energy under Contract DEAC03-76SF00S S . D. K. Su, M. J. Loinaz, and B. A. Wooley are with the Center lor Integrated Systems, Stanford University. Stanford, CA 94305. S. Masui was with the Center for Integrated Systems, Stanford University, Stanford, CA 94305. He is now with the Semiconductor Basic Technology Research Laboratory. Nippon Steel Corporation. 5- IO- 1 Fuchinobe. Sagamiham, Kanagawa 229, Japan. IEEE Log Number 9206702.

The focus of this work is on substrate noise-perturbations produced in analog circuits by switching transients in digital circuits on the same die, with the coupling occurring through the substrate. The present trend in CMOS technologies is to use a substrate comprised of a lightly doped epitaxial layer grown on a heavily doped bulk substrate in order to minimize latch-up phenomena [SI-[ 81. However, a significant fraction of current processes continue to utilize a uniform, lightly doped substrate [9]. As will be shown, the type of substrate has a crucial influence on substrate noise effects. Experimental observations, along with two-dimensional device simulations, have been used in this work to study both the mechanisms by which substrate excitations are produced and the manner in which these excitations affect analog circuits. A test chip was fabricated in a 2-pm CMOS technology with a substrate consisting of a lightly doped epitaxial layer grown on a heavily doped bulk wafer. This chip includes structures for evaluating the effectiveness of various methods of reducing substrate crosstalk, such as the use of guard rings and substrate tie-downs. Device simulations carried out using the program PISCES-IIB [ I O ] have been used to illustrate the current flow paths within the substrate. While the experimental observations presented in this work are germane to CMOS technologies with heavily doped substrates, the experimental approach is equally applicable to studying substrate noise in a technology with a lightly doped substrate. Device simulations have been used to predict substrate crosstalk effects for a CMOS process with a uniform, lightly doped substrate. In order to realize single-chip analog/digital systems that are efficient in terms of die area, packaging, and development time, designers of mixed-signal circuits must be able to assess substrate noise effects prior to chip fabrication. The experimental results presented in this paper provide the basis for a single-node substrate model for heavily doped substrates that can be readily employed in circuit simulations. The test chip and experimental setup are described in detail in Section 11 of this paper. The approach used for the device simulations is then outlined in Section 111. In Section IV, the results of both experimental observations and device simulations are presented for a technology with a heavily doped substrate. The use of physical separation between analog

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' I n this paper. substrates consi.;ting of a lightly doped epitaxial layer grown o n a heavily doped bulk substrate are referred to as hemi/! doped .~h.strute.s.Unifonn. lightly doped bulk wbstrates are referred to as / i g k t / ~ dO/JCl/.suhsrr.t~tct

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ring configurations: 1) a close pt guard ring, surrounding the current source at a distance of 6 jmi, with a dedicated bias pad; 2) a distant p+ guard ring, surrounding the current source at -5v 3 v -5v a distance of 22 pin; with a dedicated bias pad; 3) a close T T T Switching Noise I)+ guard ring (6-pn1 separation) connected to a large p+ ring Source Gate Drain surrounding the chip; and 4) a distant p+ guard ring (220.2 pF I /mi separation) connected to the large p+ ring surrounding Substrate Current Source the chip. All guard rings have 3 - / m diffusion widths. The Transistor Contact p+ diffusion ring surrounding the chip is 99-pni wide and FEpitaxial Layer (15 Q-cm) is connected to six bonding pads. Another large p+ substrate contact, with an area of 1.6 mm2, is located in the center P+ChannelStop Implant (1&cm$ of the die and connected to four bonding pads. The multiple bonding pads for these two large substrate contacts are used P+ Bulk (0.05 M m ) to study the effects of reducing the inductance in the substrate Fig. I . Basic experimental setup. bias. All p+ guard rings and substrate contact diffusions are strapped with a polysilicon/tungsten local interconnect layer and digital circuits, guard rings, and a low-inductance substrate and first-level metal (aluminum). Separate pairs of positive and negative digital power supply bias are evaluated as methods of reducing substrate crosstalk. pads are provided for the inverter block and the ring oscillator. Section V explores, via device simulations, the effectiveness of physical separation and guard-ring diffusions in reducing The current-source transistors are divided into three groups, substrate crosstalk in a CMOS technology with a lightly each group sharing bonding pads for their drain and source doped substrate. A circuit simulation model for heavily doped terminals. A separate bonding pad is provided for the gate to substrates is presented in Section VI, and circuit simulation each current source transistor. All testing is done with only results are compared to experimental observations. In Section one of the current sources tumed on at any given time. The 44-pad test chip is packaged in a 68-pin J-leaded chip VI1 a quantitative analysis of substrate crosstalk reduction in heavily doped substrates is outlined. The impact of the single- carrier and attached to the cavity using a nonconductive epoxy. node substrate model on clocking and packaging choices for The extra 24 package pins are wire bonded to the package cavity and biased at circuit board ground. The test circuit is circuits fabricated in such technologies is also discussed. operated between ground and -5 V so that a 50-R oscilloscope termination can be used as the load resistor for the current 11. EXPERIMENTAL SETUP source being observed. Since the positive supplies are biased A 2-mm x 2-mm CMOS test chip was fabricated in a at circuit board ground, the two positive digital supply pads 2-pin n-well technology [SI employing a 15-prn. IS-IL.cm, are connected to the package cavity through very short wires. I ~ p- The negative supply of the inverter block is bypassed using p-type epitaxial layer grown on a ~ O O - ~ I0.05-12.cm, type bulk substrate. Fig. 1 illustrates the basic test structure a 0.01-pF ceramic chip capacitor mounted in the package used. The effective thickness of the lightly doped epitaxial cavity, with wire bonds made directly to the chip capacitor. region, after processing is completed, is approximately 7 p r i The chip capacitor serves to reduce the coupling of supply due to the upward diffusion of boron from the p+ bulk. The bounce from the inverters' digital supply lead to other bond substrate is excited by CMOS inverters with their outputs wires and package pins. Special care is taken in the measurement setup to minimize coupled to the substrate by 0.2-pF capacitors. The inverters are driven by an on-chip ring oscillator. A single-transistor NMOS board-level noise. A two-sided etched copper board is used current source is used to measure the noise in the substrate. with all routing done on the top side and the bottom side Substrate voltage fluctuations affect the current flowing in the serving as a ground plane. Metal is left in the unused areas current source via threshold voltage variations (body effect) between the traces on the top side and connected to the ground and capacitive coupling between the substrate and the gate, plane via through-holes. The chip package is mounted in a drain, and source nodes. The drain of the current source short-lead PLCC surface mount socket. All supplies and bias is connected off-chip to an oscilloscope with a 50-12 input lines are bypassed to the ground plane at the feet of the socket termination, while its source and gate terminals are biased leads using 0.0 1-pF ceramic chip capacitors. The current with dedicated power supplies. The substrate is biased using source output leads are soldered directly to RG174 coaxial p+ substrate contact diffusions that are connected to bonding cables, each of which can be connected to a 50-12termination. pads. Three separate negative power supply traces are used on the The test chip includes ten NMOS current sources with gate board: one for the ring oscillator and inverter block, one for dimensions W / L = 200 jini/2 jim distributed throughout the the sources of the current-source transistors, and one for all die. Twelve CMOS inverters are switched at 5.3 MHz by a substrate biasing. Each power supply trace is bypassed to the 19-stage ring oscillator. Varying distances are used between ground plane using 0.1- and 1-j"F ceramic chip capacitors, and the current sources and the block of inverters to assess the a ~ ~ - Lelectrolytic LF capacitor. effects of physical separation. Seven of the current sources are A second test chip was fabricated on the same wafer as the shielded from substrate noise by one of four different guard- substrate noise test chip described above. This die includes Oscilloscope

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IEEE JOURNAL OF SOLID-STATE CIRCUITS. VOL. 28, NO. 4, APRIL 1993

422

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Representative device/circuit structure for PISCES-lIB simulations.

a variety of structures for measuring spreading resistances between substrate contacts at the chip surface, as well as the capacitance between inverter outputs and the substrate.

111. DEVICESIMULATION METHODOLOGY Although the experiments described in the preceding section enable the observation of substrate effects at the circuit level, they do not provide specific information on current flow pattems in the substrate. To understand the mechanisms of substrate crosstalk, a cross section similar to that shown in Fig. 1 was simulated at the device level. A mixed-mode device simulator that incorporates a circuit analysis capability, PISCES-IIB, was used to investigate substrate phenomena, including the effects of lumped inductances and capacitances representing package parasitics. The device structures and substrate composition were specified using doping profiles for the CMOS technology in which the experimental test chip was fabricated. Fig. 2 shows the device structure/circuit simulated. The device structure contains the following features: an equivalent drain diffusion representing the drain diffusion at the output of an inverter, an NMOS transistor current source with a gate length of 2 p m , and p+ substrate contacts biased at the negative supply. The substrate consists of a lightly doped (9 x 1014cm-3) p-type epitaxial layer grown on a heavily doped (1 x 10" cuip3) p-type bulk. The thickness of the structure is set at 200 pm (in the direction perpendicular to the page) in order to give a transistor W / L ratio of 200 p m / 2 im.Because the exact structure of the test chip is too complex for device simulations, the circuit/device structure of Fig. 2 is the result of simplifications meant to limit the number of finite-element grid points and reduce the required simulation times. Specifically, the bulk was modeled to a depth of only 90 im. and the effects of very large-area substrate contacts and bonding pad-to-substrate capacitances were not simulated. Because of these simulation expediencies, the experimental and device simulation results presented in the next two sections are not compared quantitatively. Instead, similarities in trends are used to validate and enhance understanding of the experimental results.

The components L 1 .L2. and L:, in Fig. 2 represent the inductances associated with bond wires and package traces. L4 models the inductance in series with a backside substrate contact, and the 5 0 4 resistor represents the oscilloscope input impedance. In the device simulations, a -5-V to 0-V excitation pulse with I-ns rise/fall times was applied at the equivalent drain diffusion, and the response at Voutwas observed. The dependence of the output response on the distance (1 between the current-source transistor and the equivalent drain diffusion was investigated, and various pf and n-well guard diffusions were evaluated with respect to their ability to isolate the current source from the substrate noise. These p+ and n-well guard diffusions were placed 6 and 17 pm away from the current source, respectively. In addition, when simulating the effects of a backside contact, L1 and the two p+ substrate contacts were removed and the value of La was varied to study the dependence of substrate crosstalk on the substrate bias impedance.

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RESULTSFOR HEAVILY DOPEDSUBSTRATES

A . Basic Mechanism Fig. 3(a) shows an example of a noise waveform observed at the output of a current source. The data for this figure were taken with the substrate biased using a single package pin connected to a 3-pin-wide p+ guard ring enclosing an area of 140 p i x 64 , m i . The response shown in Fig. 3(a) corresponds to one ring-oscillator cycle. High-to-low transitions at the outputs of the inverter block cause a negative-going voltage transient in the substrate. This transient increases the threshold voltage of the current-source transistor via the body effect, thereby decreasing the current flowing in the current source Similarly, the negative and inducing a positive spike in Vouout. spike in Fig. 3(a) is the result of low-to-high transitions at the outputs of the inverter block.2 Associated with the two main transients in Fig. 3(a) are initial glitches of the opposite polarity. These are caused by capacitive coupling between the chip substrate and the diffusions and interconnect that comprise the drain node of the current-source transistor. This coupling is dominated by the capacitance between the drain bonding pad and the substrate. Fig. 3(b) shows the output voltage from a device simulation. Because bonding pad capacitances are not included in the device simulations, the glitches preceding the two principal transients are reduced. The waveforms shown in Fig. 3 exhibit very little ringing. As will be discussed in Section VII, the amount of ringing is strongly dependent on the impedance of the substrate bias. For the purposes of this work, substrate noise is quantified in terms of its peak-to-peak voltage and its settling time to within 0.5 mV. The peak-to-peak voltage of the waveform of Fig. 3(a) is 10.7 mV and the settling time is 6.8 ns. All settling time data presented in this paper represent the average of the settling times of the positive and negative transients associated with a ring-oscillator cycle. 'Circuit h w l a t i o n ? such as those described in Section VI have been used to confirm the dependence of the noise waveforms on the body effect.

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B . EBect of Physical Separation Fig. 4 shows the peak-to-peak noise voltages measured at each current source as a function of distance between the current source and the inverter block with all 12 inverters active. Because of the large spatial distribution of the inverters within the inverter block, the data points of Fig. 4 are plotted both as the distance between the current source and the nearest inverter and as the average distance between the current source and the inverters. Fig. 4 shows that the peak-to-peak noise amplitude is independent of the distance between the current source and the noise sources. Increasing the separation from 40 to 850 p i does not reduce the measured noise. Moreover, physical separation has no observable effect on the noise settling time. The experimental results of Fig. 4 can be explained with device simulations. Fig. 5 presents the results of such a simulation 0.1 ns after the initiation of a I-ns high-to-low transition at the equivalent drain diffusion of Fig. 2. Current flow lines through the substrate are shown in this figure, with the region between adjacent lines representing 5% of the total substrate current. Fig. 5 indicates that most of the lateral current from the digital noise source to the substrate contacts flows in the heavily doped bulk. Because of the low resistivity and thickness of the bulk, the injected noise current flows almost directly down through the epitaxial layer into the bulk and then up through the epitaxial layer to the substrate contacts. These simulation results have been corroborated by measuring the resistance between two substrate contacts as a function of the distance between them. The measurements

C. Cur-rent-Sout-crGuard Ring5 As described in Section 11, four p+ guard-ring structures were evaluated on the test chip: a close guard ring (6-pm separation) with a dedicated bonding pad, a distant guard ring ( 2 2 - p i separation) with a dedicated bonding pad, a close

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IEEE JOURNAL OF SOLID-STATE CIRCUITS. VOL. 2X. NO. 4, APRIL 1993

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guard ring connected to a large substrate contact, and a distant guard ring connected to large substrate contact. The latter two cases are intended to emulate the situation in which a p+ guard ring is connected on-chip to all other substrate contacts, and biased using a single common bonding pad. The noise measured at the output of each guard-ring-shielded current source is compared to that measured in a nearby current source that is not protected by a guard ring. Results of noise measurements illustrating the effects of the various guard-ring structures are presented in Fig. 7. For the tests involving a dedicated guard-ring package pin, the substrate is biased using one of the package pins connected to the 99-pm-wide p+ ring surrounding the chip. As shown in Fig. 7, a p+ guard ring (biased with a dedicated package pin) placed close to the current source provides a reduction of approximately 20% in the substrate noise, while a similar but more distant ring has less of an effect. However, guard rings connected to large substrate contacts actually result in an increase in the observed noise. These experimental results can be explained with the aid of Fig. 8. If a guard ring is to reduce the switching noise in the current source, it must act to decouple the epitaxial layer in the immediate vicinity of the current source transistor from the noisy pi bulk. In Fig. 8, resistors R I .R2. and R;j represent the spreading resistance of the epitaxial layer. In Fig. 8(a)

the guard ring is biased with a dedicated package pin. This structure can reduce switching noise at node A in the epitaxial layer if resistor R I is made smaller than R2, which can be accomplished by placing the guard ring as close to the current source as possible. In Fig. 8(b) the guard ring is connected to a large substrate contact diffusion. Because of the large size of this diffusion, R3 is very small, thereby closely coupling node B to the noisy heavily doped bulk. Device simulation results for various guard diffusion structures are shown in Fig. 9. These results are consistent with the experimental observations in that they also indicate that, for heavily doped bulk substrates, a I)+ guard diffusion biased with a dedicated package pin will provide a modest reduction in substrate noise (about 30% in Fig. 9). Simulations also indicate that an n-well guard diffusion, which breaks the p+ channel stop implant, has almost no effect because most of the substrate current flows in the heavily doped bulk and not in the channel stop diffusion near the die surface. Device simulation results for a lightly doped substrate, also shown in Fig. 9, are discussed in Section V.

D . Inductance in the Siihstrute Bius Because the p+ bulk behaves electrically as a single node, attenuation of voltage fluctuations in the bulk through the use of a low-impedance connection to the negative supply voltage should reduce substrate crosstalk. Fig. 10 summarizes the measured peak-to-peak noise and noise settling time as functions of the number of package pins (10 nH per boundwire package pin) used to bias the two large p+ substrate contacts on the surface of the chip. Also included in this figure are the results obtained from circuit simulations, which are discussed in Section VI. The spreading resistance between each of the large substrate contacts and the heavily doped bulk is approximately 3 R. Increasing the number of package pins connected to the substrate contacts decreases the series

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SU et <,I : SUBSTRATE NOISE IN MIXED-SIGNAL INTEGRATED CIRCUITS

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inductance in the substrate bias, reducing oscillations in the single-node substrate. Fig. 1 1 summarizes the results of device simulations of the peak-to-peak noise and noise settling time as functions of the inductance in the substrate bias when the substrate is biased using a backside contact to the heavily doped bulk. These

results are consistent with those of Fig. IO. With zero series inductance, the backside contact virtually eliminates substrate noise by keeping the bulk at ground potential. However if the inductance is nonzero, substantial ringing is observed in the output noise. The effects of substrate bias impedance on switching noise are analyzed in Section VII.

V. DEVICESIMULATION RESULTS LIGHTLYDOPED SUBSTRATES

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Device simulations indicate that the nature of substrate crosstalk in lightly doped substrates differs significantly from that in heavily doped substrates. Specific differences are examined in this section. Results of simulations illustrating the dependence of the noise voltage on the physical separation between the equivalent drain diffusion and the NMOS transistor are included in Fig. 6 for lightly doped, as well as heavily doped, substrates. In the lightly doped case, the noise voltage decreases almost linearly with the separation distance. These results can be understood by comparing the current density lines for a lightly doped substrate shown in Fig. 12 with those for a heavily doped substrate presented in Fig. 5. In the lightly doped substrate. current flow is more uniform within the substrate because there is no low-resistance bulk. Therefore, the isolation between digital and analog circuits improves as the physical separation is increased. The effects of using a p' diffusion or n-well to shield the current source from substrate noise in a lightly doped

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lEEE JOURNAL OF SOLID-STATE CIRCUITS. VOL. 2X. NO. 4, APRIL 1993

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substrate are included in Fig. 9. The simulation results show that a p+ guard-ring diffusion can reduce the switching noise by almost an order of magnitude because a p+ guard-ring diffusion acts as a current sink that keeps the substrate in the immediate vicinity of the current source quiet. The current flow lines in Fig. 12 show that a significant amount of the substrate current flows near the die surface because of the p+ channel-stop implant. An n-well guard diffusion therefore acts to isolate the current source by interrupting the channel-stop implant and forcing substrate current to flow through the highresistance bulk. These device simulation results imply that in a technology employing a lightly doped substrate, sensitive analog circuits can be protected from substrate noise through the use of concentric n-well and p+ guard rings. Device simulations also show that low-inductance biasing increases the effectiveness of guard rings and substrate contacts. However, because substrate noise effects in a lightly doped substrate are highly layout-dependent, device simulations alone do not reveal additional general conclusions regarding the effects of substrate bias inductance.

VI. CIRCUIT MODELING FOR HEAVILY DOPEDSUBSTRATES Experimental and device simulation results indicate that when a switching noise source and a sensitive analog circuit are separated by more than four times the effective thickness of the epitaxial layer, substrate crosstalk occurs via the heavily doped bulk. Circuit simulations can be used to predict substrate effects in such cases if conventional schematics are augmented by modeling the heavily doped bulk as a single node [ I ] . Fig. 13 shows how the interactions of transistors and substrate contacts with the substrate node can be modeled. The transistors and their associated junction capacitances are represented by the appropriate SPICE models, while RPpll-Rep,~ represent spreading resistances through the epitaxial layer. To characterize spreading resistance through the epitaxial layer, p+ substrate contact diffusions of various sizes were fabricated on a separate test chip. An empirical formula that describes the epitaxial spreading resistance between a p+ substrate contact and the heavily doped bulk based on the surface geometry of the substrate contact has been derived. This formula corresponds to the parallel combination of two

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resistors, R.A.RE.A. and R P E R .The area component of the resistance, R.ARE-\. is based on uniform current flow through a rectangular block and is given by

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The parameters and T represent the resistivity and effective thickness of the lightly doped epitaxial layer, respectively, while A is the surface area of the substrate contact. The resistance due to current flow at the perimeter of the diffusion, RPER.is based on uniform conduction in a hemisphere [ 1 11

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where p is the resistivity of the epitaxial layer and P is the perimeter of the substrate contact. The resultant spreading resistance formula, based on the parallel combination of ( 1 ) and ( 2 ) , is

where the variables kl.k 2 , and h are empirical fitting parameters. Assuming T = 7pm. with k l = 0.96, k2 = 0.71. and 6 = 5 . 0 1 ~the ~ . results from (3) are within 15% of measured values. Fig. 14 shows a simplified schematic used to model the experimental setup described in Section 11. The p+ bulk is represented by a single node. Capacitor C.51 represents an n-well, while Cs2-Cs7 represent the capacitances between interconnect lines (including bonding pads) and the substrate. Drain and source junction capacitances are included in the transistor SPICE models. Switching noise is injected into the substrate by the CMOS inverter via Cs2 and the drains of 1111 and M 2 . Capacitor Cs8 models all capacitance between the bulk and ac ground. Resistors Rs1-Rs.l model spreading resistances through the epitaxial layer. Inductances L p l - L p ~ represent parasitic inductances of bond wires and package traces. The input impedance of the oscilloscope is modeled by a 5042 resistor in parallel with a 7-pF capacitor. Fig. 15 compares an experimentally observed noise waveform with the results of a circuit simulation. The top trace is the output waveform of a current source as seen on a digital oscilloscope and the bottom trace is the result of a

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SU er a / : SUBSTRATE NOISE IN MIXED-SIGNAL INTEGRATED CIRCUITS

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substrate model has been shown to give reasonable results with modest additions to conventional circuit schematics. Furthermore, the enhancements to conventional schematics can be made in a straightforward manner, making use of layout geometry, equation (3), and information about package parasitics. A layout extractor could be modified to include substrate effects, enabling designers to quantitatively assess substrate crosstalk in a given layout. For large circuits, including the entire chip in a SPICE simulation is often impractical. In such cases, the switching noise produced by a large logic block can be emulated using chains of inverters driven by an ideal clock [12]. The sizes of the inverters can be chosen to duplicate the transient current injected into the substrate by the logic block. Using these equivalent switching noise sources, simulations of sensitive analog circuits can include substrate effects associated with the entire chip. With the aid of a logic timing simulator, it should be possible to generate such equivalent switching noise sources from a layout.

VII. REDUCING SUBSTRATE CROSSTALK IN HEAVILYDOPEDSUBSTRATES

-

With the heavily doped bulk acting electrically as a single node, any switching transient that excites the bulk will affect the entire chip. For circuits fabricated on heavily doped Q c substrates, reducing substrate crosstalk is thus largely a matter 2 mVldiv of silencing the bulk node. In a p-type substrate, p+ guard rings can be used to decouple local regions of the epitaxial layer from the heavily doped 0 20 40 60 80 100 120 140 160 bulk. These structures may be placed close to sensitive analog Time (ns) circuits in an attempt to isolate them from the bulk node. Fig. 15. Observed and simulated noise wavcform7. However, both experimental and device simulation results have shown these techniques to be effective only when the SPICE simulation. The close agreement between simulation pt guard rings are placed very close to the sensitive analog and measurement is partially due to the use of experimentally circuits and are biased using dedicated package pins. A promising method of reducing excitation of the bulk measured values for the spreading resistances and package node is to modify the substrate bias impedance in order to parasitics in Fig. 14. The circuit simulation results were found tie the substrate more closely to ac ground. Analysis of the to be highly dependent on the values used for CSU.R s ~ . and L p j (55 pF, 3 fl. and 10 nH, respectively). C S ~ is simplified schematic in Fig. 16 provides insight into how bulk dominated by the capacitance between the bulk and the IC node perturbations caused by switching transients represented package cavity, through the nonconductive die attach epoxy. by V&NS can be reduced. Capacitor Cc in this schematic models diffusion and interconnect capacitances coupling the The package cavity was held at ac ground as described in switching noise sources (for example, logic gate outputs and Section 11. Depending on the chip layout, the contribution of noisy power supply lines) to the substrate. To first order, the n-well capacitance to Cs8 may be significant. Rss represents switching noise voltage at the bulk node, VBULK.is determined the spreading resistance from surface substrate contacts to by the voltage division between capacitor C c and the substrate the bulk node. L p j is determined by the number of bonding bias impedance. The substrate bias impedance is comprised of pads and package pins used to bias the substrate contacts at R,s. L s . and Cs. which correspond to R s ~L,p j , and Cs8 in the die surface. Circuit simulations using only Cs8:Rs3. and Fig. 14. Lpg (neglecting all other package parasitics and spreading The graph in Fig. 16 plots the magnitude of the frequency resistances in Fig. 14) yielded results for peak-to-peak noise response of the VBULK/VTR.ANS transfer function, which is and noise settling time within 50% of measured values. given by Fig. 10 shows good agreement between circuit simulations and experimental measurements for peak-to-peak noise voltages and noise settling times as a function of the number of package pins used to bias the substrate. Circuit simulations that include substrate crosstalk effects may therefore be feasible for chips fabricated on heavily doped substrates. A single-node (4) c

8

a

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IEEE J O U R N A L OF SOLID-STATE

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.

CIRCUITS. VOL.

2 8 . NO. 4, APRIL 1993

,

The settling behavior is governed by the damping factor <. For actual circuits, the rise and fall times of VTR.A.NS are nonzero. a A step response analysis that includes the effects of nonzero >’ 0.15 is presented in the Appendix. The transition times in VTR.A.N~ analysis shows that the noise amplitude decreases slowly as 3 >” L s is decreased, as was observed experimentally (see Section Cs = 55 PF,Cc 2.4pF) C IV). Equation ( I O ) should therefore be regarded as an upper .-c0 0.10 limit for the noise amplitude. C Equations (6)-( 10) provide insight into how the relative U, values of Rs. L s . Cs, and CC can be chosen to minimize the 1 0.05 C substrate noise amplitude and settling time. These equations show that the switching noise voltage may be overdamped (C > 1) as in Fig. 3 or underdamped (C < 1) as indicated 0.00 200 400 600 800 1WO by the oscillations in Fig. 15. Equations (6)-(IO), and the Frequency (MHz) results presented in the Appendix, suggest that the amplitude Fig. 16. Switching noise model for a heavily doped substrate. of substrate noise can be reduced by decreasing the value of C c with respect to Cs and by decreasing the value of Ls with respect to Rs. provided that the transition times of V T R A N ~ A resonance in this response occurs at frequency W O . where are much smaller than the damping time constant, (k-’. Unfortunately, the components in Fig. 16 cannot be adjusted arbitrarily. C c is determined primarily by the process technology, along with circuit performance and functionality considerations. Rs is govemed by the size and number of If the magnitude of the frequency response at W O is very large substrate contact diffusions, which are often dictated by latch(as shown in Fig. 16 for L s = 10 nH), care must be taken up considerations. Increasing the capacitance Cs by adding to ensure that all switching frequencies (e.g., clock rates) and on-chip decoupling capacitance. for example, may lower the their low-order harmonics do not coincide with the substrate noise amplitude, but it also has the undesirable effect of lowering the substrate resonance frequency. As seen in Section resonance frequency [ 11. IV, a practical means of minimizing substrate noise is to If VTR.A.NSin Fig. 16 is represented as a square wave with reduce the inductance Ls relative to Rs. If the value of a period large enough so that all substrate transients die out LS is reduced by lowering parasitic inductance of the IC between the rising and falling edges, upper bounds for the package, both the amplitude and settling time of substrate substrate noise amplitude and noise settling time can be found noise are reduced without compromising circuit performance. by considering the step response of the circuit in Fig. 16. When When a conventional package is used. Ls can be reduced by V & N ~ is a unit step, the substrate noise voltage response, connecting multiple bond wires to the substrate contact. An V B U L K ( ~is) % alternative approach is to use a custom package where the package cavity can be held at ac ground through a very lowinductance lead. The backside of the die can be electrically connected to the package cavity using a conductive epoxy. The backside substrate contact configuration could then have where the damping coefficient N is a very small L.7. However, because RS has also been greatly reduced, the noise settling times may be much longer. The Rs (Y = (7) resultant values of Rs. L s , C y . and CC must be considered 2LS in conjunction with the analysis developed in the Appendix to the frequency of the oscillations in the response, /I. is determine the effects of using a nonstandard package. 0.20,

U)

.

,

,

,

.

A

,

.

VTRANS

.

4

I\

L

;

~

~

1 =

l/Ls(Q

+ CC)

_ _R: _

(8)

4Li

and the damping factor ( is

+ Cc).

( = “JLS(CS

The maximum amplitude of the step response occurs at and is given by V B ~ r L K ( 1 l l a X )=

CC

cc + C‘S‘

~

(9) f =

(

0

VIII. CONCLUSION The experiments and simulations described in this paper provide insight into the nature of switching noise in mixedsignal integrated circuits. Propagation of switching noise should be visualized as a three-dimensional phenomenon, with the type of substrate playing a crucial role in crosstalk effects. An experimental framework for studying substrate noise in mixed-signal IC’s has been developed and used to observe substrate crosstalk effects in a technology with a substrate consisting of a lightly doped epitaxial layer grown on a heavily doped bulk. Experimental observations and device simulations

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SU et

U / .

SUBSTRATE NOISE IN MIXED-SIGNAL INTEGRATED CIRCUITS

429

indicate that switching noise that reaches the heavily doped and bulk spreads throughout the entire chip. If analog and digital l Rc\ 2 circuits are separated by four times the effective thickness of the epitaxial layer, crosstalk between digital circuit blocks and sensitive analog circuits occurs primarily by way of the heavily doped bulk, and further increases in the physical separation The quantities (Y and /j are specified in (7) and (8). Note that will not reduce substrate crosstalk. In an n-well process, ps guard rings can partially shield sensitive analog circuits from as the rise time becomes small, p7. goes to infinity and (1 1) noise in the bulk if the rings are placed very close to the analog reduces to (4). Plots of (13) show that decreasing LS will circuits and biased with dedicated package pins. Reducing the result in lower noise amplitude. as observed experimentally. inductance in the substrate bias was found to be the most ACKNOWLEDGMENT effective way of minimizing substrate noise. Device simulations of substrate crosstalk in lightly doped The authors wish to thank Dr. J. Shott and the staff of the substrates indicate that substrate noise is highly dependent Integrated Circuits Laboratory at Stanford University for the on layout geometry. For circuits fabricated on lightly doped fabrication of the test circuits and for providing the doping substrates, physical separation and guard rings appear to be profiles used in the device simulations. A special acknowledgeffective ways of shielding sensitive analog circuits from ment is extended to Technology Modeling Associates, Inc. for digital switching transients. providing the program PISCES-IIB. Thanks are also due to Dr. Although simple rules of thumb can be helpful, circuit B. Razavi, D. Wingard, and W. Wong for technical assistance simulations that can quantitatively predict substrate crosstalk and numerous helpful discussions. effects are needed for the design of mixed-signal integrated circuits. For technologies employing an epitaxial layer grown REFERENCES on a heavily doped bulk substrate, a single-node model of I1I T. J . Schmerbeck. R. A. Richetta. and L. D. Smith, “A 27 MHZ mixed the bulk substrate can be used to include substrate effects A/D magnetic recording channel DSP using partial response signalling in circuit simulations. Analysis of the single-node substrate with maximum likelihood detection.’’ in ISSCC D ~ RTech. . Puprra. 1991. 121 S. Takeuchi et d.“A 30-MHz mixed analog/digital signal processor.” model provides insight into how substrate noise amplitude and I E E E J . So/id-.Srate Circ.irits. vol. 2.5. pp. 1458-1463, Dec. 1990. settling time can be reduced. 131 B. P. Brandt and B. A. Woolev, “A SO-MHz multibit sigma-delta mod-

APPENDIX When considering the step response of the circuit of Fig. 16, the effects of a nonzero step rise time must be included in order to accurately reflect the effects of changing L s . A nonzero rise time for the VTR.~NS signal can be modeled using a single-pole response. This can be accomplished by adding a single-pole filter to (4), yielding

(41 151

161

171

181 101

I IO] I 12)

ulator for 12-b 2-MHi A/D conver\ion.” IEEE .I. Solrd-Srute Crrcrrits. vol. 26. pp. 17461756. Dec. 1991. L. D. Smith er al., “A CMOS-based analog standard cell product family.” / € E € J . Solid-State Ciwrtitr, vol. 24, pp. 370-379. Apr. 1989. Y. Taur et U / . , “A self-aligned I-ltm-channel CMOS technology with retrograde n-well and thin epitaxy.” IEEE Trans. Elec,tron De1.ic.r.y. vol. ED-32. pp. 203-209, Feb. 19x5. R. A. Chapman et U / . . ”An O.8mm CMOS technology for high performance logic applications.” in lEDM Tech. Dix.. 1987. G. J . Hu and R. H. Bruce, “A CMOS structure with high latchup holding voltage,” IEEE Elrc,trori De1,ic.e Lefr.. vol. EDL-5, pp. 21 1-214, June 1084. “The Stanford BICMOS project annual report,” Center for Integrated Syst.. Stanford Univ., Stanford, CA. pp, 7-24, 1990. H. Ooka r r U / , “High \peed CMOS technology for ASIC application,” in IEDM Tech. Dr,q., 1986. TMA PISCES-IIR. A T~~o-Diniet7sronuI Dr1,ic.eAnulysrs Progran7 Wrth A M . Technology Modeling Associate.; Inc., July 1991. C o m m 4th ed. New York: Springer Verlag, 1967. L. D. Smith, “Circuit model for \ub\trate noise on mixed analogflogic products,” presented at the IEEE SSCTC Workshop on Noise in Mixed Analog/Digital IC‘s, Sept. 199 I .

where

2.2

pr = -. rise tiriic

The step response of the above transfer function is

where

David K. Su (S’X I ) was born in Kuching, Malaysia, on September 16. 1961. He received the B.S. and M.E. degrees in electrical engineering from the University of Tennessee, Knoxville, in 1982 and 1985, respectively. He is currently a Ph.D. candidate in electrical engineering at Stanford University, Stanford, CA. From 19x5 to 1989 he worked as an IC design engineer at Hewlett-Packard Company in Corvallis, OR, and Singapore where he designed full-custom and semi-custom application-specific integrated circuits. During the summer of 1991, he worked on the design of an oversampling DIA converter at IBM Corporation. Research Triangle Park, NC. His current research interests include the design of analog, mixed-signal, and data conversion integrated circuits. Mr. Su i \ ;1 member of Tau Beta Pi. Eta Kappa Nu. and Phi Eta Sigma.

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IEEE JOURNAL OF SOLID-STATE CIRCUITS. VOL. 28, NO. 4, APRIL 1993

430

Marc J. Loinaz (S’89) was bom in Manila. the Philippines, on August 20, 1967. He received the B.S. degree in electrical engineering from the University of Pennsylvania, Philadelphia. in 1988 and the M.S. degree from Stanford University. Stanford. CA, in 1990. He is currently a Ph.D. candidate in electrical engineering at Stanford University. During the summer of 1990, he worked at National Semiconductor Corporation, Santa Clara, CA, where he was involved in the design of an oversamuline A D converter. Over the summer of 1991, he was employed at the Digital Equipment Corporation Western Research Laboptory, Palo Alto, CA, where he participated in the design of an ECL RISC microprocessor. His research interests are in the area of highperformance analog and digital circuit design, with emphasis on mixed-signal integrated circuits in CMOS and BiCMOS technologies. Mr. Loinaz was a recipient of the E. Stuart Eichert Memorial Prize from the University of Pennsylvania in 1987, and is a member of Tau Beta Pi and Eta Kappa Nu.

. -

P

Shoichi Masui (M’89) was bom in Nagoya, Japan on February 14, 1960. He received the B.S. and M.S. degrees in electrical engineering from Nagoya University, Nagoya, Japan. in 1982 and 1984, respectively. In 1984 he joined Nippon Steel Corporation, Kanagawa, Japan. where he is currently a Senior Researcher in the Electronics Research Laboratories. From 1990 to 1992 he was a Visiting Scholar at Stanford University. His research interests include the design and testing of mixed-signal integrated circuits

Bruce A. Wooley (S’64-M’7GSM’76-F382) was bom in Milwaukee, WI, on October 14. 1943. He received the B.S., M.S. and Ph.D. degrees in electrical engineering from the University of Califomia, Berkeley. in 1966, 1968, and 1970. respectively. From 1970 to 1984 he was a member of the research staff at Bell Laboratories in Holmdel, NJ. In 1980 he was a Visiting Lecturer at the University of Califomia, Berkeley. In 1984 he assumed his present position as Professor of Electrical Engineering at Stanford University. Stanford, CA. His research is in the field of integrated circuit design and technology where his interests have included monolithic broad-band amplifier design, circuit architectures for high-speed arithmetic, analog-to-digital conversion, digital filtering, highspeed memory design, high-performance packaging and test systems, and high-speed instrumentation interfaces. Prof. Wooley was the Editor of the IEEE J O U R N A L O F SOLID-STATE CIRCUITS from 1986 to 1989. He was the Program Chairman of the 1990 Symposium on VLSI Circuits and the Co-chairman of the 1991 Symposium on VLSI Circuits. He was the Chairman of the 1981 lntemational Solid-state Circuits Conference, and he is a former Chairman of the IEEE Solid-State Circuits and Technology Committee. He has also served on the IEEE Solid-state Circuits Council and the IEEE Circuits and Systems Society Ad Cam. In 1986 he was a member of the NSF-sponsored JTECH Panel on Telecommunications Technology in Japan. He is a member of Sigma Xi, Tau Beta Pi, and Eta Kappa Nu. In 1966 he wa\ awarded the University Medal by the University of Califomia, Berkeley, and he was the IEEE Fortescue Fellow for 19661967.

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