Exp 2.docx

Exp 2 4X1 mux Dataflow

Mux4X1 using operators(dataflow) Source code module mux4X1_operator(d,s,y); input [3:0]d; input [1:0]s; output y; assign y= (~s[1]&~s[0]&d[0])|(~s[1]&s[0]&d[1])|(s[1]&~s[0]&d[2])|(s[1]&s[0]&d[3]); endmodule

TEST BENCH module mux4X1_operator_tb(); reg [3:0]d; reg [1:0]s; wire y; mux4X1_operator a1(d,s,y); initial begin s=2'b00; d=$random; #10 s=2'b01; d=$random; #10 s=2'b10;d=$random; #10 s=2'b11;d=$random; #10 $finish; end

endmodule

Using ternary operators Source Code: module mux4X1_ternary(d,s,y); input [3:0]d; input [1:0]s; output y; assign y=s[1]?(s[0]?d[3]:d[2]):(s[0]?d[1]:d[0]); endmodule

Test Bench Code:

module mux4X1_ternary_tb(); reg [3:0]d; reg [1:0]s; wire y;

mux4X1_ternary a1(d,s,y); initial begin s=2'b00;d=$random;

#10 s=2'b01;d=$random; #10 s=2'b10;d=$random; #10 s=2'b11;d=$random; #10 $finish; end endmodule

waveform:

Structural

MUX4X1 using structural Source code module mux4X1_struct(d,s,y); input [3:0]d; input [1:0]s; output y; wire [1:6]w; not n1(w[1],s[1]),n2(w[2],s[0]);

and a1(w[3],w[1],w[2],d[0]),a2(w[4],w[1],s[0],d[1]),a3(w[5],s[1],w[2],d[2]),a4(w[6],s[1],s[0],d[3]); or o1(y,w[3],w[4],w[5],w[6]); endmodule

test bench module mux4X1_struct_tb(); reg [3:0]d; reg [1:0]s; wire y; mux4X1_struct a1(d,s,y); initial begin s=2'b00; d=$random; #10 s=2'b01; d=$random; #10 s=2'b10;d=$random; #10 s=2'b11;d=$random; #10 $finish; end endmodule waveform

Mux4X1 using if Source code module mux4X1_if(d,s,y); input [3:0]d; input [1:0]s;

output reg y; always @(s,d) begin if(s==2'b00)y=d[0];else if(s==2'b01)y=d[1];else if(s==2'b10)y=d[2];else if(s==2'b11)y=d[3];else y=1'bx; end endmodule test bench module mux4X1_if_tb(); reg [3:0]d; reg [1:0]s; wire y; mux4X1_if a1(d,s,y); initial begin s=2'b00; d=$random; #10 s=2'b01; d=$random; #10 s=2'b10;d=$random; #10 s=2'b11;d=$random; #10 $finish; end endmodule

waveform

Udp Source code primitive mux4X1_udp(y,d0,d1,d2,d3,s1,s0); input d0,d1,d2,d3,s0,s1; output y; table //d0 d1 d2 d3 s1 s0 : y 0 ? ? ? 0 0 : 0; 1 ? ? ? 0 0 : 1; ? 0 ? ? 0 1 : 0; ? 1 ? ? 0 1 : 1; ? ? 0 ? 1 0 : 0; ? ? 1 ? 1 0 : 1; ? ? ? 0 1 1 : 0; ? ? ? 1 1 1 : 1; ? ? ? ? X ? : X; 0 ? ? ? ? X : X; endtable endprimitive Testbench module mux4X1_udp_tb(); reg d0,d1,d2,d3,s0,s1; wire y; mux4X1_udp m1(y,d0,d1,d2,d3,s1,s0); initial begin

s1=$random; s0=$random; d0=$random; #10 s1=$random; s0=$random; d1=$random; #10 s1=$random; s0=$random; d2=$random; #10 s1=$random; s0=$random; d3=$random; #10 $finish; end endmodule Waveform

Switch level 4X1 2X1 2X1 mux Source code module mux2X1_gtl(a,b,s,y); input a,b,s; output y; wire sbar; cmos c1(y,a,sbar,s), c2(y,b,s,sbar); nor n1(sbar,s,s); endmodule test bench module mux2X1_gtl_tb(); reg a,b,s; wire y; mux2X1_gtl a1(a,b,s,y); initial

begin s=1'b0; a=$random; b=$random; #10 s=1'b1;a=$random; b=$random; #10 $finish; end endmodule testbench waveform

Mux4X1 module mux4X1_gtl(d,s,y); input [3:0]d; input [1:0]s; output y; wire w1,w2; mux2X1_gtl a1(d[0],d[1],s[1],w1),a2(d[2],d[3],s[1],w2), a3(w1,w2,s[0],y); endmodule

test bench module mux4X1_gtl_tb(); reg [3:0]d; reg [1:0]s; wire y; mux4X1_gtl m1(d,s,y); initial begin s=2'b00;d=$random; #10 s=2'b01;d=$random; #10 s=2'b10;d=$random;

#10 s=2'b11;d=$random; #10 $finish; end endmodule

testbench waveform