Dsp Lab Manual (1)

INTRODUCTION DSP Algorithm Design Flow An FPGA provides the user with a two-dimensional array of configurable resources that can implement a wide range of arithmetic and logic functions. These resources include dedicated DSP blocks, multipliers, dual port memories, lookup tables (LUTs), registers, tri-state buffers, multiplexers, and digital clock managers. In addition, Xilinx FPGAs contain sophisticated I/O mechanisms that can handle a wide range of bandwidth and voltage requirements. FPGAs are high performance data processing devices. FPGA DSP performance is derived from the ability they provide to construct highly parallel architectures for processing data. In contrast with a microprocessor or DSP processor, where performance is tied to the clock rate at which the processor can run, FPGA performance is tied to the amount of parallelism that can be brought to bear in the algorithms making up a signal processing system. A combination of increasingly high system clock rates (current system frequencies of 100-200 MHz are common today) and a highly distributed memory architecture gives the system designer an ability to exploit parallelism in DSP (and other) applications that operate on data streams. For example, the raw memory bandwidth of a large FPGA running at a clock rate of 150 MHz can be hundreds of terabytes per second. There are many DSP applications (e.g., digital up/down converters) that can be implemented only in custom integrated circuits (ICs) or in an FPGA; a von Neumann processor lacks both the compute capability and the memory bandwidth required. Advantages of using an FPGA include significantly lower non-recurring engineering costs than those associated with a custom IC (FPGAs are commercial off-the-shelf devices), shorter time to market, and the configurability of an FPGA, which allows a design to be modified, even after deployment in an end application.

• Design using System Generator: Ð Ð Ð Ð Ð Ð Ð

Ð Ð Ð

System Generator for DSP is a software tool for modelling and designing FPGA-based signal processing systems in Simulink. System Generator extends Simulink to enable hardware design, providing high level abstractions that can be automatically compiled into an FPGA. The tool presents a high level abstract view of a DSP system; it will map the system to a faithful hardware implementation. What is most significant is that System Generator provides these services without substantially compromising either the quality of the abstract view or the performance of the hardware implementation Simulink provides a powerful high level modelling environment for DSP systems, and consequently is widely used for algorithm development and verification. Simulink provides a graphical environment for creating and modelling dynamical systems. System Generator consists of a Simulink library called the Xilinx Blockset, and software to translate a Simulink model into a hardware realization of the model. System Generator maps system parameters defined in Simulink (e.g. as mask variables in Xilinx Blockset blocks), into entities and architectures, ports, signals, and attributes in a hardware realization System Generator automatically produces command files for FPGA synthesis, HDL simulation, and implementation tools, so that the user can work entirely in graphical environments in going from system specification to hardware realization. When a System Generator project is created, the software produces VHDL design or cores from the Xilinx CORE Generator. In addition, many other project files are automatically created. The implementation is made efficient through the instantiation of intellectual property (IP) blocks that provide a range of functionality from arithmetic operations to complex DSP functions.

MATLAB is a tool which is best suited for DSP algorithm development. Xilinx ISE tool is used for implementation of systems in FPGA. But there is a gap between these two tools. This gap can be filled by Xilinx System Generator Tool. In below block diagram we shows design flow of two different platforms.

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• Algorithm Verification and Implementation Design Flow System Design Domain

•

FPGA Design Domain

Algorithm design

Manual design entry in HDL

System verification (floating point)

Hardware simulation

GAP

Conversion to fixed point

Synthesis, place and route

Optimization and re-verification

Timing verification

MATLAB and Simulink

Foundation/Alliance

• Linking the System and FPGA Design Domains

System Design Domain

FPGA Design Domain

Algorithm design

Automatic generation of HDL

System verification (floating point) Conversion to fixed point

Xilinx System Generator & LogiCOREs

Hardware simulation Synthesis, place and route

Optimization and re-verification

Timing verification

MATLAB and Simulink

Foundation/Alliance

Our system designer flow confronts signal processing, control, and project management challenges in the process of developing DSP solutions. The System Generator for DSP design flow encompasses the entire design process.

• System Modeling and Design You can use familiar tools such as Simulink to develop your DSP system models. System Generator for DSP includes a Xilinx Blockset comprised of basic level building blocks such as FFTs and advanced DSP algorithms such as digital down converters. When combined with Simulink, System Generator enables you to build sophisticated DSP systems. By using it with Xilinx Platform Studio, you

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can also create microprocessor based control circuits. You can also bring in your own HDL modules via, or write MATLAB code for combinational control logic or state machines.

• Algorithm Development MATLAB is an excellent language for creating complex algorithms such as matrix operations and linear algebra. With the Xilinx AccelDSP Synthesis tool, you can automatically translate these algorithms into RTL and export them into a larger Simulink/System Generator system.

• Hardware Generation and Simulation You can use the System Generator tool to automatically generate highly efficient VHDL or Verilog code. To synthesize the VHDL/Verilog you have a choice of tools including Xilinx Synthesis Technology (XST), Synplify Pro from Synplicity or FPGA Advantage from Mentor Graphics. HDL modules can also be incorporated into a Simulink/System Generator design via a black box and cosimulated using ModelSim. You can also create a VHDL testbench and data vectors with System Generator for DSP. These vectors represent the inputs and expected outputs seen in the Simulink simulation, and allow you to easily see any discrepancies between Simulink and VHDL results. FPGA Advantage can be used to conduct simulations of DSP systems prior to implementation. ModelSim is required for HDL cosimulation.

• Debug and Verification Using high bandwidth hardware in the loop, you can accelerate simulations and verify your designs using FPGA hardware. If ChipScope™ Pro probes are introduced in the system modeling and design phase, they are automatically inserted into the design during hardware generation. These probes facilitate debugging by allowing internal nodes to be observed. Xilinx System Generator for DSP manages the entire design flow from a single environment Following files are created by Xilinx System Generator • • • • • • • •

• •

.vhd - the top level VHDL file for your project. There are additional VHDL files included when your design has more hierarchy. core - files associated with the generated multiplier core, such as the behavioral simulation models and EDIF file. corework - subdirectory containing the CORE Generator log file. .xcf - generated constraints file when XST synthesis is chosen in the System Generator block. Buses in this file are denoted with angle brackets. .ncf - generated constraints file when Synplify or Leonardo Spectrum is chosen as the synthesis tool. Buses are denoted with parentheses. .npl - project file for opening the design in Xilinx ISE 6.2i Project Navigator, using your chosen synthesis compiler and ModelSim simulator. testbench.vhd - the top level VHDL testbench file, associated with the top level VHDL source file in the project .dat - stimulus files for inputs to testbenches, or predicted outputs of testbenches. The .dat files are generated by Simulink simulation and saved for running in Xilinx testbenches to verify design behavior. In this example, refers to the names of the Xilinx gateway blocks, which collect and save the data. VhdlFiles - a list of VHDL files, and their dependency order, needed for synthesis projects. System Generator's Perl scripts read from this file when creating project files. Globals - a file containing the characteristics of the design needed by downstream software tools in order to synthesize and implement.

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• • • • • •

Synplify_fir_filtert.prj - a project file for running this design in Synplify (synthesis tools from Synplicity) if you have chosen it as your synthesis tool in the System Generator block. XST_fir_filtert.prj - a project file for running this design in XST if you have chosen it as your synthesis tool in the System Generator block. Spectrum_fir_filtert.tcl - a project file for running this design in Leonardo Spectrum (synthesis tools from Mentor Graphics). Pn_behavioral.do, pn_posttranslate.do, pn_postmap.do, Pn_postpar.do - compilation and simulation do files for running this design through simulation at different stages. These 4 files are associated with ModelSim simulation through the Xilinx ISE 6.2i Project Navigator. Vcom.do, vsim.do - default behavioral simulation files for use with ModelSim. Sysgen.log - log file. xlRunScripts.log - logfileshowing status of post-processing scripts run by System Generator.

• Implementation of a core generated by MATLAB in Xilinx ISE tool.

•

Simulation : Verifying the design specifications after design entry is functional simulation. It Saves the time consumed for physical prototyping

•

Synthesis : Is the process of creating a representation of a system at a lower level of design abstraction from a higher level representation Synthesis tools provides a means to convert schematic or HDL in real-world hardware. The output of synthesis is a netlist.

•

For locking physical pins with the designed entity user constraint file(UCF) has to specify by the user. Implementation : Is the process of placing the design into the specified target technology. Implementation tool reads the standard netlist & fits it into the target device. Following steps are performed by the implementation tool Ð Mapping:Tool partitions the design into the logic blocks available on the device. Good partitioning results in better performance. Ð Placing : After the logic is partitioned, implementation software searches for the best location to place the logic block among all of the possibilities. Primary goal is to reduce the amount of routing recourses required.

•

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Ð •

Routing : Logical nets are assigned to the physical wire segments in the device that interconnect logic cells.

Programming: Ð After the design is Implemented, software creates the bitstream ( binary programming ). Ð The programmable device is configured for the function by downloading the programming file into target. Ð After the device is programmed, you are ready to test the actual system, with real life inputs and outputs.

• Understanding the Number System Basis of implementing a DSP system are • “A-PRIORY KNOWLEDGE”, meaning a prior knowledge of the available hardware and the signals that, will be applied to the input and are expected at the output. • It is all about “Assigning Meaning to Numbers”, meaning Ð The input signals have to be converted properly to the number system being implemented in hardware Ð The numbers available at the system output have to be understood and then converted to analog domain. System Generator “System Generator for DSP” ( SysGen) is an EDA tool offered by Xilinx. It acts as a bridge between a design environment which is Matlab (simulink) and the hardware implementation environment, which is a Xilinx FPGA. System generator when loaded with Matlab, adds a Xilinx Blockset in the Simulink Library Browser. This blockset consists of synthesizable blocks for various applications in Communication and DSP. The “System Generator” block, allows automatic generation of VHDL code. This code can be synthesized and implemented in the target device using Xilinx ISE tool. In this document we the detailed steps to implement a Simple Filter in hardware, using the Matlab (simulink ) and System Generator for DSP Tools. The Filter will be implemented using DSP development board from Mechatronics Test Equipment. HARDWARE DESCRIPTION The following is the configuration of the DSP development board. • It has a built-in Signal Generator generates, which generates a Sine wave of amplitude 10V peak to peak. • ADC on board has the following specifications Ð Resolution - 12 bits. Ð Input range - ±10V. Ð Output Format - ADC output can be in straight Binary or 2’s complement format. • DAC on-board has the following specifications Ð Resolution 12 bits Ð Output Range - ±10V. Ð Output Format – Straight Binary. • Crystal oscillator on board has a freq of 4 MHz.

• Design Example for FIR Filter STEPS TO BE FOLLOWED TO DESIGN FIR FILTER IN SIMULINK Blocks required: Where to find FIR Xilinx - DSP Blockset Gateway-In, Gateway-out Xilinx – Basic Elements Signal Generator Simulink – Sources Scope Simulink – Sinks System Generator Xilinx – Basic Elements

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Inputs to System Generator Block: • Device Family = Spartan-III (check FPGA device in your DSP PROTOBOARD) • Target Directory = User defined • Check in “Create Test bench” option • Click on “Generate”

• STEPS TO IMPLEMENT THE FILTER IN DSP-PROTOBOARD Ð Ð Ð

Ð Ð Ð

Change the device type to XC3S400-4PQ208. Add source files : lowpass.vhd, adc_7891.vhd. Change the name of the component in “lowpass.vhd” according to the entity name in the VHDL file generated by system generator (project name). Assign the generic number n in “lowpass.vhd” the value equal to the Gateway_out signal’s bus-width. Add “UCF” file at the “implement design” step. Configure FPGA.

• ADC-DAC Controller in VHDL

--Description: Combines the ADC-DAC Controller module and User Generated module. --Required component : DSP PROTOBOARD --VHDL code for ADC (AD7891) and DAC (AD 7541) interfacing library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity adc_dac_test is generic (n : natural := 21); Port ( clk : in std_logic; -- Local clock reset : in std_logic; -- Local reset signal ----------------------------- For ADC1(7891)--------adc_clk : out std_logic; --sampling frequency to ADC cs_ad7891 : out std_logic; --chip select convst_ad7891 : out std_logic; --conversion start wr_ad7891 : out std_logic; --write rd_ad7891 : out std_logic; --read eoc_ad7891 : in std_logic; --end of conversion mode_ad7891 : out std_logic; --mode=1 for parallel db_7891 : inout std_logic_vector(11 downto 0);--ADC bidirectional input/output ---------------------------------For DAC----------------bit_trun : in std_logic_vector( 7 downto 0); dac_sel : in std_logic_vector(1 downto 0); --- DAC selection. IL0 and IL1 are used ch_adc : in std_logic_vector( 1 downto 0); --- Input channel selection for ADC --- IL6 and IL7 are used for Ch_adc --- 00 for ch1,01 for ch2,10 for ch3,11 for ch4 dac_out : out std_logic_vector(11 downto 0); ---Output to DAC en : out std_logic_vector( 3 downto 0) ---DAC latch enable ); end adc_dac_test; architecture Behavioral of adc_dac_test is type state_1 is (reset_1, write_cwr, start_conv, read_data); signal ps_1, ns_1 : state_1; signal dac_out_s, : std_logic_vector(11 downto 0);

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signal dacout : std_logic_vector(n downto 0); signal div_adc : std_logic_vector(15 downto 0 ); ---This should be changed as per input on board clock signal decade : std_logic_vector( 3 downto 0 ); signal sampling_clk, wr_s, clk_s, rd_s, convst_ad7891_s : std_logic; signal db_7891_s : std_logic_vector( 11 downto 0 ); component lowpass -- Change the name of the component in “lowpass.vhd” according to the entity port ( clk : in std_logic; --Name in the VHDL file generated by system generator (project name). gateway_in : in std_logic_vector(11 downto 0); gateway_out : out std_logic_vector(21 downto 0)); end component; begin -----------------------------Clk Divider-------------------------Decade counter is used because on board clock is 20 MHz. It can be 40 MHz --or 4 MHz.In case of 20/40 MHz we have to use decade counter to get 2/4 MHz. --In case of 4 MHz bypass decade counter. This arrangement is made so as to --design filter or any other application irrespective of input clk at --particular clock frequency. Otherwise every time we will have to change --frequency of our design. We cannot have similar frequency by direct --division of input clock 20/40/4 MHz. For example 4 divided --by 5 FF to have 62.5KHz.if we want this frequency from 20/40 MHz clock --we get 78.125. process(clk, reset) begin if(reset = '1') then decade <= (others => '0'); elsif(clk'event and clk = '1') then if decade="1001" then decade<=(others=>'0'); else decade <= decade + 1; end if; end if; end process; clk_s<='1' when decade="1001" else '0'; process(clk_s, reset) begin if(reset = '1') then div_adc <= (others => '0'); elsif(clk_s'event and clk_s = '1') then div_adc <= div_adc + 1; end if; end process; sampling_clk <=div_adc(2) ; ---Input clock is very fast so divided clock is used as sampling clock to FSM. ---FSM will divide sampling clock ---by four so sampling clock for ADC is 62.5KHz. adc_clk <= sampling_clk; --- Used just for checking, mapped to output LED OL0. ------------------------------------------------------------------------process(reset, sampling_clk) begin if(reset = '1' ) then ps_1 <= reset_1; elsif (sampling_clk'event and sampling_clk = '1') then

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ps_1 <= ns_1; end if; end process; ------------------------------------------------------------------------process(ps_1) begin case ps_1 is when reset_1 => ns_1 <= write_cwr; when write_cwr => ns_1 <= start_conv; when start_conv => ns_1 <= read_data; when read_data => ns_1 <= reset_1; end case; end process; cs_ad7891 <= '0' when (ps_1 = read_data or ps_1 = write_cwr) else '1'; wr_s <='0' when (ps_1 = write_cwr) else ‘1'; wr_ad7891 <= wr_s; rd_s <= '0'when (ps_1 = read_data) else '1'; rd_ad7891 <= rd_s; mode_ad7891 <= '1'; -- set parallel mode of ADC --- Write channel number db_7891(5 downto 0) <= '0' & ch_adc & "000" when wr_s = '0' else (others => 'Z'); -----------------------------convst-----------------------process(reset, sampling_clk) begin if(reset = '1') then convst_ad7891_s <= '0'; elsif(sampling_clk'event and sampling_clk = '1') then convst_ad7891_s <= wr_s; end if; end process; convst_ad7891 <= convst_ad7891_s; --------------------------read adc-------------------------process(reset, clk,rd_s) begin if(reset = '1') then db_7891_s <= (others => '0'); elsif(sampling_clk'event and sampling_clk = '0') then if(rd_s = '0') then db_7891_s <= db_7891; end if; end if; end process; ------------------ write ADC Data to DAC ------------------------dac_out_s <= dacout(n downto n-11) when bit_trun(0)='1' else dacout(n-1 downto n-12) when bit_trun(1)='1' else dacout(n-2 downto n-13) when bit_trun(2)='1' else dacout(n-3 downto n-14) when bit_trun(3)='1' else dacout(n-4 downto n-15) when bit_trun(4)='1' else dacout(n-5 downto n-16) when bit_trun(5)='1' else dacout(n-6 downto n-17) when bit_trun(6)='1' else dacout(n-7 downto n-12) when bit_trun(7)='1' else dacout(n-8 downto n-12) ; dac_out<= (dac_out_s(11)&( not dac_out_s( 10 downto 0))) +'1' when dac_out_s(11)='0' else dac_out_s(11)&( not dac_out_s( 10 downto 0));

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----------------------DAC selection logic-------------------------process(dac_sel) begin case dac_sel is when "00" => en<="1000" ; when "01" => en<="0100"; when "10"=> en <="0010"; when "11"=> en <="0001"; when others=> null; end case; end process; Inst_untitled: lowpass port map( clk =>div_adc(4) , ---Filter is operating at 62.5KHz so we have divided the clock gate way_in =>db_7891_s , gateway_out =>dacout ); end Behavioral;

• ADC-DAC Controller in Verilog

// Description: Combines the ADC-DAC Controller module and User Generated module. //Required component : DSP PROTOBOARD //Verilog code for ADC (AD7891) and DAC (AD 7541) interfacing module lowpassvlog (smpclk,dac_out,en,cs_ad7891,convst_ad7891,wr_ad7891,rd_ad7891,mode_ad7891,reset,cl k,dac_sel, bit_trunc,ch_adc,db_7891); output smpclk,cs_ad7891,convst_ad7891,wr_ad7891,rd_ad7891,mode_ad7891; output [11:0] dac_out; output [3:0] en; input clk, reset; input [7:0] bit_trunc; input [1:0] dac_sel; input [1:0] ch_adc; inout [11:0] db_7891; reg [3:0] en; reg cs_ad7891,convst_ad7891,wr_ad7891,rd_ad7891,mode_ad7891,convst_ad7891_s; wire sampling_clk,wr_s,rd_s; wire [11:0] dac_out_s; wire [21:0] dacout; `define reset_1 2'd0 `define write_cwr 2'd1 `define start_conv 2'd2 `define read_data 2'd3 reg [1:0] ps_1; reg [1:0] ns_1; reg [3:0] div; wire [5:0] conc; wire [11:0] conc1; reg [15:0] div_adc; reg [11:0] adcin,db_7891_s; wire clk_s; always @ (posedge reset or posedge clk) begin if (reset) div = 4'b0000; else if (div == 4'b1001) div = 4'b0000; else div = div + 4'b0001; end

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assign clk_s = (div == 4'b1001) ? 1'b1:1'b0; always @ (posedge reset or posedge clk_s) begin if (reset) div_adc = 16'd0; else div_adc = div_adc + 1; end assign sampling_clk = div_adc[2]; assign smpclk = sampling_clk; always @ (posedge reset or posedge sampling_clk) begin if (reset) ps_1 = `reset_1; else ps_1 = ns_1; end always @ (ps_1) begin case (ps_1) `reset_1 : ns_1 = `write_cwr; `write_cwr : begin cs_ad7891 = 1'b0; ns_1 = `start_conv; end `start_conv : ns_1 = `read_data; `read_data : begin cs_ad7891 = 1'b0; ns_1 = `reset_1; end endcase end assign conc = {1'b0,ch_adc,3'b0}; assign db_7891[5:0] = (wr_s == 1'b0) ? conc : 6'bZZZZZZ; always @ (posedge reset or posedge sampling_clk) begin if (reset) convst_ad7891_s = 1'b0; else convst_ad7891_s = wr_s; end always @ (convst_ad7891_s) convst_ad7891 = convst_ad7891_s; always @ (posedge reset or negedge sampling_clk) begin if (reset) db_7891_s = 12'b0; else if (!rd_s) db_7891_s = db_7891; end always @ (db_7891_s) adcin = db_7891_s;

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always mode_ad7891 = 1'b1; assign wr_s = (ps_1 == `write_cwr) ? 1'b0 :1'b1; assign rd_s = (ps_1 == `read_data) ? 1'b0 : 1'b1; always @ (rd_s or wr_s) begin wr_ad7891 = wr_s; rd_ad7891 = rd_s; end always @ (dac_sel) begin case (dac_sel) 2'b00 : en 2'b01 : en 2'b10 : en 2'b11 : en default : en endcase end

= = = = =

4'b1000; 4'b0100; 4'b0010; 4'b0001; 4'b0000;

lowpass u1(.clk(div_adc[4]),.gateway_in(adcin),.gateway_out(dacout)); assign dac_out_s = bit_trunc[0] ? dacout[21:10] : (bit_trunc[1] ? dacout[20:9] : (bit_trunc[2] ? dacout[19:8] : (bit_trunc[3] ? dacout[18:7] : (bit_trunc[4] ? dacout[17:6] : (bit_trunc[5] ? dacout[16:5] : (bit_trunc[6] ? dacout[15:4] : (bit_trunc[7] ? dacout[14:3]: dacout[13:2]))))))); assign conc1 = {dac_out_s[11],~dac_out_s[10:0]}; assign dac_out = (dac_out_s[11] == 0) ? (conc1 + 1) : conc1; endmodule

Note : The component name represented in BOLD (e.g. lowpass) letters is required to be changed according to the entity name in the module generated by user. The value of n must be equal to the bus-width of the Gateway_out signal in the module generated by user. SPARTAN III PQ208 – connections details of on board peripherals Clock & Reset Signal

Spartan III Pin Number

GCLK1

76

GCLK2

77

RESET

78 RS232 Serial Port

RXD1

205

TXD1

204

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STEPPER MOTOR INTERFACE A1_COIL

43

A2_COIL

42

B1_COIL

37

B2_COIL

39 RELAY

RELAY0

40

ADC

DAC

Signal

FPGA pin Number

Signal

FPGA pin Number

"DB0"

45

"DAC0"

81

"DB1"

46

"DAC1"

79

"DB2"

57

"DAC2"

100

"DB3"

58

"DAC3"

97

"DB4"

61

"DAC4"

93

"DB5"

62

"DAC5"

90

"DB6"

63

"DAC6"

94

"DB7"

64

"DAC7"

95

"DB8"

65

"DAC8"

96

"DB9"

67

"DAC9"

102

"DB10"

68

"DAC10"

101

"DB11"

71

"DAC11"

80

"MODE"

72

"EN1"

87

"EOC"

44

"EN2"

85

"\CONVST\ "

48

"EN3"

86

"\CS\"

50

"EN4"

74

"\RD\"

51

"\WR\"

52

USB INTERFACE FPGA pin Signal Number USB_D0

106

Signal

FPGA pin Number

USB_D6

114

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USB_D1

107

USB_D7

115

USB_D2

108

RD#

116

USB_D3

109

WR#

117

USB_D4

111

TXE#

119

USB_D5

113

"RXF#

120

INPUT SWITCHES FPGA pin Signal Number

Connecter name and pin number

"IL0"

141

J1-7

"IL1"

140

J1-8

"IL2"

139

J1-11

"IL3"

138

J1-12

"IL4"

137

J1-13

"IL5"

135

J1-14

"IL6"

133

J1-15

"IL7"

132

J1-16

"IL8"

131

J1-17

"IL9"

130

J1-18

"IL10"

128

J1-21

"IL11"

126

J1-22

"IL12"

125

J1-23

"IL13"

124

J1-24

"IL14"

123

J1-25

"IL15"

122

J1-26

KEY SWITCHES FPGA pin Signal Number

Jumper name and pin number

"KEY0"

143

J1-6

"KEY1"

144

J1-5

"KEY2"

146

J1-4

"KEY3"

147

J1-3

FPGA pin Number

Jumper name and pin number

OUTPUT LEDs Signal

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“OL0”

161

J2-34

“OL1”

172

J2-24

“OL2”

156

J2-43

“OL3”

171

J2-33

“OL4”

155

J2-36

“OL5”

169

J2-26

“OL6”

154

J2-35

“OL7”

168

J2-25

“OL8”

152

J2-38

“OL9”

167

J2-28

“OL10”

150

J2-37

“OL11”

166

J2-27

“OL12”

149

J1-1

“OL13”

165

J2-32

“OL14”

148

J1-2

“OL15”

162

J2-31

7 SEGMENT DISPLAY FPGA pin Signal Number

Jumper name and pin number

"SEGA"

189

J2-8

"SEGB"

190

J2-7

"SEGC"

187

J2-12

"SEGD"

185

J2-11

"SEGE"

184

J2-14

"SEGF"

183

J2-13

"SEGG"

182

J2-16

"SEGDP"

181

J2-15

SEG. DISPLAY SELECTION "CSDIS0"

175

J2-18

"CSDIS1"

176

J2-17

"CSDIS2"

178

J2-22

"CSDIS3"

180

J2-21

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LCD DISPLAY Signal

FPGA pin Number

Jumper name and pin number

"DL0"

33

J3-32

"DL1"

31

J3-31

"DL2"

29

J3-28

"DL3"

28

J3-27

"DL4"

27

J3-26

"DL5"

26

J3-25

"DL6"

24

J3-24

"DL7"

22

J3-23

"E"

36

J3-33

"R/W"

35

J3-34

"RS"

34

J3-35

USER I/O’S Type

FPGA PIN Number

Connector pin

I/O1_QS

21

J3-22

I/O2_QS

20

J3-21

I/O3_QS

19

J3-18

I/O4_QS

18

J3-17

I/O5_QS

16

J3-16

I/O6_QS

15

J3-15

I/O7_QS

13

J3-14

I/O8_QS

12

J3-13

I/O9_QS

11

J3-12

I/O10_QS

10

J3-11

I/O11_QS

9

J3-8

I/O12_QS

7

J3-7

I/O13_QS

5

J3-6

I/O14_QS

4

J3-5

I/O15_QS

3

J3-4

I/O16_QS

2

J3-3

I/O17_QS

203

J3-1

I/O18_QS

200

J3-2

I/O19_QS

199

J2-1

I/O20_QS

198

J2-2

Number

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I/O21_QS

197

J2-3

I/O22_QS

196

J2-4

I/O23_QS

194

J2-5

I/O24_QS

191

J2-6

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LAB 1 Generate Waveforms using DAC 1.1 Introduction Analog signals represent real physical parameters with accuracy, but it is difficult to process or store them. It is necessary to translate an Analog signal into a Digital signal. Similarly, a digital signal needs to be translated into an analog signal to represent a physical quantity. Quite often it is also necessary to decode any digital signal, the most obvious method is to use D/A converter for each signal. Therefore it is necessary to study the behaviour of DAC. For that waveform generation using DAC is done. Various waveforms such as square, sine, triangular, ramp etc. can be generated. In this lab ramp waveform is being generated. DAC:- Digital to analog conversion involves translation of digital signal into equivalent analog signal. Applications of DACs include digital voltmeters, peak detectors, panel meters, programmable gain and attenuation, and stepping motor drive.

1.2 Specifications of DAC AD7541: • • • • •

DAC type – Monolithic Multiplying DAC structure. Resolution - 12 bits Conversion time - 100 ns Settling time – 600 ns Output Range – (-10 to +10 Volts, Bipolar)

The two important aspects of the D/A converter are the Resolution & Accuracy of the conversion. ACCURACY:-Accuracy is a measure of how close the actual output voltage is to the theoretical output voltage. RESOLUTION:-Resolution is the smallest increment in output voltage and is determined by the LSB. n Ex:-If the full scale Analog voltage is 10V, the smallest unit or the LSB is equivalent to 1/2 of 10V. This is defined as resolution. DAC AD7541 used on SP3 DSP Protoboard is 12 bit and the Full scale voltage of the analog output block is 10V Hence the resolution of the analog output block is 10V/212 12 LSB = 10/2 MSB= ½ full scale = 5V Full scale output =(Full scale Value–(1 LSB)) = 10V-(10V/212). ------For 12 bit DAC = 9.998V. Figure1 shows a block diagram of a 3-bit DAC and characteristics of digital input vs. analog output

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Figure 1

1.3 Objective After completing this lab you will be able to • Perform the basic design flow for generating Counter in VHDL. • Simulate a VHDL file. • Synthesize a design using XST. • Implement a design using the Xilinx implementation tools. • It will help you to understand behaviour of DAC it should show proper RAMP at the output.

1.4 Design Description In this lab ramp waveform is being generated, for that you will have to design a counter .Counter output is mapped to DAC input as shown in figure. This will help you to understand behaviour of DAC & interfacing of DAC with FPGA to generate waveforms of different amplitude and frequency.

1.5 Experimental Set up

In above figure we can implement 3 bit loadable up /down counter. with asynchronous reset. Counter output is given to DAC to generate Ramp output waveform.

1.6 Procedure To design Counter, perform the following steps: Step 1:

Start the Xilinx Project Navigator by using the desktop shortcut or by using the Start Æ Programs Æ Xilinx ISE 7 Æ Project Navigator Step 2: In the Project Navigator window go on FILE ÆNew projectÆselect device.

Step 3:

Click on FPGA symbol of device and then right clickÆ click on new source ÆVHDL module give name countÆDefine portsÆfinish.

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Step 4:

Generate the Behavioural VHDL Code for the counter.

Step 5:

Check syntax, remove errors if present.

1.7 Simulate the Design Using ModelSim In this procedure, simulate your VHDL code to verify that it is functioning correct. After simulation if there is an error, you can go back and make changes, recompile the code, and resimulate. To run the functional simulation, perform the following steps: Step 1:

Again generate test waveform using Test bench waveform Editor.

Step 2:

Highlight count_tb.vhd file in the Sources in Project window.

Step 3:

Expand the Xilinx simulator /Modelsim simulator in the Processes for Current Source window.

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Step 4:

Double-click on Simulate Behavioral VHDL Model. If the modelsim simulator is used then Model Technology window pops-up, click Run ModelSim. The simulation will run. Otherwise on the ISE simulator window waveforms are displayed.

s Step 5:

Verify the operation of the counter by looking at the input and output signals in the test bench named *_tb

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Note: It may be easier to view the input and output in decimal. This can be done by highlighting the appropriate signals in the waveform viewer, then use the pull down menus Format Æ Radix Æ Decimal. Step 6:

After you verify operation you can close ModelSim .If the counter is not functioning correctly, verify your VHDL code and re-run the simulation.

1.8 Synthesize the Design Using XST Now that design has been verified using the ModelSim VHDL behavioural simulator, you can synthesize your design. We do this by using the Xilinx Synthesis Technology (XST). To synthesize your design, perform the following steps: Step 1: Highlight counter.vhd file in the Sources in Project window. Step 2:

To run synthesis, right-click on Synthesize, and choose the Run option, or double-click on Synthesize in the Processes for Current Source window. Synthesis will run, and a green check will appear next to Synthesize when it is successfully completed.

A yellow exclamation mark indicates that a warning was generated, and a red cross indicates an error was generated. Warnings are OK.

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Step 3

If there are any errors, you can View Synthesis Report by expanding Synthesis, right-click and Choose the View option; otherwise continue on to the next step.

1.9 Running the Xilinx Implementation Tools Once synthesis is complete, you can place and route your design to fit into the FPGA provided on the protoboard (XC3S400-5PQ208), you can also get post place-and-route timing information about the design. This procedure runs you through the basic flow for implementation. To run the implementation tools, perform the following steps: Step 1:

Right-click Implement Design, and choose the Run option, or double left-click Implement Design.

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This runs the design through Place and Route. You will notice green check marks (or warning exclamations) next to the processes that means finished successfully. Step 2:

To get the Post Place and Route Timing, run Generate Post-Place & Route Static Timing, and when finished, expand and open the Text. Based Post-Place & Route Static Timing Report.

You can view the results in the console window

1.10 Download design into DSP Protoboard For Downloading bitstream into DSP Protoboard follow the procedure given below. • Before the implementation write UCF file using User constraints in workspace • Double click on create timing constraintsÆportsÆLocations

Note: - User constraint file (UCF) is used to lock the input and output which we are going to use.

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Step 8: Step 9:

Right-click on Generate Programming File, and choose the Run option, or double left-click on Generate Programming File. This will generate the Bitstream. Double click on Configure Device to download the bitstream.

Step 10: Connect the CRO probe to the DAC Out terminal to observe “Ramp waveform” as shown in figure below. Thus the digital input applied through counter is converted into an analog ramp waveform.

1.11 Conclusion You should now know the basic design flow for taking VHDL through the design process. You have: • Realized some challenges in writing the VHDL counter. • Run a piece of VHDL code through simulation. • Run synthesis using XST. • Run a synthesized design through the Xilinx implementation tools. • After downloading check output of DAC on Four output analog channel.

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1. What is the Implementation Result. See the Place and Route report file and fill in the information below • Number of slices:_________________________________ • Number of global buffers (BUFGMUXs): _______________ • Number of IOBs: __________________________________ 2. Open the Post-Place and Routing Timing report, and fill in the information requested below • Maximum clock frequency: ___________________________ • Generate a square and triangular waveform. (Hint. Change the counter direction according to waveform) 3. Maximum clock frequency: _______________________ 4. Design counter which will give Ramp output waveform of amplitude 2.5V. (Hint – Refer graph of digital input Vs analog output and modify the counter.) 5. Modify the design to change the frequency of Ramp wave 6. What will be the change in the functionality if we want an inverted ramp at the output? 7. How will you change the step size? 8. What will happen if the time scale is changed? Draw the waveform and write down the observations for two different time scales. 9. Write a code to generate sine wave, square wave and triangular wave at the output of the DAC. Try for different values of frequency and amplitude keeping in mind the specifications of DAC. 10. How 4MHz clock frequency can be divided to see counter response on LEDs. If clock is applied directly what would you observe? 11. Define Resolution Time & Settling Time.

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LAB 2 Verification of Sampling Theorem using ADC-DAC 2.1 Introduction Most signals such as speech, biological signals, various communication signals such as audio and video signals, are analog. To process analog signals by digital means, it is first necessary to convert them into digital form. The devices used for this are Analog to Digital converters (ADCs). In many cases it is desirable to convert the processed digital signals into analog form. This process is done by Digital-to-Analog converters (DACs). In this lab, sampling theorem is verified. According to the Sampling theorem, the sampling frequency should be double or more than double the highest input frequency. The input to ADC is given through an external source and here sampling frequency is fixed. The input frequency can be increased to see the aliasing effect at the output. Aliasing is the process where a sinusoid changes from one frequency to another as a result of sampling or other nonlinear action and usually results in a loss of signal’s information. Increasing the input frequency to more than half the sampling frequency gives aliased low frequency waveform at the output. 2.2 Objective The design example in this lab is to demonstrate • How to write and execute Matlab Simulink program. • How to generate VHDL/VERILOG code from the system generator. • How to modify ADC-DAC program according to your application. • How to use in build function generator. • How to adjust sampling frequency. 2.3 Design Description:• External/On-Board Analog input can be given to the ADC, it converts applied analog input to 12-Bit Digital signals. This signal is then given to DAC via FPGA and the output is checked at the DAC output. • Five channels of ADC are used, wherein Channel 1 to Channel 4 gets the input from an external source & Channel 5th is used on board for Thermister. • Output of ADC is then given to FPGA, Conversion Start, ADC clock and channel address signals are generated through FPGA. FPGA receives End of conversion (EOC) from ADC. • FPGA will map ADC output directly to DAC input. • Digital to Analog converter accepts input from FPGA, converts digital data to Analog signal. • Output of DAC is available on the connector. (Refer connector details given below)

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2.4 Experimental Set up:-

Step1: Step2: Step3: Step4: Step5: Step6:

Open the MATLAB command window by double clicking on the MATLAB icon, which is provided on the desktop. Open the Simulink library browser window by typing Simulink on the command prompt (>> Simulink) or clicking on the Simulink library browser. Now open the new model file by >> File >> New >> Model. Go to Simulink library browser and click on sources and select the signal generator block and drag that into new model file. Then you click on sinks, here you select the scope and drag that on to the sheet. Then you click on Xilinx block set in the library browser and then click on basic elements and select the system generator block, Gateway In, and Gateway Out blocks and drag them on to new model file.

Fig1. shows the Simulink library

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Step7: Now interconnect all the blocks. The following figure shows how it looks like. Fig. shows how to interconnect the different Simulink block.

Step8:

Double click on each block, the parameter window will open and select the parameters. For signal generator choose parameters as waveform as sine wave, amplitude as 3V, and frequency as 0.135 rad/sec. Note: Frequency (rad/sec) = 2πFp / Fs. Fig. shows how to set signal property of signal generator Simulink block

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Now double click on Gate Way In block, the parameter window will open and fill the

parameters as given below. Step9: Run your simulation and observe the output waveform by double clicking the Simulink scope. Step10: Now double click on the System Generator block , parameter window will open Here you select target device in which you want to implement your design and target directory that is location at which you want to store your VHDL project file. The parameter window looks as shown in figure.

Step11: After selecting the proper device and proper project directory click on Generate. Here the pop up window will open that shows the running of system generator as shown in figure.

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Step12: Check the generated code in specified folder. 2.5 Generate, Synthesize, and Place & Route in Xilinx Step1: Double click on Xilinx project navigator icon, which is provided on the desktop. Step2:

Now go to >> File. >> Open project, here you have to specify the path at which your design has been stored.

Step3:

Now add the ADC_DAC controller VHDL Design to your file. This is done as: Right click on the source file and click on add new source. The following shows how it happens.

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Step4:

After that you have to write user constraint file for the ADC_DAC controller VHDL Design. This is also done by right clicking on source file >> new source>>Implement constraint file. >> file name >>next The following depicts that.

Step5:

After writing constraint file you go to processes for source window and run the synthesize process. The following depicts that.

Step6:

After running synthesize process run the implement design. The following depicts that.

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Step7:

click on Generate program file. and go to the properties. Then pop up window will open. In that you go to start up options and select the desired clock. The following is depicts that.

Step8:

The above process will generate the bit file. Now right click on the configure device and click on the properties. Then pop up window will open. Select the particular configuration mode. The following figure depicts that.

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Step9: After selecting the configuration mode you program your device by downloading bit file into the FPGA. Note: System generator generates the code corresponding to the logic in between Gateway In and Gateway Out. The signal generator and the scope used by the system generator are just for simulation. Use onboard function generator for input signal. Observe the results on CRO. This function generator and CRO are for physical verification. 2.6 For physical verification: After configuring the device you apply the input signal to any one channel of ADC (ch1, ch2, ch3, ch4) and output of DAC i.e. (Vout1, Vout2, Vout3, Vout4) is applied to CRO and observe if there is any deviation from input Repeat same procedure for various ADC sampling frequency by changing the positions of DIP switches (IL0, IL1, and IL2) and observe the output. The above procedure should repeat for square wave and triangular wave inputs. 2.7 Assignments 1

Open the place and route tool and fill the following? • Number of slices consumed:_____________________________ • Number of IOBs:________________________________________ • Number of GBUFs:_______________________________________ 2 What would be the effect of change in sampling frequency? 3 Repeat the whole experiment for square & triangular input signal. 4 Change the sampling frequency and input frequency. Observe the aliasing effect on CRO. 5 How to select the sampling frequency of ADC? 6 Write down the specifications of ADC and DAC. 7 What is the maximum input frequency? 8 If two more channels of ADC are used, what will be the change in the above code? 9 See the Place & Route report and give the number of global buffers, LUTs, and IOBs. 10 Change the input frequency and observe the change at the output.

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LAB 3 FIR filter using windowing method 3.1 Introduction In this lab, you can study one way to specify, simulate, and implement a FIR filter using the MATLAB Filter Design & Analysis Tool (FDA Tool). The FDA Tool is used to define the filter order and coefficients, and the Xilinx FIR filter Blockset is used for the implementation and Simulink simulation. MATLAB is a tool which is best suited for DSP algorithm development. Xilinx ISE tool is used for implementation of systems in FPGA. But there is a gap between these two. tools. This gap can be filled by Xilinx System Generator Tool The algorithms /system can be verified using MATLAB Simulink blocks. Xilinx system generator tool is a part of Simulink tool box. System generator is used to generate VHDL and all supporting files. Xilinx ISE tool. is used to synthesize, implement and programming of FPGA. Design a FIR Filter using Windowing method for a given frequency response. • Sampling frequency (Fs) =20000Hz • Passband frequency (Fpass) =3000Hz • Stopband frequency (Fstop) =4500Hz • Passband attenuation (Apass) =1dB • Stopband attenuation (Astop) =80dB To design the filters by using “window” method. Here we have to design the filter in the FDATool with the desired filter specifications and export the coefficients to the Simulink workspace. Windowing is one of the method for designing FIR filter. Other method is the “frequency sampling” method.

3.2 Objective After completing this lab you will be able to write and simulate Simulink program. Understanding the basics of building in designing a system generator. Simulate the design in the System Generator. Run the system generator token for generating the VHDL code. Run the designs through System Generator design flow.

3.3 Procedure Step1:

Open the MATLAB command window by double clicking the MATLAB icon that is provided on the desktop.

Step2:

Open the Simulink window by typing the Simulink at the command prompt (>> Simulink) or clicking on the Simulink Library Browser. The Simulink window will be as shown below.

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Step3: Look at the blocks that are available on the window. The following are the blocks. • SIMULINK (sources and sinks) • DSP Block set • XILINX Block set Step4:

Right click on block on the library browser and choose help from the MATLAB menu

This bring up the details of the block and it also work on the Xilinx block set elements Step5:

Create a new model file

Go to file >> new>> model

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Step6:

Go to sources and select the signal generator and add that to the model file. Go to sinks and select the Scope and add that to the model file. Double click on Signal Generator block to set its parameter Select type of wave form

Write amplitude of input signal

Ratio of input Freq and Sampling freq

Step7:

Go to Xilinx Blockset and click on the Basic Elements and select the system generator, GateWay In and GateWay Out blocks and add them to the new model file.

Step8:

Go to the DSP section in the Xilinx block set and right click on the FIR block and add to the new model file.

Fig shows interconnection of above selected components

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Below a Block Diagram of FIR filter is shown

IO blocks used as interface between the Xilinx blockset and other Simulink blocks

Simulinksources

SysGen blocks realizable in Hardware

Simulink sinks & library function

Double click on FIR Xilinx Blockset, to set parameters of FIR • Coefficients generated from FDA tool.

• Latency is required since FIR is a synthesizable xilinx block.

• Easy generation of cores.

Step9:

Now go to MATLAB command window and type FDATool (>> FDATool) _you get will get window

Step10: Then you enter the following specifications • Sampling frequency (Fs) =20000Hz. • Passband frequency (Fpass) =3000Hz. • Stopband frequency (Fstop) =4500Hz. • Passband attenuation (Apass) =1 dB. • Stopband attenuation (Astop) =80 dB. Ð Select design method as “Kaiser Window” Ð Select type of filter as “low pass FIR” Ð Click on design filter.

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The FDATool generates the filter with the desired specifications. In the FDA tool you can observe • magnitude response of the filter • phase response • magnitude and phase response • Group delay response • impulse response • step response • pole zero plot

Step11:

Go to file and export the filter coefficients to the workspace. >> File >>Export The following depicts how it looks like

Fig shows how the filter coefficient export to work space

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Select Export to >>Workspace Export as >>Coefficients >> ok.

Step12:

Now come back to your model file where you have designed your design file and double click on FIR block .Here the parameter window will open and type the Num in the coefficients and click OK. The parameter window will look like below.

After that double click on the signal generator block and select the waveform, amplitude, and frequency. Step13:

Set the simulation time 1000 and run the simulation.

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Step14:

Now double click on the System Generator block, parameter window will open. Here you select target device in which you want to implement your design and target directory that is location at which you want to store your VHDL project file. The parameter window looks as shown below.

Design core will be stored at this location

After selecting the proper device and proper project directory click on Generate. Here the pop up window will open that shows the running of system generator as shown in figure

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Implementation of Design which is generated by MATLAB in Xilinx ISE tool. When a System Generator project is created, the software produces VHDL design or cores from the Xilinx CORE Generator. In addition, many other project files are automatically created. Step15:

Now open the Xilinx project navigator and go to >>file >> open project. Here you need to provide location at which your generated file has stored.

. Step16:

Now add ADC-DAC controller design & generated VHDL/VERILOG core to your project files. Modify ADC-DAC controller according to your application. Instantiate Core, generated by MATLAB as a component in ADC-DAC controller design.l

Step17:

Then you have to provide .ucf file(User Constraint file). Right click on VHDL file >> new source >> Implementation Constraint File >> specify constraints for the Design.

Step18:

Note – Refer the user constraint file(UCF) which is attached at the end of this manual. Then go to the processes for the source in the navigator window and double click on the“Synthesize”.

Step19:

Then right click on “Implement the design” and click on Run.

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Step20:

Then right click on “Generate programming file” and go to properties and then go to the start up options. Select the clock as CCLK or JTAG. The figure below depicts that procedure.

Step21: Step22:

Then run “Generate programming file”. This will generate the bit file. Then go to processes for source window and right click on “Configure device” >> properties >> slave serial / Boundary-scan mode depending upon the selection of clock (CCLK, JTAG clock).

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t

Step23:

Then double click on “Configure device”. Download bitstream into FPGA and follow the procedure to verify desired filter on FPGA.

Now you can verify your design by applying sine wave input to any one of the channels and see the output waveform on the CRO. Set the frequency to 60Hz and increase it gradually to cut-off frequency and go beyond the cut-off frequency and observe the output on the CRO. You may notice that if the frequency is increased beyond the cut-off frequency the amplitude will reduce gradually and as you move far away from cut-off frequency the output will become zero. Download the bit file in the Device.& follow the following procedure • Give input (Square) to ADC using connector (CH1, CH2, CH3, CH4). • Using preset PR2 we can adjust the magnitude of input square wave. • Now set frequency of square wave to minimum possible using preset PR1. Check the output. It should be same as input square wave since the filter has pass band frequency of 2000Hz. • If the output shows distorted waveform, adjust the truncation bit using sw2 (input switch). In this case fix IL3 (SW2) = 1 and rest all zeros. • Now increase the frequency continuously and check output. As you approach 2000 Hz, the output will start converting to a sin wave of frequency equal to frequency of square wave • Above 2000Hz output will remain sine curve but its amplitude will start decreasing. You can repeat the above procedure for high pass filter, band pass filter, and band reject filter.

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3.4 Assignments 1. Open the place and route tool and fill the following information • Number of slices ____________________________________ • Number of IOBs ____________________________________ • Number of GBUFs ____________________________________ • Maximum clk frquency ____________________________________ 2. What should be the cut-off frequency? 3. Describe windowing design method of above filter How it differs from the Fourier series and frequency sampling method. 4. Draw the waveforms of Different Window functions? 5. What are the different windows available for filter design? What is the criterion to design a particular window? 6. Use different type of window for design a filter with same frequency response

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LAB 4 Design of FIR filter 4.1 Introduction This lab is to design low pass FIR filter by using Equiripple Design method. The filter specifications are as follows • Sampling frequency : Fs = ***** • Passband frequency : Fpass = 2 KHz • Stopband frequency : Fstop = 5 KHz • Passband ripple : Apass = 1dB • Stopband ripple : Astop = 24

4.2 Procedure • •

Drag & Drop the required components from the DSP Blockset. Generate Coefficients for the FIR Filter:Ð you specify the filter characteristics through the MATLAB FDA Tool, Save the coefficients to the workspace, and use the coefficients in the Xilinx FIR filter Blockset. • To analyze the output of the filter, input and output signals are displayed in a spectrum scope and a transfer scope. Note-A spectrum scope is used to compare the frequency response of the fixed- point FIR filter, and the double precision direct form II Transpose filter.

4.3 Filter Design Fixed- point FIR filter is implemented in the FPGA. while Transpose filter is invoked from the Simulink Blockset library. To design the filter using the FDA Tool, perform the following steps: Step 1: Start the FDA Tool by typing >> fdatool in the MATLAB Command window. Step 2: Enter the following filter parameters in the Filter Design & Analysis Tool • Sampling frequency : Fs = ***** • Passband frequency : Fpass = 2 KHz • Stopband frequency : Fstop = 5 KHz • Passband ripple : Apass = 1dB • Stopband ripple : Astop = 24dB Click on the Design Filter button to find out the filter order

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Error!

Step 3:

In the FDA Tool startup window, choose File → Export .

Step 4:

Click OK to save the coefficients in the Workspace.

Step 5:

Save Coefficients in the Workspace. You will observe two new variables in your MATLAB workspace: Num and Den. For a FIR filter, Den is equal to one, and Num represents the coefficients that are used in the filter.

Step 6:

Type Num from the MATLAB workspace to see the list of Coefficients >> Num.

Step 7:

Add the FIR filter block from the Xilinx Blockset/DSP library. Double click the Xilinx FIR Filter block, and specify the variable Num in the coefficients parameter field as well as the coefficient width of Fix12_6. Also, in this design, it is possible to deselect the “Provide Valid Ports” option because there is a continuous and always valid data on the input of the FIR filter. Step.8: Now interconnect all the blocks Fig. shows how to interconnect the different Simulink block.

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4.4 Simulate the FIR filter in Simulink Following steps are needed to implement FIR in Simulink. Step 1:

To simulate the block click on Simulation icon.

Step 2:

Select simulation time (i.e. 1000).

Step 3:

Click on start simulation.

Step 4:

Double click on scopes.

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Step 5:

Click properties to change the number of axis displayed and the time range value (X-axis).

Step 6:

Use Data history to control how many values are stored and displayed on the scope.

Step 7:

Click auto scale to configure the display to the correct axis values.

Step 8:

Right click on the Y-axis to set its value.

Step 9:

Click on play to see response of signals on scope.

An error will be reported regarding the filter latency when you stop simulation: Error reported by S-function 'xlfir' in block 'filter1/FIR': To use a core, latency must be increased to at least 13. Behaviour of the configured block can be simulated. It is not possible to target it in to hardware as no synthesizable filter code is provided by FDA Tool Note: At this point, you need to re-open the FIR Filter parameters and set the latency to 13 as specified in the Error Message.

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4.5 Generate Synthesize and Place and Route In third section, you will observe that what impact of data width, coefficient width, and the number of taps has on the size and performance of the Filter Implementation. Step 1:

Open the FIR filter Blockset, and verify that all the parameters are set as follows

Step 2:

Select the SPARTAN-III family, the XC3S400-4pq208 device, XST and generate the toplevel VHDL code with the System Generator icon.

Step 3:

Open Project Navigator by double-clicking the filter1.npl file in Windows Explorer.

Step 4:

Synthesize and Implement the design

Step 5:

Now, go back to the Simulink filter design example, and decrease the coefficient width to Fix12_6.

Step 6:

Rerun Synthesize and Implement in the Project Navigator.

Step 7:

Download Design into FPFA and follow following procedure to verify desired filter on FPGA.

4.6 Download the bit file in the Device. • • • • • • •

Give input (Square) to ADC using connector Using PR2 we can adjust the magnitude of input square wave. Now set frequency of square wave to minimum possible using PR1.Check the output. It should be same as input square wave since our filter has pass band frequency of 2000Hz. If the output shows distorted waveform adjust the truncation bit using sw2 (input switch).In this case fix IL3 (SW2) = 1 and rest all zero. Now increase the frequency continuously and check output. As you approach 2000 Hz, the output will start converting to a sine wave of frequency equal to frequency of square wave Above 2000Hz output will remain sine curve but its amplitude will start decreasing. As you increase frequency beyond 3000Hz the output magnitude (peak-peak) will start vanishing.

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4.7 Assignments 1. Based on the above description, what is the minimum order of the filter? 2. What difference does increasing or decreasing the coefficient width make on the filter response? 3. How many slices are used and are the timing constraint met? 4. What is the actual clock period? what is the actual filter sample rate? 5. What impact does decreasing the coefficient width and input data width on the filter size? 6. Design FIR Filter by using Least-Squares, Window, Equiripple, Maximally Flat Design methods. • Determine the values of the Co-efficients. 7. Observe & verify Magnitude, Phase, Magnitude & Phase, Group delay, Impulse, step response of the above designed filter.

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LAB 5 Implementation of aliasing effect 5.1 Introduction This is an interfacing code for ADC and DAC. Sampling frequency will remain fix here. We can change our input frequency to observe aliasing effect at output. According to the Sampling theorem, the sampling frequency should be double or more than double the highest input frequency. The input to ADC is given through an external source and here sampling frequency is fixed. The input frequency can be changed to see the aliasing effect at the output. Aliasing is the process where a sinusoid changes from one frequency to another as a result of sampling or other non-linear action. Usually results in a loss of signal’s information. Increase in input frequency more than half the sampling frequency gives alias low frequency waveform at the output. 5.2 Objective In this lab we will verify the “Nyquist criteria”. We can change our input frequency to see aliasing effect at output of DAC (According to Nyquist criteria sampling frequency should be double / more than double the highest frequency of the input signal).As soon as increase the input frequency more than half of sampling frequency , we will observe alias low frequency waveform at output. 5.3 Design Description Configuration of system for Digital processing of an analog signal

Input

Antialiasing filter

ADC

DSP µP

1…01

Discrete Logic

0..10

DAC

DSP

ASICs

Reconstruction Output Filter

FPGA

Sampling Theorem:If the highest frequency of a signal is Fmax then the signal should be sampled at the rate of at least 2fmax for the samples to describe the signal completely Fs >=2Fmax( Fs = sampling frequency) Aliasing :- Sampling does not results in a loss of information nor does it introduce distortion in the signal if the signal bandwidth is finite In principle, the analog signal can be reconstructed from the samples, provided that the sampling rate is sufficiently high to avoid the problem commonly called Aliasing Anti aliasing filter : Anti-aliasing filter is used to reduce the effect of aliasing. For that purpose sharp cut-off. anti-aliasing filters are used to band limit the signal.

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The sampling frequency is increased, to widen the separation between the signal and image spectra. Any frequency components of the signal above the folding frequency Fs/2 are sufficiently attenuated by Anti aliasing filter. DSP processor is used to implement DSP algorithms DAC. Advantages of DSP Processor • Quick turnaround- Software can be easily changed & functionality modified • Reconfigure-same hardware resources can be reused for different designs. Reconstruction filter : Output of the DAC is need to be reconstruct using low pass analog filter .before giving to the final output .It serves two purpose first reconstruct output of DAC and second Remove unwanted frequency i.e above Nyquist frequency 5.4 Procedure • Use reference material of ADC,DAC . • Study of ADC and DAC data sheets in details. • Write VHDL code for interfacing ADC and DAC. • Set sampling frequency through VHDL code • Download design code in DSP proto board • So when we apply sin wave/square wave at input and increase its frequency (using PR1 and SW2) we will get same output frequency as input frequency till half the sampling frequency. As soon as we cross this frequency (in this case 15.625Khz or 19.53125Khz respectively for 4Mhz and 20Mhz) we will start observing aliased (low frequency)sin wave. 5.5 Simulate the Design Using Modelsim Follow same procedure as in counter. 5.6 Synthesize the Design Using XST Follow same procedure as in counter. 5.7 Running Xilinx Implementation tool Follow same procedure as in counter. 5.8 Assignments 1 2 3 4 5 6 7 8 9

Which type of ADC,DAC is used on protoboard? Write down the specifications of ADC,DA.C What is the maximum input frequency?. How to set input frequecny range for function generator? Write VHDL code for programmable sampling frequency. What is the minimum sampling rate available in your protoboard?. How to get desired sampling clock from DSP board to ADC?. What is aliasing.and How to reduce aliasing effect?. What is Quantization, Expain Midtread & Midriser Uniform Quantization? Define “Sampling Theorem”.

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LAB 6 IMPULSE RESPONSE OF GIVEN FILTER 6.1 Introduction In this lab, you can study one way to specify, simulate, and implement a impulse response of FIR filter using the MATLAB Filter Design & Analysis Tool (FDA Tool). The FDA Tool is used to define the filter order and coefficients, and the Xilinx FIR filter Blockset is used for the implementation and Simulink simulation. The impulse response of a linear time-invariant system is defined as the response of the system to a unit sample excitation. The output of the system is convolution of input signal x(n) and the system function h(n). The impulse response of a system helps in finding the stability of that system.

X(n)

System h(n)

Y(n)

Fig 1 Block Diagram The output of the above diagram can be defined as N y(n) = ∑ [x(k)*h(n-k)] k=0 In frequency domain the output of a system is multiplication of Fourier transform of input and system function i.e. Y(w) = X(w) * H(w) Since Fourier transform of impulse signal (input signal X(w)) is equal to 1, hence output is equal to H(w) i.e. Y(w) = H(w) Taking the Inverse Fourier Transform, we will get y(n) = h(n) Multiple manipulations helps you to understand what impact of changing the coefficient and data width on both the quality of the filter response and the resulting size MATLAB is a tool which is best suited for DSP algorithm development. Xilinx ISE tool is used for implementation of systems in FPGA. But there is a gap between these two. tools. This gap can be filled by Xilinx System Generator Tool The algorithms /system can be verified using MATLAB Simulink blocks. Xilinx system generator tool is a part of Simulink tool box. System generator is used to generate VHDL and all supporting files. Xilinx ISE tool. is used to synthesize, implement and programming of FPGA. Design a High pass filter for a given filter parameter • Sampling Frequency (fs): =62500Hz • Pass band Frequency (fpass): =3000Hz • Stop band Frequency (fstop): =1000Hz

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6.2 Design Procedure Using MATLAB: Step1: Open MATLAB command window ( by double clicking on the MATLAB icon) Step2: Open the Simulink library browser window by typing Simulink on the command prompt (>> Simulink) or by clicking on the Simulink library browser. Step3: Open a new model file by >> File >> New

>>

Model

Step4: Go to Simulink library browser and click on sources and select the Pulse generator block and drag that into new model file. Step5: Click on sinks and select scope. Drag scope on to open sheet. Step6: Click on Xilinx block set in the library browser, when in it Click on basic elements and select system generator block, Gateway In block and Gateway Out block. Drag them on to new model file. Step7: Now interconnect all the blocks. It will look as shown in Fig-2. Step8: Double click on each block, the parameter window will open and select the parameters.

Figure 2

6.3 Pulse Generator The Pulse Generator block generates square wave pulses at regular intervals. The block's waveform parameters, Amplitude, Pulse Width, Period, and Phase Delay, determine the shape of the output waveform. The Pulse Generator can emit scalar, vector, or matrix signals of any real data type. To cause the block to emit a scalar signal, use scalars to specify the waveform parameters. To cause the block to emit a vector or matrix signal, use vectors or matrices, respectively, to specify the waveform parameters. Each element of the waveform parameters affects the corresponding element of the output signal. For example, the first element of a vector amplitude parameter determines the amplitude of the first element of a vector output pulse. The data type of the output is the same as the data type of the Amplitude parameter. The block's Pulse type parameter allows you to specify whether the block's output is time-based or sample-based. We have to select sample-based, the block computes its outputs at fixed intervals that we specify. This can result in fewer computations being required to compute the block's output over the simulation time period. Depending on the pulse's waveform characteristics, the intervals between changes in the block's output can vary. For this reason, Simulink cannot use a fixed solver to compute the output of a

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time-based pulse generator. Simulink allows you to specify a fixed-step solver for models that contain time-based pulse generators. However, in this case, Simulink computes a fixed sample time for the time-based pulse generators. It then simulates the time-based pulse generators as sample-based.

Note If you use a fixed-step solver and the Pulse type is timebased, you must choose the step size such that the period, phase delay, and pulse width (in seconds) are integer multiples of the step size. For example, suppose that the period is 4 seconds, the pulse width is 75% (i.e., 3 s), and the phase delay is 1 s. In this case, the computed sample time is 1 s. Therefore, you must choose a fixed-step size that is 1 or that divides 1 exactly (e.g., 0.25). You can guarantee this by setting the fixed-step solver's step size to auto on the Configuration Parameters dialog box. If you select time-based as the block's pulse type, you must specify the pulse's phase delay and period in units of seconds. If you specify sample-based, you must specify the block's sample time in seconds, using the Sample Time parameter, then specify the block's phase delay and period as integer multiples of the sample time. For example, suppose that you specify a sample time of 0.5 second. And suppose you want the pulse to repeat every two seconds. In this case, you would specify 4 as the value of the block's Period parameter

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LAB 7 Design Of A Bandpass Filter Design the Bandpass Equiripple filter for given filter specification. • • • • • • • •

Sampling frequency(fs) :62500Hz Stop band Frequency1 :500Hz Pass band Frequency1 :2000Hz Stop band Frequency2: 8000Hz Pass band Frequency2 :6000 Hz Stop1 band ripple (Astop1 = 60 db) Pass band ripple (Apass = 1db) Stop2 band ripple (Astop2 = 60 db)

7.1 Procedure Follow the steps taken in LAB 3

7.2 Assignments 1. 1:Open the place and route tool and fill the following information • Number of slices consumed____________________________ • Number of IOBs_______________________________________ • Number of GBUFs______________________________________ • Maximum path delay___________________________________ 2: What is bandpass filter? How it differ from the highpass and lowpass filter. 3:Draw the simple sketch which shows filter specification of Bandpass filter.

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LAB 8 Design Of A Band Reject Filter Design the Bandreject Equiripple filter for given filter specification. • • • • • • • •

Sampling Frequency (fs) 62500 Hz Stop band Frequency1 (Fstop1) 3000 Hz Stop band Frequency2 (Fstop2) 4000 Hz Pass band Frequency1 (Fpass1) 1000 Hz Pass band Frequency2 (Fpass2) 6000 Hz Apass1 = 5 db Apass2 = 1 db Astop = 60 db

8.1 Procedure Follow the all step as taken in LAB 3.

8.2 Assignments • Open the place and information Ð Number of slices Ð Number of IOBs Ð Number of GBUFs Ð Maximum path •

route tool and fill the following consumed______________________ ________________________________ ________________________________ delay _____________________________

What is Bandreject filter? How it differs from the highpass and lowpass filter?.

• Draw the simple sketch which will show filter specification of Bandreject filter.

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LAB 9 Noise Removal 9.1 Noise Removal This experiment shows the noise performance of given system. In this experiment we generate the signal of 400 Hz. The noise is introducing on given signal of the frequency 3 kHz. Then design the filter such that when this noise added signal pass through the filter it will remove noise from the signal. The noise is removing by using low pass filter. Suppose we are adding a noise of frequency 3 kHz on a signal of 400 Hz. The filter required to suppress the noise will have cutoff frequency of 400 Hz.

FIG : NOISE REMOVAL

9.2 Hardware Description The following is the configuration of the DSP development board. • It has a built-in Signal Generator generates, which generates a Sine wave of amplitude 10V peak to peak. • ADC on board has the following specifications Ð Resolution - 12 bits. Ð Input range - ±10V. Ð Output Format - ADC output can be in straight Binary or 2’s complement format. • DAC on-board has the following specifications Ð Resolution 12 bits Ð Output Range - ±10V. Ð Output Format – Straight Binary. • Crystal oscillator on board has a freq of 4 MHz.

9.3 Filter Design Procedure using MATLAB Step1:

Open MATLAB command window (by double clicking on the MATLAB icon)

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Fig -1 Block diagram of Filter Step2: Open the Simulink library browser window by typing Simulink on the command prompt (>> Simulink) or by clicking on the Simulink library browser. Step3: Open a new model file by >> File >> New >> Model Step4: Go to Simulink library browser and click on sources and select the signal generator block and drag that into new model file. Step5: Click on sinks and select scope. Drag scope on to open sheet. Step6: Click on Xilinx block set in the library browser, when in it Click on basic elements and select system generator block, Gateway In block and Gateway Out block. Drag them on to new model file. Step7: Now interconnect all the blocks. It will look as shown in Fig-2. Step8: Double click on each block, the parameter window will open and select the parameters.

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Fig-2

9.4 Filter Specifications: The specifications of the filter that we intended to design are as follows. • • • • •

Type of filter – Low Pass. Cut Off Frequency Fc = 400 Hz. Filter structure - Hamming Window Number of Taps – 128 Sampling frequency – Fs = 250KHz.

9.5 Signal Generator: Signal generator is used to verify your filter design in the Matlab domain. It applies an stimulus (note – this stimulus is in the digital domain) of your choice to the Filter. To program the signal generator, Double click on signal generator icon. A window as shown in Fig-3 will pop up. Signal Generator parameters • Amplitude: - The amplitude is the peak value of the input wave. • Frequency: - The frequency of input wave. Is entered as ratio of input frequency to • Sampling frequency. (2π * Fin / Fc radians /sec).

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Ð

The cut off frequency of our filter is 2000Hz and the sampling frequency is 250000Hz. Hence frequencies in the pass band are represented by a value 0.0502 or greater. We have input a value 0.135 which corresponds to an input frequency of 5370 Hz (a pass band frequency)

9.6 Gateway In Gateway In blocks are the inputs into the Xilinx portion of the user's Simulink design. These blocks convert Simulinks integer, double and fixed point data types into the System Generator fixed point type. Each block defines a top-level input port in the HDL design generated by System Generator. To set the block parameters of the gateway in block, double click on the gateway in icon, a window as shown in Fig-3 will pop up. FIG 3 GATEWAY IN WINDOW Selecting proper Gateway Parameters is crucial to proper implementation of the filter in hardware. The parameters programmed are directly derived from the hardware setup that the user has.

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(refer to the specifications of DSP development board given above) Also note that the Input to Gateway-In is coming from the on-board ADC, Output Data type – is chosen as 2’s complement, because the ADC that is how the ADC codes its output. Number of Bits: - represents the number of the bits required to represent the applied input. The on-board ADC is a 12 bit ADC, Hence we choose number of bits as 12. Binary Point: - It is position of binary point in the input value (from ADC) from the right hand side. We use a normalized number system (preferred way of doing a design using Matlab), Hence we put the binary point at 10 positions ( from the RHS), by doing this, • We have normalized our input between +1 to -1. Since the sign bit is represented by MSB. 0 bit in MSB represents a positive number and 1 in MSB represents a negative number. • The next bit (2nd MSB) bit is used to represent the integer value 1 and the remaining 10 bits represent the fractional value. 10 bits are sufficient to represent maximum fractional value (0.9999999999….). Quantization: - We choose the option truncate. It will truncate bits from MSB if our input number is more than 12 bits from input. Overflow: - It will wrap the input if our input number is more than 12 bits from input, which means value greater than +2047 will map as -2048.

9.7 FIR Filter Design: (Selecting Filter parameters) Number of Bits: - It indicates the number of bits required to represent coefficients Coefficient values lie between +1 to -1. We select to represent the coefficients by 12 bits, ( note that selection of number of bits depends upon the accuracy required and will affect the hardware consumed). Binary Point: - It is position of binary point in the filter coefficients from the right hand side. The coefficients are signed numbers, hence the MSB represents the sign bit, and the 2nd MSB represents the maximum magnitude, which is “1”, so we have to leave 2nd MSB bit for integer value representation and the remaining bits are used to represents fractional value of coefficient. (Note - as a thumb rule the position of the binary point is 2-bit places from the left.) Latency: - indicates the number of initial clock cycles lost after which the filter starts giving valid output. Latency is calculated as – [8 + log2 (taps)]

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9.8 FDA Tool:Step 1: Double click on FDA Tool Block and you get window that looks like below. Step 2: Then enter our filter specifications • Sampling frequency (Fs) = 250000Hz • Passband frequency (Fpass) = 400Hz (cut-off frequency) • Type of Filter - Windowed FIR • Type of Window – Hamming • Order – 128 taps Step 3: Go to file menu and export the filter coefficients to the workspace. (>> file >>export) Step 4 Now come back to your model file where you have design your design file and double click on FIR

9.9 GATEWAY Out Xilinx Gateway Out block is the output from the Xilinx portion of the user's Simulink design. This block converts the System Generator fixed point data type into Simulink’s Integer, Double, or Fixed Point, as selected by the user.

Selecting the decimal point position in output result. The decimal point position in the output will be at 20 places form the RHS. Reason - both the samples and coefficients had their decimal place at 10 places from the RHS. So when we multiply them, the decimal point position in the result shifts to 20 places from the RHS. Sign bit - the results are in 2’s compliment form hence MSB represents the sign bit.

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Applying Results to DAC. The results from Filter are as follows • Form - 2’s compliment • Number of Bits – 24 • Sign bit – at MSB. • Position of Decimal point – before the 19th bit • Maximum value of any output sample is between +1 to -1 (because output is also normalized.)

We also know from our DAC specification that we have a 12 bit DAC and it accepts inputs in straight binary format. Hence we take bits 20 This leads to 2-problems. 1. We need to select only 12 bits out of the 24 bits at gateway-out. 2. We need to convert the gateway-out data in 2’s compliment form to Straight Binary. The 12 bits that will represent the output will be selected as follows. MSB will be considered, because it represents the sign bit. The magnitude is represented by bits starting from bit position 19 (refer fig-7), hence we will take bits 19 down to 9 to represent the magnitude.

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LAB 10 Compiling MATLAB into an FPGA 10.1 Introduction The MCode block applies input values to an M-function for evaluation using Xilinx's fixed-point data type. The evaluation is done once for each sample period. The block is capable of keeping internal states with the user of persistent state variables. The input ports of the block are determined by the input arguments of the specified M-function and the output ports of the block are determined by the output arguments of the M-function. The block provides a convenient way to build finite state machines and control logic. In order to construct a MCode block, an M-function must be written. The M-file must be in the directory of the model file that is to use the M-file or in a directory in the MATLAB path. This tutorial provides two examples that use the MCode block. • Example 1 shows how to implement a function that returns the maximum value of its inputs; • Example 2 shows how to implement simple arithmetic operations; Example 1: Simple Selector This example is a simple controller for data path, which assigns the maximum value of two inputs to the output. The M-function is specified as the following and is saved in an M-file xlmax.m The Simulink design of example is

Note: write a matlab file name xlmax as given below function z = xlmax(x, y) if x > y z = x; else z = y; end The xlmax.m(file and function name ) file should be either saved in the same directory of the model file or should be in the MATLAB path. Once the xlmax.m has been saved to the appropriate place, you should drag a MCode block into your model, open the block parameter dialog box, and enter xlmax into the Mfunction MATLAB Function. After clicking the OK button, the block has two input ports x and y, and one output port z.

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The following figure shows what the block looks like after the model is compiled. You can see that the block calculates and sets the necessary fixed-point data type to the output port.

Example 2: Simple Arithmetic Operations This example shows some simple arithmetic operations and type conversions. The following shows the xlSimpleArith.m file, which specifies the xlSimpleArith M-function. The simulink design of example is

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function [z1, z2, z3, z4] = xlSimpleArith(a, b) % xlSimpleArith demonstrates some of the arithmetic operations % supported by the Xilinx MCode block. The function uses xfix() % to create Xilinx fixed-point numbers with appropriate % container types. % % You must use a xfix() to specify type, number of bits, and % binary point position to convert floating point values to % Xilinx fixed-point constants or variables % By default, the xfix call uses xlTruncate % and xlWrap % for quantization and overflow modes. % const1 is Ufix_8_3 const1 = xfix({xlUnsigned, 8, 3}, 1.53); % const2 is Fix_10_4 const2 = xfix({xlSigned, 10, 4, xlRound, xlWrap}, 5.687); z1 = a + const1; z2 = -b - const2; z3 = z1 - z2; % convert z3 to Fix_12_8 with saturation for overflow z3 = xfix({xlSigned, 12, 8, xlTruncate, xlSaturate}, z3); % z4 is true if both inputs are positive z4 = a>const1 & b>-1; This M-function uses addition and subtraction operators. The MCode block calculates these operations in full precision, which means the output precision is sufficient to carry out the operation without losing information.

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One thing worth discussing is the xfix function call. The function requires two arguments: the first for fixed-point data type precision and the second indicating the value. The precision is specified in a cell array. The first element of the precision cell array is the type value. It can be one of three different types: xlUnsigned, xlSigned, or xlBoolean. The second element is the number of bits of the fixed-point number. The third is the binary point position. If the element is xlBoolean, there is no need to specify the number of bits and binary point position. The number of bits and binary point position must be specified in pair. The fourth element is the quantization mode and the fifth element is the overflow mode. The quantization mode can be one of xlTruncate, xlRound, or xlRoundBanker. The overflow mode can be one of xlWrap, xlSaturate, or xlThrowOverflow. Quanitization mode and overflow mode must be specified as a pair. If the quantization-overflow mode pair is not specified, the xfix function uses xlTruncate and xlWrap for signed and unsigned numbers. The second argument of the xfix function can be either a double or a Xilinx fixed-point number. If a constant is an integer number, there is no need to use the xfix function. The Mcode block converts it to the appropriate fixed-point number automatically. After setting the dialog box parameter MATLAB Function to xlSimpleArith, the block shows two input ports a and b, and four output ports z1, z2, z3, and z4.

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M-functions using Xilinx data types and functions can be tested in the MATLAB command window. For example, if you type: [z1, z2, z3, z4] = xlSimpleArith(2, 3) in the MATLAB command window, you'll get the following lines: UFix(9, 3): 3.500000 Fix(12, 4): -8.687500 Fix(12, 8): 7.996094 Bool: true Notice that the two integer arguments (2 and 3) are converted to fixed-point numbers automatically. If you have a floating-point number as an argument, an xfix call is required.

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LAB 11 Design of A High Pass Filter 11.1 Introduction In this lab, you can study one way to specify, simulate, and implement a FIR filter using the MATLAB Filter Design & Analysis Tool (FDA Tool). The FDA Tool is used to define the filter order and coefficients, and the Xilinx FIR filter Blockset is used for the implementation and Simulink simulation. Multiple manipulations help you to understand what impact of changing the coefficient and data width on both the quality of the filter response and the resulting size MATLAB is a tool which is best suited for DSP algorithm development. Xilinx ISE tool is used for implementation of systems in FPGA. But there is a gap between these two. Tools. This gap can be filled by Xilinx System Generator Tool The algorithms /system can be verified using MATLAB Simulink blocks. Xilinx system generator tool is a part of Simulink tool box. System generator is used to generate VHDL and all supporting files. Xilinx ISE tool. is used to synthesize, implement and programming of FPGA. Design a High pass filter for a given filter parameter • Sampling Frequency (fs): =62500Hz • Pass band Frequency (fpass): =3000Hz • Stop band Frequency (fstop): =1000Hz

11.2 Procedure Design of FIR filter – 1. Drag & Drop the required components from the DSP Blockset. 2. Generate Coefficients for the FIR Filter:• you specify the filter characteristics through the MATLAB FDA Tool, Save the coefficients to the workspace, and use the coefficients in the Xilinx FIR filter Blockset. 3. To analyze the output of the filter, input and output signals are displayed in a spectrum scope and a transfer scope. Note-A spectrum scope is used to compare the frequency response of the fixed- point FIR filter, and the double precision direct form II Transpose filter.

11.3 Filter Design To design the filter using the FDA Tool, perform the following steps: Step 1: Start the FDA Tool by typing >> fda tool in the MATLAB Command window. Step 2: Enter the following filter parameters in the Filter Design & Analysis Tool • Sampling Frequency (fs): 62500Hz • Pass band Frequency (fpass): 3000Hz • Stop band Frequency (fstop): 1000Hz • Passband ripple (Apass = 1db) • Stopband ripple (Astop = 60 db)

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Sampling. Frequency

Stop frequency

Pass frequency

Click on the Design Filter button to find out the filter order Step 3: In the FDA Tool start-up window, choose File → Export

Go analysis ->select full view analysis observe all theoretical filter analysis • -Magnitude response. • -Phase response. • -Magnitude and phase response. • -Group delay response. • -Impulse response • -Step response. • -Pole /zero plot. • -Filter coefficient. • -Noise loading method.

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•

-Turn quantization on.

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Step 4: Step 5:

Click OK to save the coefficients in the Workspace. You now have two new variables in your MATLAB workspace: Num and Den. For a FIR filter, Den is equal to one, and Num represents the coefficients that are used in the filter. Type Num from the MATLAB workspace to see the list of coefficients. >> Num

Step 6:

Add the FIR filter block from the Xilinx Blockset/DSP library.

Step 7:

Double-click the Xilinx FIR Filter block, and specify the variable Num in the coefficients parameter field as well as the coefficient width of Fix12_6.(or Fix12_8) Also, in this design, it is possible to deselect the “Provide Valid Ports” option because there is a continuous and always valid data on the input of the FIR filter.

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Simulate the FIR Filter in Simulink Following steps are needed to implement FIR filter Step 1:

To simulate the block, click on Simulation icon.

Step 2:

Select simulation time (i.e. 1000).

Step 3:

Click on start simulation.

Step 4:

Double click on scopes.

Step 5:

Click properties to change the number of axis displayed and the time range value (X-axis)

Step 6:

Use Data history to control, how many values are stored and displayed on the scope

Step 7:

Click auto scale to configure the display to the correct axis values

Step 8:

Right click on the Y-axis to set its value

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Step 9:

Click on play to see response of signals on scope.

•

Click properties to change the number of axis displayed and the time range value (X-axis)

•

Use Data history to control how many values are stored and displayed on the scope

•

Click autoscale to quickly let the tools configure the display to the correct axis values Right click on the Y-axis to set its value

•

An error will be reported regarding the filter latency: Error reported by S-function 'xlfir' in block 'filter1/FIR': To use a core, latency must be increased to at least 13. Behaviour of the configured block can be simulated. It is not possible to target it in to hardware as no synthesizable filter code is provided by FDA Tool Note: At this point, you need to re-open the FIR Filter parameters and set the latency to 13 as specified in the Error Message.

11.4 Generate, Synthesize, and Place & Route Step 1:

Open the FIR filter Blockset, and verify that all the parameters are set as follows.

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Step 2:

Select the SPARTAN-III family, the XC3S400-5PQ208 device, XST and generate the toplevel VHDL code with the System Generator icon

Step 3:

Open Project Navigator by double-clicking the filter1.npl file in Windows Explorer

Step 4:

Synthesize and Implement the design.

Step 5:

Now, go back to the Simulink filter design example, and decrease the coefficient width to Fix8_8.

Step 6:

Rerun Synthesize and Implement in the Project Navigator.

Step 7: Download Design into FPGA and follow following procedure to verify desired filter on FPGA. • Download the bit file in the Device. • Give input (Square/sin) to ADC using connector • Using PR2/PR3/PR4 we can adjust the magnitude of input wave. • Set the frequency of input using PR1 to 4 KHz. Then start decreasing it. Initially you will • get output same as input. As you go below 3 kHz attenuation starts. • Below 1 KHz the output will attenuate almost to zero and you will see a DC value with high frequency noise. • If you increase value of input frequency above Nyquist criteria (15 kHz) then you will see aliasing effect (you’ll see low frequency waveform at output).

11.5 Conclusion After this lab you are able to know, • How to select and generate filter coefficients using FDA tool. • How Xilinx system generator can be used to implement DSP applications. • Complete simulation and block parameter selection of Xilinx system generator block set. • Complete MATLAB and ISE design flow. • How to analyse synthesis and implementation report. • How Filter can be verified on FPGA using MECHATRONICS DSP Board.

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11.6 Assignments 1. What is the type of filter used? • Equiripple filter: Most of the filters designed here are equiripple filter. • Equiripple filter mean that in stop band all the lobes will have equal size or we can say equal gain. 2. What is the Order of the filter? • If we have a FIR filter of order 10 it means that it has 10 coefficients. Mathematically it means • Y (n) =a0*x(0-n) +a1*x(1-n) +a2*x(2-n) +………….a9*x(9-n) Since here it has 10 constants this filter is of order10.These constants are called filter coefficients. • Physically it represents number of Mac’s (Multiply and Accumulate) required for implementing this filter. Higher the order higher is number of MAC required. 3. What is the Sampling Frequency? • Sampling frequency implies the rate at which we collect samples from Analog input to process. If we have sampling frequency of 20 KHz it implies that we are collecting 20000 samples per second • The sampling frequency should follow Nyquist Criteria. It states that sampling frequency should be greater than or equal to twice the highest frequency in input signal. 4. What difference does increasing or decreasing the coefficient width make on the filter response? • Decreasing the coefficient width results in less attenuation, and increasing the width steepens the transition and increases the attenuation. 5. What does a Hardware Over-Sampling Rate of 9 tell you about the filter implementation? Why is it set to 9 and not 8? • It specifies the serial implementation of the filter. It will take 9 clock cycles per output. It is 9-bits instead of 8-bits because of the symmetry in the coefficients. With symmetry, samples are added before going through the serial multiplier. • Two 8-bit numbers added together result in a 9-bit output because of the carry out. 6. How many slices are used, and are the timing constraint met?What is the actual clock period? Knowing that you selected the serial implementation, what is the actual filter sample rate?--- slices. Constraints are met. Actual period is xx ns or yyy MHz. Sample rate is yyy/xx = ---MSPS. 7. What impact does decreasing the coefficient width have on the filter size? What would be the impact of decreasing the

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input data width? Decreasing the coefficient width results in a smaller FIR filter. Decreasing the data width impacts the sample rate in serial implementation. The smaller the data, the faster the sample rate. 8. What do you infer by 3 db bandwidth? It is defined as the frequency at which the output signal falls to 0.707 of the input. 9. What is pass band and stop band frequencies? Explain. Pass Band Freq.

Stop Band Frequency Equal Ripples

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LAB 12 Multirate Signal Processing 12.1 Introduction Having discussed the cases of decimation (down sampling by factor D) and interpolation (up sampling by factor I) we now consider the general case of sampling rate conversion by factor I/D. Basically, we can achieve this sampling rate conversion by first performing interpolation by factor I and decimating the output of the interpolator by the factor D. In other words, a sampling rate conversion by the rational factor I/D is accomplished by cascading an interpolator with a decimator. This experiment explains multirate signal processing, how to convert Sampling Rate by rational factor I/D.

12.2 Procedure Step1:

Open the MATLAB command window by double clicking on the MATLAB icon, which is provided on the desktop.

Step2:

Now open the Simulink Library Browser by typing the Simulink at the command prompt (>> Simulink) or clicking on the Simulink library browser.

Step3:

Go to File and open the new model file.

Step4:

Go to Simulink sources and select the signal generator block and drag it into model file. Then go to sinks select the scope and drag into model file.

Step5:

Go to Xilinx blocks set and click on the basic elements. The Simulink library browser looks like below fig.

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Select the Gateway In, Gateway Out, System Generator, up sample, and FIR blocks and drop them into new model file. Then interconnect all the blocks as shown below

Step6:

In the figure there are two Xilinx block sets up-sampler followed by low pass filter. Now you can design the filter as described in the previous lab with the same Specifications. And export the co-efficient to the FIR Xilinx filter block.

Step7:

Now double click on the Up-sampler block. The parameter window will open and select the sampling rate as 2 as shown in figure below.

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Now double click on the FIR block. The parameter window will open and fill the parameters like coefficients with Num and latency should be greater than 14. Click on ok.

. Step8:

Now double click on Gateway In. The parameter window will open and enter the parameters as shown below

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Step9:

Now double click on the signal generator block and select the parameters as shown in below

Step10:

Go to simulation parameters and keep the simulation time as 1000.as shown in below

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Step11:

Run the simulation and observe the output on the scope. It will look like below

Top one is the output and bottom one is the input waveform Step12:

Now double click on the System Generator block. And select the target device and target directory where you want to save your file.

Implementation of Design which is generated by MATLAB in Xilinx ISE tool.

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Step1:

Now open the Xilinx project navigator and go to..>>File >> Open Project. Here you need to specify location at which your generated file is stored.

Step2:

Now add ADC-DAC controller design & generated VHDL/VERILOG core to your project files. Modify ADC-DAC controller according to your application. Instantiate Core, generated by MATLAB as a component in ADC-DAC controller design.

Step3:

Then you have to provide .ucf file (User Constraint file). Right click on VHDL file >> new source >> Implementation Constraint File >> specify constraints for the Design. Note – Refer the user constraint file (UCF) which is attached at the end of this manual.

Step4:

Then go to the processes for the source in the navigator window and double click on the “synthesize”.

Step5:

Then right click on “Implement the design “and click on Run.

Step6:

Then right click on “Generate programming file” and go to properties and then go to the start up options. Select the clock as CCLK or JTAG. The figure below depicts that procedure.

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Step8

Then run “Generate Programming File”. This will generate the bit file.

Step9:

Then go to processes for source window and right click on “Configure device” >> properties >> slave serial / Boundary-scan mode depending upon the selection of clock (CCLK, JTAG clock).

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Step10: Then double click on “Configure device”. Download bitstream into FPGA and follow the procedure to verify desired filter on FPGA. Now you can verify your design by applying sine wave input to any one of the channels and see the output waveform on the CRO. Set the frequency to 60Hz and increase it gradually to cut-off frequency and go beyond the cut-off frequency and observe the output on the CRO. You may notice that if the frequency is increased beyond the cut-off frequency the amplitude will reduce gradually and as you move far away from cut-off frequency the output will become zero. Note: You can vary the sampling frequency of ADC by changing the positions of DIPs IL0, IL1, IL2 (switch1, switch2, switch3) from all OFFs to all ONs. Refer DSP manual.

12.3 Assignments 1. Open the place and route tool and fill the following information • Number of slices _________________________________ • Number of IOBs _________________________________ • Number of GBUFs _________________________________ • Maximum clk frq _________________________________ 2. What should be the cut-off frequency? 3. What will be the effect of change in sampling frequency on the output waveform? 4. What impact does decreasing the coefficient width and input data width on the Filter size 5. What is Decimator, Interpolator & applications of Decimator & Interpolator? 6. What is Sampling Rate Conversion of Digital signal? 7. Advantages & Disadvantages of Sampling Rate Conversion in the Digital Domain.

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LAB 12-A Decimator In Multirate Signal Processing 12-A.1 Introduction The process of reducing the sampling rate by a factor D (Down sampling by D) is called decimation. For that the input sequence is passed through low pass filter first and then down sampled.

12-A.2 Procedure Step 1:

Follow the Step 1 to step 4 given in LAB 7.

Step 5:

Go to Xilinx block set and click on the basic elements. From that select the Gateway In, Gateway Out, System Generator, down sample, and FIR blocks and drop them into new model file. Then interconnect all the blocks are as shown below

Step 6:

In the figure there are two Xilinx block sets, up-sampler followed by low pass filter. Now you design the filter as described in the previous lab with the same specifications. And export the co-efficient to the FIR Xilinx filter block.

Step 7:

Now double click on the down-sampler block. The parameter window will open and select the sampling rate as 2 as shown in fig below.

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Now double click on the FIR block. The parameter window will open and fill the parameters like coefficients with Num and latency should be greater than 14. Click on ok.

. Step 8:

Now double click on Gateway In. The parameter window will open and enter the parameters as shown below

Step 9:

Now double click on the signal generator block and select the parameters as shown.

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. Step 10: Go to simulation parameters and keep the simulation time as 1000 as shown.

Step11: Run the simulation and observe the output on the scope. It will look as shown below.

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Top one is the output and bottom one is the input waveform Step12:

Now double click on the System Generator block. And select the target device and target directory where you want to save your file. Click on Generate.

12-A.3 Running The Design In Xilinx ISE Software Environment Step1:

Now open the Xilinx project navigator and go to >>File >> Open Project. Here you need to specify location at which your generated file has stored.

Step2:

Now add ADC-DAC controller design & generated VHDL/VERILOG core to your project files. Modify ADC-DAC controller according to your application. Instantiate Core, generated by MATLAB as a component in ADC-DAC controller design

Step3:

Then you have to provide .ucf file(User Constraint file). Right click on VHDL file >> new source >> Implementation Constraint File >> specify constraints for the Design. Note – Refer the user constraint file(UCF) which is attached at the end of this manual.

Step4:

Then go to the processes for the source in the navigator window and double click on the “synthesize”.

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Step5:

Then right click on “Implement the design” and click on Run.

Step6:

Then right click on “Generate programming file” and go to properties and then go to the start up options. Select the clock as CCLK or JTAG. The figure below depicts that procedure.

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Step7:

Then run the “Generate programming file”. This will generate the bit file.

Step8:

Then go to processes for source window and right click on “Configure device” >> properties >> slave serial / Boundary-scan mode depending upon the selection of clock (CCLK, JTAG clock).

Step9:

Then double click on “Configure device”. Download bitstream into FPGA and follow the procedure to verify desired filter on FPGA.

Now you can verify your design by applying sine wave input to any one of the channels and see the output waveform on the CRO. Set the frequency to 60Hz and increase it gradually to cut-off frequency and go beyond the cut-off frequency and observe the output on the CRO. You may notice that if the frequency is increased beyond the cut-off frequency the amplitude will reduce gradually and as you move far away from cut-off frequency the output will become zero.

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12-A.4: Assignments 1. Open the place and route tool and fill the following information • Number of slices _______________________________ • Number of IOBs __________________________________ • Number of GBUFs ________________________________ • Maximum clk frq ________________________________ 2. What should be the cut-off frequency? 3. What will be the effect of change in sampling frequency on the output waveform? 4. What impact does decreasing the coefficient width have on the filter size? What would be the impact of decreasing the input data width? 5. Based on the defined specifications, what is the minimum • filter order? 6. What is the multirate signal processing? What is the need to change sampling frequency?

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LAB 12-B Interpolator In Multirate Signal Processing 12-B .1 Introduction Interpolation is the process of up sampling followed by low pass filtering. An increase in the sampling rate by an integer factor of I can be accomplished by interpolating (I-1) new samples between successive values of the signal. We can describe it by other means as a process that preserves the spectral shape of the input signal sequence. Let v (m) denote a sequence with a rate Fy = IFx which is obtained from input sequence by adding (I-1) zeros between successive values of input sequence.

12-B.2 Procedure Step1:

Open the MATLAB command window by double clicking on the MATLAB icon, which is provided on the desktop.

Step2:

Now open the Simulink Library Browser by typing the Simulink at the command prompt (>> Simulink) or clicking on the Simulink library browser.

Step3:

Go to file and open the new model file.

Step4:

Go to Simulink sources and select the signal generator block and drag it into model file. Then go to sinks select the scope and drag into model file.

Step5:

Go to Xilinx block set and click on the basic elements. The Simulink library browser is as shown below

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Select the Gateway In, Gateway Out, System Generator, up sample, and FIR blocks and drop them into new model file. Then interconnect all the blocks as shown below.

Step6:

In the figure there are two Xilinx block sets up-sampler followed by lowpass filter. Now you design the filter as described in the previous lab with the same specifications. And export the co-efficient to the FIR .Xilinx filter block.

Step7:

Now double click on the Up-sampler block. The parameter window will open and select the sampling rate as “2” as shown in the figure below.

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Now double click on the FIR block. The parameter window will open and fill the parameters like coefficients with Num and latency should be greater than 14.Click on ok.

Step8:

Now double click on Gateway In. The parameter window will open and enter the parameters as shown below

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Step9:

Now double click on the signal generator block and select the parameters as shown below

Step10: Go to simulation parameters and keep the simulation time as 1000.as shown in below

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Step11:

Run the simulation and observe the output on the scope. It will look as shown below.

Top one is the output and bottom one is the input waveform Step12: Now double click on the System Generator block and select the target device and target directory where you want to save your file. Click on Generate.

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12-B.3 Implementation of Design which is generated by MATLAB in Xilinx ISE tool. Step1: Now open the Xilinx project navigator and go to >>File >> Open Project. Here you need to specify location at which your generated file is stored. Step2:

Now add ADC-DAC controller design & generated VHDL/VERILOG core to your project files. Modify ADC-DAC controller according to your application. Instantiate Core, generated by MATLAB as a component in ADC-DAC controller design.

Step3:

Then you have to provide .ucf file (User Constraint file). Right click on VHDL file >> new source >> Implementation Constraint File >> specify constraints for the Design.

Step4:

Then right click on “synthesize” and then on “Run”.

Step5:

Then right click on “Implement the design” and click on Run.

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Step6:

Then right click on “Generate programming file” and go to properties and then go to the start up options. Select the clock as CCLK or JTAG. The figure below depicts that procedure.

Step7:

Then run “Generate programming file”. This will generate the bit file.

Step8:

Then go to processes for source window and right click on “Configure device” >> properties >> slave serial / Boundary-scan mode depending upon the selection of clock (CCLK, JTAG clock).

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Step9:

Then double click on “Configure device”. Download bitstream into FPGA and follow the procedure to verify desired filter on FPGA.

Now you can verify your design by applying sine wave input to any one of the channels and see the output waveform on CRO. Set the frequency to 60Hz and increase it gradually to cut-off frequency and go beyond the cut-off frequency and observe the output on CRO. You may notice that if the frequency is increased beyond the cut-off frequency the amplitude will reduce gradually and as you move far away from cut-off frequency the output will become zero. Note: You can vary the ADC sampling frequency by changing the positions of Dipswitches IL1, IL2 (switch1, switch2) from all Off’ to all Ons. Refer Manual of DSP.

12-B.3 Assignments 1. Open the place and route tool and fill the following information • Number of slices consumed __________________________ • Number of IOBs ____________________________________ • Number of GBUFs ____________________________________ • Maximum path delay __________________________________ 2. What impact should occur at the output if you change the coefficient width? 3. View the input and output waveforms simultaneously on the CRO and comment on that? 4. What will be the effect of changing the sampling frequency?

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LAB 13 Analysis of Audio Signal Using Filters 13.1 Introduction Most signals such as speech, biological signals, various communication signals such as audio and video signals, are analog. To process analog signals by digital means, it is first necessary to convert them into digital form. The devices used for this are Analog to Digital converters (ADCs). To convert the processed digital signals into analog form.the device used is D/A converters (DAC – AD7541). After designing different types of filter successfully there is a need of applying filters in application. Audio (music) signal contains many frequencies like voice, tones, and drums. If we use low pass filter and select low frequency from Win amp software, it will show selected range of frequencies and we will listen music of selected frequency. Using different filters we can extract different music frequency signals. In this lab, ADC-DAC interface controller can be verified / implemented in the FPGA using the Xilinx ISE Tool. The input to ADC (Audio Signal) is given through stereo jack. Audio (music) signal contains many frequencies like voice, tones, and drums. If we use low pass filter and select low frequency from Win amp software, it will show selected range of frequencies and we will listen music of selected frequency. Using different filters we can extract different music frequency signals.

13.2 Objective After completing this lab you can go for various audio applications like extracting of some frequencies with the use of filters. Filters limit the bandwidth of the signal. Low pass filter can be designed for all low frequencies .As we know musical signal contains musical effects(bass, voice, treble) that may have higher frequencies all the high frequency effects will be attenuated .We can hear the impact on speakers. Similarly if we use high pass filter that will pass higher frequencies then all the low frequency components will be attenuated. Effect can be easily hear on speakers. If we change frequencies on Winamp software, we can hear different effect on speakers. Similarly if we use bandpass or bandreject filters then as per selected frequency range we can hear effect on speakers.

13.3 Design Description • • • • • •

Five channels of ADC are used, wherein Channel 1 or Channel 2 gets the input from a stereo jack. Output of ADC is then given to FPGA, Conversion Start, ADC clock and channel address signals are generated through FPGA. FPGA receives End of conversion (EOC) from ADC. FPGA will map ADC output directly to DAC input. Digital to Analog converter accepts input from FPGA, converts digital data to Analog signal. Output of DAC is available on the output stereo jack. Design description of all filters is similar as in Labs of filters.

13.4 Procedure Follow the following steps to analyse music system • Follow the filter design steps to design filter. • Instead of giving input from Function generator to ADC use audio output port of PC. • Output of DAC is connected to speakers. • Open Win amp. Run music and set frequencies in Win amp. • As per your filter specification it will attenuate unwanted frequency. • Vary frequencies from Win amp and listen effect on speakers. Step 1:

Start the Xilinx Project Navigator by using the desktop shortcut or by using the Start Æ Programs Æ Xilinx ISE Æ Project Navigator

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Step 2: Step 3:

In the Project Navigator window go on FILE ÆNew projectÆSelect Device. Click on symbol of FPGA device and then right clickÆ Click on new source ÆVHDL module and give name adcdacmodi2ÆDefine portsÆFinish.

Step 4:

Generate the Behavioral VHDL Code for the ADC-DAC interface.

Step 5:

Check syntax, and remove errors if present.

Step 6:

Synthesize the design using XST. Highlight adcdacmodi2.vhd file in the Sources in Project window. To run synthesis, right-click on Synthesize>> Run >> double-click on Synthesize in the Processes for Current Source window. Synthesis will run, and a green check will appear next to Synthesize when it is successfully completed. A yellow exclamation mark indicates that a warning was generated, and a red cross indicates an error was generated. Warnings are OK.

If there are any errors, you can View Synthesis Report by expanding Synthesis, right-click and choose the View option, otherwise continue on to the next step.

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Step 7: Step 8:

Write User Constraint file wherein the FPGA pins are locked as per the Spartan-III hardware. Running the Xilinx Implementation Tools. Once synthesis is complete, you can place and route your design to fit into a Xilinx device (Spartan3- 400k), and you can also get some post place-and-route timing information about the design. This procedure runs you through the basic flow for implementation. Right-click on Implement Design, and choose the Run option, or double left-click on Implement Design.

Right-click on Generate Programming File, and choose the Run option, or double left-click on Generate Programming File. This will generate the Bitstream. Step 9:

Double click on Configure Device to download the bitstream.

Step 10: Instead of giving input from function generator to ADC use audio out port of PC. Connect it to the input stereo jack. Connect output of DAC to speakers via an output stereo jack provided on board. Required control signals of ADC are generated through FPGA. Step 11: Observe and verify all signals on Test Points of Spartan-III Protoboard (Conversion start, End of Conversion, sampling clock).

13.5 Experimental Set up

13.6 Further assignments 1. What frequencies does music contain? 2. Differentiate frequencies ranges of bass, audio, treble? 3. Write down the specifications of ADC and DAC. 4. What is the maximum input frequency? 5. If two more channels of ADC are used, what will be the change in the above code? 6. See the Place and Route report and give the number of i) global buffers, LUTs, and IOBs

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LAB 14 Implementation of Stepper Motor Controller 14.1 Introduction:The stepper motor is an electrical motor, which converts digital electric input into a rotary motion. Stepper Motor is the one that revolves through a fixed angle for each pulse applied to the logic sequences. By controlling pulse rate stepper motor speed can be controlled. Stepper Motor is also called as a Single Stack Variable Reluctance Motor. If the switching is carried out in a sequence, the rotor will rotate with stepped motion. Each coil of stepper motor has a centre tap - a wire coming out from the coil is midway in length between its two terminals. Because of the long length of the wound wire, it has a significant resistance (and inductance). You can identify the centre tap by measuring resistance with a suitable ohm-meter. The resistance from a terminal to the centre tap is half the resistance from the two terminals of a coil. As shown in the figure, the current flowing from the centre tap of winding 1 to terminal A1 causes the top stator pole to be a north pole while the bottom stator pole is a south pole. This attracts the rotor into the position shown. If the power to winding 1 is removed and winding 2 is energised, the rotor will turn 30 degrees, or one step. The motor cross section shown in Figure is of a 30 degree per step permanent magnet or hybrid motor. Motor winding number 1 is distributed between the top and bottom stator pole, while motor winding number 2 is distributed between the left and right motor poles. The rotor is a permanent magnet with 6 poles, 3 south and 3 north, arranged around its circumference.

The switching process can also control the average speed. In this lab, you are shown one way of implementing a Stepper Motor Controller using the Spartan-III protoboard. • Write the functionality for stepper Motor Controller in the Xilinx project navigator. • Synthesize your design with XST. • Take the synthesized design through the Xilinx implementation tools. • Download the bit stream file.

14.2 Objective In this lab, you will be able to • Implement a Stepper Motor Controller in an FPGA and verify it on Mechatronics make protoboard. • Verify & change speed of Stepper Motor by varying input frequency. • Verify & change the direction of rotation of Motor. • Use Spartan-III Protoboard for implementation • Initialize and test Spartan-III Protoboard before using for your application.

14.3 Design Description:The design example in this lab is stepper motor controller which is implemented in FPGA. Stepper Motor speed & Direction of rotation is programmable with the use of DIP switches.

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To rotate the motor continuously, we just apply power to the two windings in sequence. Assuming positive logic, where a 1 means turning on the current through a motor winding, the following two control sequences will spin the motor. Step A1 Coil B1 Coil A2 Coil B2 Coil 1 1 0 0 0 2 0 1 0 0 3 0 0 1 0 4 0 0 0 1 1 1 0 0 0 The sequence above produces the smoothest movement and consumes least power. Step A1 Coil B1 Coil A2 Coil B2 Coil 1 1 1 0 0 2 0 1 1 0 3 0 0 1 1 4 1 0 0 1 1 1 1 0 0 This sequence uses more power and but produces greater torque. The step positions produced by the two sequences above are not the same; as a result, combining the two sequences allows half stepping, with the motor stopping alternately at the positions indicated by one or the other sequence. The combined sequence is as follows. Step 1 2 3 4 5 6 7 8 1

A1 Coil 1 1 0 0 0 0 0 1 1

B1 Coil 0 1 1 1 0 0 0 0 0

A2 Coil 0 0 0 1 1 1 0 0 0

B2 Coil 0 0 0 0 0 1 1 1 0

Specifications of motor • • •

Voltage Rating – 12 V DC Step Angle –1.80. Steps/Revolution-200

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14.4 Procedure Step 1: Step 2:

Step 3: Step 4: Step 5: Step 6:

Start the Xilinx Project Navigator by using the desktop shortcut or by using the Start Æ Programs Æ Xilinx ISE Æ Project Navigator In the Project Navigator window go on FILE ÆNew projectÆSelect Device.

Click on symbol of FPGA device and then right clickÆ Click on new source ÆVHDL module and give name stepper_motor_hsÆDefine portsÆFinish. Generate the Behavioral VHDL Code for the stepper motor controller. Check syntax, and remove errors if present. Synthesize the design using XST. Highlight stepper_motor_test.vhd file in the Sources in Project window. To run synthesis, right-click on Synthesize, and choose the Run option, or double-click on Synthesize in the Processes for Current Source window. Synthesis will run, and a green check will appear next to Synthesize when it is successfully completed. A yellow exclamation mark indicates that a warning was generated, and a red cross indicates an error was generated. Warnings are OK.

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If there are any errors, you can View Synthesis Report by expanding Synthesis, right- click and choose the View option, otherwise continue on to the next step. Step 7: Write User Constraint file wherein the FPGA pins are locked as per the Spartan-II hardware. Step 8: Running the Xilinx Implementation Tools. Once synthesis is complete, you can place and route your design to fit into a Xilinx device (Spartan3 400k), and you can also get some post place-and-route timing information about the design. This procedure runs you through the basic flow for implementation. Right-click on Implement Design, and choose the Run option, or double left-click on Implement Design. Right-click on Generate Programming File, and choose the Run option, or double left-click on Generate Programming File. This will generate the Bitstream. Step 9: Double click on Configure Device to download the bitstream.

Step 10: Connect stepper motor to the protoboard as shown below.

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Step 11: Set the DIP switch IL0 to change the direction of rotation. For clockwise rotation : IL0 = 0. For anticlockwise rotation : IL0 = 1. Step 12: Set the DIP switches IL1 and IL2 to change the speed of motor.

14.5 Experimental Set up:-

14.6 Conclusion: Thus stepper motor is implemented in FPGA for different speeds and the direction of the motor is changed and verified.

14.7 Further assignments 1. What is the hardware created by the functionality written? 2. Open the Place and Route report and fill in the information. • Number of slices consumed:____________________ • Number of IOBs:_____________________________ • Number of GBUFs:___________________________

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LAB 15 USB Controller 15.1 USB USB (Universal Serial Bus) is used for Data transfer with peripherals and has many advantages:• Best way to communicate with many Ð Input Devices (Mouse, Keyboard, Joysticks .etc). • Memory Devices like Disk Drives, Memory Cards …etc. Ð Computer peripherals like, Modems, Printers, Disk drives..etc Ð Other devices like Digital Cameras, MP3 players, Set Top boxes …etc. • USB expansion hubs make the bus simultaneously available to dozens of Device. • USB devices are true plug-n-play i.e. can be plugged in anytime, even when the PC is turned ON.

15.2 USB Interfacing:When you plug into USB, the host goes through a Sign ON sequence. • The host sends a Get Descriptor-Device request to address Zero (all USB device must respond to address Zero when first attached). • The Device responds to the request by sending ID data back to the Host to identify itself. • The Host sends a Set Address request which assigns a unique address to the just attached device. So it may be distinguished from other devices connected to the Bus • The Host sends more Get Descriptor request asking for additional device description.

15.3 USB Interface Devices:USB interface devices are devices which provide interface between a USB bus and a host controller (microprocessor, microcontroller, FPGA …etc). They ease the designer’s job of interfacing their systems to a USB port by taking care of the USB interface and USB protocol. Shown below is a generic block diagram of a USB Interface Device.

USB devices available in a large variety through a large a number of vendors. The device provided on our proto-board is FT245BM from FTDI Inc. The FT245BM is their 2nd generation USB FIFO IC.

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15.4 Features of FT245BM • • • • • • • •

Single Chip USB interface with no external components, on chip firmware (with facility for external EEPROM). Entire USB protocol handled on chip, no USB-specific firmware programming required. Support data transfer rates upto 1MB/sec. Supports USB Bulk or Isochronous data transfer modes. Required device drivers provided free by FTDI. (D2xx Driver). Parallel FIFO on peripheral (local) side for transferring data to/from a peripheral and a host PC, makes it easy to interface to any microcontroller, microprocessor, FPGA via IO ports. Eight bit data bus with 4 wire handshake interface is provided. FIFO Receive Buffer (128 Byte):-Data sent from the USB Host (PC) to FT245 is stored in the FIFO receive buffer which can be read by local host (using RD#). FIFO Transmit Buffer (384 Byte):-Data written into the FIFO by local host (using WR# ) is stored in the FIFO Transmit Buffer. FT245 transmits this data to USB Host (PC).

15.5 General Description of USB-FIFO (FTDI):-To send data from the peripheral to the host computer, simply write the byte wide data into the module when TXE# is low If the (384-byte) transmit buffer fills up or is busy storing the previously written byte, the device keeps TXE# high in order to stop further data from being written until some of the FIFO data has been transferred over USB to the host. TXE# goes high after every byte written. When the host sends data to the peripheral over USB, the device will take RXF# low to let the peripheral know that at least one byte of data is available. The peripheral can read a data byte every time RXF# goes low. RXF# goes high after every byte read.

• • • • • • •

D0 to D7 :- FIFO DATA Bus. RD# :- Enables current FIFO Data Byte on D0-D7 when low. Fetches the next FIFO Data Byte (if available) from the receive FIFO Buffer when RD# goes from low to high WR:- Writes the Data Byte on the D0-D7 into the Transmit FIFO Buffer when WR goes from high to low. TXE#:- When high, do not write data byte into the FIFO. When low, data can be written into the FIFO by strobing WR high then low. RXF#:- When high, do not read data from the FIFO. When low, there is data available in the FIFO which can be read by strobing RD# low high again. USB Drivers Required Drivers and DLL S/W Interface are provided on CD supplied with this proto-board and are also freely downloadable from the FTDI Website.

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15.6 LAB Description After completing this lab, you will be able to • To send data from the peripheral to the Host PC through USB • Host PC send data to the peripheral over USB • Data Transfer at fastest rate

15.7 Design Description Three demonstrations are provided on the CD. They demonstrate data transfer operations (both READ & WRITE ) through USB to/from FPGA. The complete code (software + HDL) is provided on the CD. These codes can be used by students to develop their own applications • Hardware:- It contains one folder, provided with UCF, BIT files. Sample (VHDL) code for downloading purpose. Ð VHDL_xc3s400_PQ208:-(VHDL, UCF, Bit files) • Software:Three folders, it contains software required for data transfer (READ & WRITE operation) through USB (Universal serial bus) to FPGA • counter_read_write:-It contains two folder Ð D2XX_lib (Library File) Ð Read_Write_VC (Software programme) • file-loopback:Ð D2XX_lib (Library File) Ð Read_Write_VC (Software programme) • keyboard_ASCII:Ð D2XX_lib (Library File) Ð Read_Write_VC (Software programme) • counter_read_write: A COUNTER is run in 'C' and fed into an array which in turn is passed into the buffer and finally through FTDI (FT245BM) into FIFO of FPGA (SPARTAN3). When data enters into the FIFO empty flag of FIFO goes down and data is written into FIFO. When FIFO gets full, the full flag gets high and then read operation is performed and data transferred is seen as a counter on LEDs. • File-loopback: Data is sent from file input (of size 16MB in this case).When data enters into the FIFO, empty flag of FIFO goes down and data is written into FIFO. When FIFO gets full, the full flag gets high and then read operation is performed. As reading operation gets over, an output file is created in which data from f1 is poured. This serves as a Loop back operation. Data is written in the FIFO in chunks of 4KB and then read from fifo, till the fifo gets empty and then again same process of writing and reading in chunks of 4KB is done till end of file is reached. • Keyboard_ASCII:Data is input through the keyboard and written into the FIFO and loop back operation is observed. (Corresponding ASCII) value is returned.

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15.8 Procedure:Step 1: Step 2:

Step 3:

Start the Xilinx Project Navigator by using the desktop shortcut or by using the Start Æ Programs Æ Xilinx ISE Æ Project Navigator. In the Project Navigator window go on FILE ÆNew projectÆSelect Device.

Step 4:

Click on symbol of FPGA device and then right clickÆ Click on new source ÆVHDL module and give name usb_main.vhdÆDefine portsÆFinish. Generate the Behavioural VHDL Code for the USB Interface.

Step 5:

Check syntax, and remove errors if present.

Step 6:

Synthesize the design using XST. Highlight usb_main.vhd file in the Sources in Project window. To run synthesis, right-click on Synthesize, and choose the Run option, or double-click on Synthesize in the Processes for Current Source window. Synthesis will run, and a green check will appear next to Synthesize when it is successfully completed. A yellow exclamation mark indicates that a warning was generated, and a red cross indicates an error was generated. Warnings are OK.

Step 7: Step 8:

If there are any errors, you can View Synthesis Report by expanding Synthesis, right-click and choose the View option, otherwise continue on to the next step. Write User Constraint file wherein the FPGA pins are locked as per the Spartan-II hardware. Running the Xilinx Implementation Tools. Once synthesis is complete, you can place and route your design to fit into a Xilinx device (Spartan2 200k), and you can also get some post place-and-route timing information about the design. This procedure runs you through the basic flow for implementation. Right-click on Implement Design, and choose the Run option, or double left-click on Implement Design. Right-click on Generate Programming File, and choose the Run option, or double left-click on Generate Programming File. This will generate the Bitstream.

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Step 9: Make Experimental Set up as shown in Figure below. Step 10: Double click on Configure Device to download the bitstream.(“usb_main.bit”).

Step 11: Open “Software\counter_read_write\Read_Write_VC\Rd_Wr_Chunk.dsw” VC++ project work space.

Step 11: Execute program Observe output.

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15 .9 Experimental Setup

Note-For windows driver installation, refer Operational Manual

15.10 Conclusion USB controller (Interface) is implemented in FPGA for transferring data to/from a peripheral and a host P.C. at up to 1 MB/sec.

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LAB 16 Implementation of 8:1 Multiplexer 16.1 Introduction: The Multiplexer is a combinational circuit that is the most widely used circuit in Digital Design. Multiplexing means transmitting a large number of information units over a smaller number of channels or lines. A Digital Multiplexer is a combinational circuit that selects binary information from one of many input lines and directs it to a single output line. The selection of a particular input line is controlled by a set of selection lines. In this lab, you will learn how to implement an 8:1 Multiplexer using Xilinx ISE Tool. • Write the functionality in the Xilinx project navigator. • Run a functional HDL simulation. • Synthesize your design with XST. • Take the synthesized design through the Xilinx implementation tools. • Download the bit stream file. • Check the performance of your design by applying different inputs and verify the outputs.

16.2 Objectives: In this lab, you will be able to implement the multiplexer in FPGA and verify it on Mechatronics make Protoboard.

16.3 Design Description: For selecting one out of ‘n’ inputs for connection to the output, a set of m select inputs are required. 2m = n (n= Number of inputs, m = Number of select lines) Depending upon the digital code applied at the select inputs one out of 8 data sources is selected & transmitted to a single output Channel. Truth Table of 8:1 Mux: Select Inputs A B C 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1

Output Y I0 I1 I2 I3 I4 I5 I6 I7

16.4 Experimental Set up:

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16.5 Steps to implement the 8:1 multiplexer in the FPGA Step 1: Step 2:

Step 3:

Start the Xilinx Project Navigator by using the desktop shortcut or by using the Start Æ Programs Æ Xilinx ISE Æ Project Navigator. In the Project Navigator window go to FILE ÆNew projectÆSelect Device.

Click on the symbol of FPGA device and then right clickÆ Click on new source ÆVHDL module and give the name 8_1_MultiplexerÆDefine portsÆFinish.

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Step 4:

Generate the Behavioural VHDL Code for the 8_1_Multiplexer.

Step 5: Step 6:

Check syntax, and remove errors if present. Simulate the design using ModelSim. Highlight 8_1_Multiplexer.vhd file in the Sources in Project window. To run the Functional Simulation, Click on the symbol of FPGA device and then right clickÆ Click on new sourceÆClick on test bench waveformÆGive file nameÆSelect entityÆFinishÆGive inputsÆ Click on simulate behavioral model Æsee the output. Click on test bench file. Test bench file will open in main window. Assign all the signals and save File. From the source of progress window. click on Simulate Behavioural Model. ModelSim window will open. Verify your design in wave window by observing behaviour of output signal with respect to input signal. Close the ModelSim window.

Step 7:

Step 8:

Synthesize the design using XST.

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Highlight 8_1_Multiplexer.vhd file in the Sources in Project window. To run synthesis, right-click on Synthesize, and choose the Run option, or double-click on Synthesize in the Processes for Current Source window. Synthesis will run, and a green check will appear next to Synthesize, when it is successfully completed. A yellow exclamation mark indicates that warnings are generated, and a red cross indicates errors are generated. Warnings are OK.

If there are any errors, you can view the error through the console window otherwise continue on to the next step. Step 9: Write User Constraint file (UCF) wherein the FPGA pins are locked as per the hardware. Step 10: Run the Xilinx Implementation Tools.

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Once synthesis is complete, you can place and route your design to fit into a Xilinx device (Spartan-III- 400k), and you can also get post place-and-route timing information about the design. This procedure runs you through the basic flow for implementation. Right-click on Implement Design, and choose the Run option, or double left-click on Implement Design. Right-click on Generate Programming File, and choose the Run option, or double left-click on Generate Programming File. This will generate the Bit stream Step 11: Double click on Configure Device to download the bit stream. Step 12: Apply input through DIP Switches (IL3 to IL10) and select lines are mapped to (IL0 to IL2) output is displayed on LEDs.

16.6 Conclusion:Design of 8:1 Multiplexer is implemented in Protoboard and is verified according to the truth Table.

VHD Code for 8:1 Multiplexer:-

Verilog Code for 8:1 Multiplexer

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux is Port ( I0, I1, I2, I3, I4, I5, I6, I7: in std_logic; sel : in std_logic_vector(3 downto 0); Y : out std_logic); end mux; architecture Behavioral of mux is begin Y <= I0 when sel="000" else I1 when sel="001" else I2 when sel="010" else I3 when sel="011" else I4 when sel="100" else I5 when sel="101" else I6 when sel="110" else I7; end Behavioral;

`timescale 1ns / 1ps module mux8to1(op, inp, sel); output op; input [7:0] inp; input [2:0] sel; assign op = sel[2] ? ( sel[1] ? (sel[0] ? inp[7] : inp[6]) : (sel[0] ? inp[5] : inp[4]) ) : (sel[1] ? (sel[0] ? inp[3] : inp[2]) : (sel[0] ? inp[1] : inp[0])); endmodule

UCF for 8:1 Multiplexer:net sel<0> loc = p141;--(IL0) net sel<1> loc = p140;--(IL1) net sel<2> loc = p139;--(IL2) net I0 loc = p138;--(IL3) net I1 loc = p137;--(IL4) net I2 loc = p135;--(IL5) net I3 loc = p133;--(IL6) net I4 loc = p132;--(IL7) net I5 loc = p131;--(IL8) net I6 loc = p130;--(IL9) net I7 loc = p128;--(IL10) net Y loc = p161;--(OL0)

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16.7 Assignments 1. Design a 16:1 mux using 4:1 mux. 2. Design a 32:1 mux using 16:1 mux and 2:1 mux as basic components. 3. Design a xor Gate using mux. 4. Design a Half adder and Full adder using Mux. 5. Design a customized multiplexer with five input buses [A, B, C, D, E]. Three bit select line [S] decides which input bus should drive 4-bit output bus, according to the table given below (Note- Make proper assumption) S2 S1 S0 T 0 0 0 A 0 0 1 B 0 1 0 A 0 1 1 C 1 0 0 A 1 0 1 D 1 1 0 A 1 1 1 E Note – Refer the user constraint file (UCF) which is attached at the end of this manual.

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LAB 17 Implementation of 2:4 Decoder 17.1 Introduction:Discrete quantities of information are represented in digital systems with binary codes. A binary code of n bits is capable of representing up to 2n distinct elements of the coded information. A Decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2n output lines. Decoder is similar to a Demultiplexer except that there is no data input. The only inputs are the control inputs A and B. In this lab, you will learn how to implement a 2:4 Decoder using Xilinx ISE Tool. • Write the functionality in the Xilinx project navigator. • Run a functional HDL simulation. • Synthesize your design with XST. • Take the synthesized design through the Xilinx implementation tools. • Download the bit stream file. • Check the performance of your design by applying binary inputs and verify the outputs.

17.2 Objectives:In this lab, you will be able to implement the Decoder in FPGA and verify it on Mechatronics make Protoboard.

17.3 Design Description:The Truth Table of 2:4 decoders is as below. Control Lines Output Lines A B Y0 Y1 Y2 0 0 1 0 0 0 1 0 1 0 1 0 0 0 1 1 1 0 0 0 The Block Diagram of 2:4 decoder is as shown below.

Y3 0 0 0 1

17.4 Experimental Set up:-

17.5 Steps to implement the 2:4 Decoder in the FPGA

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Step 1: Start the Xilinx Project Navigator by using the desktop shortcut or by using the Start Æ Programs Æ Xilinx ISE Æ Project Navigator. Step 2: In the Project Navigator window go to FILE ÆNew projectÆSelect Device.

Step 3: Step 4: Step 5: Step 6:

Step 7:

Click on the symbol of FPGA device and then right clickÆ Click on new source ÆVHDL module and give the name 2_4_DecoderÆDefine portsÆFinish. Generate the Behavioral VHDL Code for the 2_4_Decoder. Check syntax, and remove errors if present. Simulate the design using Modelsim. Highlight Decoder_tb.vhd file in the Sources in Project window. To run the Functional Simulation, Click on the symbol of FPGA device and then right clickÆ Click on new sourceÆClick on test bench waveformÆGive file nameÆSelect entityÆFinishÆGive inputsÆ Click on simulate behavioral model Æobserve the output.

Synthesize the design using XST. Highlight 2_4_Decoder.vhd file in the Sources in Project window. To run the synthesis, right-click on Synthesize, and choose the Run option, or double-click on Synthesize in the Processes for Current Source window. Synthesis will run, and a green check will appear

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next to Synthesize when it is successfully completed. A yellow exclamation mark indicates that a warning was generated, and a red cross indicates an error was generated. Warnings are OK.

If there are any errors, you can view the error through the console window otherwise continue on to the next step. Step 8: Step 9:

Write User Constraint file wherein the FPGA pins are locked as per the hardware. Run the Xilinx Implementation Tools. Once synthesis is complete, you can place and route your design to fit into a Xilinx device (Spartan-III 400k), and you can also get some post place-and-route timing information about the design. This procedure runs you through the basic flow for implementation. Right-click on Implement Design, and choose the Run option, or double left-click on Implement Design. Right-click on Generate Programming File, and choose the Run option, or double left-click on Generate Programming File. This will generate the Bit stream

Step 10: Double click on Configure Device to download the bit stream. Step 11: Apply input through DIP Switches (IL0 to IL1) and output is displayed on LEDs.

17.6 Conclusion:Design of 2:4 Decoder is implemented in Protoboard and is verified according to the truth Table.

UCF for 2:4 Decoder:net net net net net net

D_in<0> loc = p141;--(IL0) D_in<1> loc = p140;--(IL1) D_out<0> loc = p161;--(OL0) D_out<1> loc = p172;--(OL1) D_out<2> loc = p156;--(OL2) D_out<3> loc = p171;--(OL3)

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VHDL Code for 2:4 Decoder:-

Verilog Code for 2:4 Decoder:-

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

`timescale 1ns / 1ps module decoer2to4(op, inp); output [3:0] op; input [1:0] inp;

entity Decoder is Port ( D_in :in std_logic_vector(1 downto 0); D_out : out std_logic_vector(3 downto 0)); end Decoder; architecture Behavioral of Decoder begin D_out <= "0001" when D_in = "00" "0010" when D_in = "01" "0100" when D_in = "10" “1000”; end Behavioral;

is else else else

assign (~inp[1]); assign (~inp[1]); assign (inp[1]); assign (inp[1]);

op[0] = (~inp[0]) & op[1] = (inp[0]) & op[2] = (~inp[0]) & op[3] = (inp[0]) &

endmodule

1. Design 3:8 decoder and implement it in FPGA. 2. Design a full adder using 3:8 decoders. 3. Design 4 Bit BCD to Seven-Segment Decoder for common cathode /common anode display. • If the input number is greater than 9 • Don’t care for these inputs. • Indicate the error by displaying a letter “E”. • Compare the simulation result for above cases. Note – Refer the user constraint file(UCF) which is attached at the end of this manual.

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LAB 17-A Implementation of 8:3 Encoder 17-A .1 Introduction:-

An Encoder is a digital circuit that performs the inverse operation of a decoder. An Encoder has 2n input lines and n output lines. The output lines generate the binary code corresponding to the input value. In this lab, you will learn how to implement a 8:3 Encoder using Xilinx ISE Tool. Write the functionality in the Xilinx project navigator. Run a functional HDL simulation. Synthesize your design with XST. Take the synthesized design through the Xilinx implementation tools. Download the bit stream file. Check the performance of your design by applying eight inputs and verify the binary outputs.

17-A.2 Objectives: After completing this lab, you will be able to implement the Encoder in FPGA and verify it on Mechatronics make Protoboard.

17-A.3 Design Description: The Truth Table of 8:3 Encoder is as shown below. Y0 Y1 Y2 Y3 Y4 Y5 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0

Y6 0 0 0 0 0 0 1 0

Y7 0 0 0 0 0 0 0 1

C 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

A 0 1 0 1 0 1 0 1

The Block diagram of the 8:3 Encoder is as below.

17-A.4 Steps to implement the 8:3 Encoder in the FPGA Step 1: Step 2: Step 3: Step 4: Step 5:

Start the Xilinx Project Navigator by using the desktop shortcut or by using the Start Æ Programs Æ Xilinx ISE Æ Project Navigator. In the Project Navigator window go to FILE ÆNew projectÆSelect Device. Click on the symbol of FPGA device and then right clickÆ Click on new source ÆVHDL module and give the name 8_3_EncoderÆDefine portsÆFinish. Generate the Behavioural VHDL Code for the 8_3_Encoder. Check syntax and remove errors if present.

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Step 6:

Simulate the design using ModelSim. Highlight Encoder_tb.vhd file in the Sources in Project window. To run the Functional Simulation, Click on the symbol of FPGA device and then right clickÆ Click on new sourceÆClick on test bench waveformÆGive file nameÆSelect entityÆFinishÆGive inputsÆ Click on simulate behavioural model Æsee the output.

Step 7:

Synthesize the design using XST. Highlight 8_3_Encoder.vhd file in the Sources in Project window. To run the synthesis, right-click on Synthesize, and choose the Run option, or double-click on Synthesize in the Processes for Current Source window. Synthesis will run, and a green check will appear next to Synthesize when it is successfully completed. A yellow exclamation mark indicates

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that a warning was generated, and a red cross indicates an error was generated. Warnings are OK.

If there are any errors, you can view the error through the console window otherwise continue on to the next step. Step 8: Write User Constraint file wherein the FPGA pins are locked as per the hardware. Step 9: Run the Xilinx Implementation Tools. Once synthesis is complete, you can place and route your design to fit into a Xilinx device (Spartan-III 400k), and you can also get some post place-and-route timing information about the design. This procedure runs you through the basic flow for implementation. Right-click on Implement Design, and choose the Run option, or double left-click on Implement Design. Right-click on Generate Programming File, and choose the Run option, or double leftclick on Generate Programming File. This will generate the Bit stream. Step 10: Double click on Configure Device to download the bit stream. Step 11: Apply input through DIP Switches (IL0 to IL7) and output is displayed on LEDs.

17-A.5 Experimental Set up:-

17-A.6 Conclusion:Design of 8:3 Encoder is implemented in Protoboard and is verified according to the truth Table.

17-A.7 Assignments 1. Design 8:3 Priority encoder with Y7 having highest priority. 2. Give applications of encoder.

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LAB 18 Implementation of 8:3 Encoder 18.1 Introduction:-

An Encoder is a digital circuit that performs the inverse operation of a decoder. An Encoder has 2n input lines and n output lines. The output lines generate the binary code corresponding to the input value. In this lab, you will learn how to implement a 8:3 Encoder using Xilinx ISE Tool. • Write the functionality in the Xilinx project navigator. • Run a functional HDL simulation. • Synthesize your design with XST. • Take the synthesized design through the Xilinx implementation tools. • Download the bit stream file. • Check the performance of your design by applying eight inputs and verify the binary outputs.

18.2 Objectives:In this lab, you will be able to implement the Encoder in FPGA and verify it on Mechatronics make Protoboard.

18.3 Design Description:The Truth Table of 8:3 Encoder is as shown below. Y0 Y1 Y2 Y3 Y4 Y5 Y6 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0

Y7 0 0 0 0 0 0 0 1

C 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

A 0 1 0 1 0 1 0 1

The Block diagram of the 8:3 Encoder is as below.

18.4 Experimental Set up:-

18.5 Steps to implement the 8:3 Encoder in the FPGA

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Step 1: Step 2: Step 3: Step 4: Step 5:

Step 6:

Start the Xilinx Project Navigator by using the desktop shortcut or by using the Start Æ Programs Æ Xilinx ISE Æ Project Navigator. In the Project Navigator window go to FILE ÆNew projectÆSelect Device. Click on the symbol of FPGA device and then right clickÆ Click on new source ÆVHDL module and give the name 8_3_EncoderÆDefine portsÆFinish. Generate the Behavioural VHDL Code for the 8_3_Encoder. Check syntax and remove errors if present.

Simulate the design using ModelSim. Highlight Encoder_tb.vhd file in the Sources in Project window. To run the Functional Simulation, Click on the symbol of FPGA device and then right clickÆ Click on new sourceÆClick on test bench waveformÆGive file nameÆSelect entityÆFinishÆGive inputsÆ Click on simulate behavioral model Æobserve the output.

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Step 7:

Synthesize the design using XST. Highlight 8_3_Encoder.vhd file in the Sources in Project window. To run the synthesis, right-click on Synthesize, and choose the Run option, or double-click on Synthesize in the Processes for Current Source window. Synthesis will run, and a green check will appear next to Synthesize when it is successfully completed. A yellow exclamation mark indicates that a warning was generated, and a red cross indicates an error was generated. Warnings are OK.

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If there are any errors, you can view the error through the console window otherwise continue on to the next step. Step 8: Write User Constraint file wherein the FPGA pins are locked as per the hardware. Step 9: Run the Xilinx Implementation Tools. Once synthesis is complete, you can place and route your design to fit into a Xilinx device (Spartan-III 400k), and you can also get some post place-and-route timing information about the design. This procedure runs you through the basic flow for implementation. Right-click on Implement Design, and choose the Run option, or double left-click on Implement Design. Right-click on Generate Programming File, and choose the Run option, or double left-click on Generate Programming File. This will generate the Bit stream. Step 10: Double click on Configure Device to download the bit stream. Step 11: Apply input through DIP Switches (IL0 to IL7) and output is displayed on LEDs.

18.6 Conclusion:Design of 8:3 Encoder is implemented in Protoboard and is verified according to the truth Table.

18.7 Assignments 1. Design 8:3 Priority encoder with Y7 having highest priority 2. Give applications of encoder. Note – Refer the user constraint file(UCF) which is attached at the end of this manual

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LAB 19 Implementation of 2 Bit Comparator 19.1 Introduction:The comparison of two numbers is an operation that determines if one number is greater than, less than or equal to the other number. A magnitude comparator is a combinational circuit that compares two numbers, A and B, and determines their relative magnitudes. The output of the comparison is specified by the three binary outputs that indicates whether A is greater than B (A>B), A is less than B (A
19.2 Objectives:In this lab, you will be able to implement the 2 Bit Comparator in FPGA and verify it on Mechatronics make Protoboards.

19.3 Design Description:A and B are two 2 bit numbers. As the two numbers are binary, the digits are either 0 or 1. So the numbers are equal only when the pairs of the significant digits are equal. In terms of equation, A=B only when X i = 1 Where X i = A I B i + A i’ B i’ To determine as to whether A is greater than B or less than B see the relative magnitudes of pairs of significant digits starting from Most Significant position. If the two digits are equal then we check the digits at lower significant position. This comparison continues till a pair of unequal digits is reached. If corresponding digit of A is 1 and that of B is 0, then A>B and vice versa. Truth Table of Comparator Input Lines A B 00 00 00 01 00 10 00 11 01 00 01 01 01 10 01 11 10 00 10 01 10 10 10 11 11 00 11 01 11 10 11 11

Output Lines A=B A>B A
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A and B are 2 bit numbers which can be applied through switches IL0, IL1, IL2, IL3. Output can be checked on OL0, OL1, and OL2.

19.4 Experimental Set up:-

19.5 Steps to implement the 2 Bit Comparator in the FPGA Step 1:

Start the Xilinx Project Navigator by using the desktop shortcut or by using the Start Æ Programs Æ Xilinx ISE Æ Project Navigator.

Step 2:

In the Project Navigator window go to FILE ÆNew projectÆSelect Device.

Step 3:

Click on the symbol of FPGA device and then right clickÆ Click on new source ÆVHDL module and give the name comparatorÆDefine portsÆFinish.

Step 4:

Generate the Behavioural VHDL Code for the Comparator.

Step 5:

Check syntax and remove errors if present.

Step 6:

Simulate the design using ModelSim. Highlight Comparator_tb.vhd file in the Sources in Project window. To run the Functional Simulation, Click on the symbol of FPGA device and then right clickÆ Click on new sourceÆClick on test bench waveformÆGive file nameÆSelect entityÆFinishÆGive inputsÆ Click on simulate behavioral model Æobserve the output.

Step 7:

Synthesize the design using XST.

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Highlight Comparator.vhd file in the Sources in Project window. To run the synthesis, rightclick on Synthesize, and choose the Run option, or double-click on Synthesize in the Processes for Current Source window. Synthesis will run, and a green check will appear next to Synthesize when it is successfully completed. A yellow exclamation mark indicates that a warning was generated, and a red cross indicates an error was generated. Warnings are OK.

Step 8: Step 9:

If there are any errors, you can view the error through the console window otherwise continue on to the next step. Write User Constraint file wherein the FPGA pins are locked as per the hardware. Running the Xilinx Implementation Tools. Once synthesis is complete, you can place and route your design to fit into a Xilinx device (Spartan-IIII 400k), and you can also get some post place-and-route timing information about the design. This procedure runs you through the basic flow for implementation. Right-click on Implement Design, and choose the Run option, or double left-click on Implement Design.

Right-click on Generate Programming File, and choose the Run option, or double left-click on Generate Programming File. This will generate the Bit stream. Step 10: Double click on Configure Device to download the bit stream. Step 11: Apply input through DIP Switches (IL0 to IL3) and output is displayed on LEDs. Further assignments

1. Design Generalized Comparator using Generic statements in VHDL (Ex. n bit comparator). 2. See the synthesis report and place and route report and observe the hardware. Note – Refer the user constraint file(UCF) which is attached at the end of this manual

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LAB 20 Implementation Of Binary To Gray Code Converter 20.1 Introduction:The availability of a large variety of codes for the same discrete elements of information results in the use of different codes by different digital systems. It is sometimes necessary to use the output of one system as a input to another. A conversion circuit must be inserted between the two systems if each uses different codes for the same information. Thus, a code converter is a circuit that makes the two systems compatible even though each uses a different binary code. To convert from binary code A to binary code B, the input lines must supply the bit combination of elements as specified by code A and the output lines must generate the corresponding bit combination of code B. A combinational circuit performs this transformation by means of logic gates. Sometimes it is convenient to use the Gray code to represent the digital data when it is converted from analog data. The advantage of the Gray code over binary numbers is that only one bit in the code group changes when going from one number to the next. The gray code is used in applications where the normal sequence of binary numbers may produce an error or ambiguity during the transition from one number to the next. In this lab, you will learn how to implement a Binary to Gray Code Converter using Xilinx ISE Tool. • Write the functionality in the Xilinx project navigator. • Run a functional HDL simulation. • Synthesize your design with XST. • Take the synthesized design through the Xilinx implementation tools. • Download the bit stream file. • Check the performance of your design by applying inputs and verify the outputs.

20.2 Objectives:In this lab, you will be able to implement the binary to gray code converter in FPGA and verify it on Mechatronics make Protoboard.

20.3 Design Description:After preparing K maps for all four outputs, simplified equations are G3 = B3. G2 = B2 xor B3. G1 = B1 xor B2. G0 = B0 xor B1.

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20.4 Truth Table for Binary to Gray Code: B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

Binary Inputs B2 B1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1

B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

G3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

Outputs G2 G1 0 0 0 0 0 1 0 1 1 1 1 1 1 0 1 0 1 0 1 0 1 1 1 1 0 1 0 1 0 0 0 0

G0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0

20.5 Experimental Set up:

20.6 Steps to implement the Binary to Gray code converter Step 1: Step 2:

Start the Xilinx Project Navigator by using the desktop shortcut or by using the Start Æ Programs Æ Xilinx ISE Æ Project Navigator. In the Project Navigator window go to FILE ÆNew projectÆSelect Device.

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Step 3: Step 4: Step 5: Step 6:

Step 7:

Click on the symbol of FPGA device and then right clickÆ Click on new source ÆVHDL module and give the name bintograyÆDefine portsÆFinish. Generate the Behavioral VHDL Code for the Bintogray. Check syntax and remove errors if present. Simulate the design using Modelsim. Highlight bintogray_tb.vhd file in the Sources in Project window. To run the Functional Simulation, Click on the symbol of FPGA device and then right clickÆ Click on new sourceÆClick on test bench waveformÆGive file nameÆSelect entityÆFinishÆGive inputsÆ Click on simulate behavioral model Æsee the output.

Synthesize the design using XST. Highlight bintogray.vhd file in the Sources in Project window. To run the synthesis, rightclick on Synthesize, and choose the Run option, or double-click on Synthesize in the Processes for Current Source window. Synthesis will run, and a green check will appear next to Synthesize when it is successfully completed. A yellow exclamation mark indicates that a warning was generated, and a red cross indicates an error was generated. Warnings are OK.

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If there are any errors, you can view the error through the console window otherwise continue on to the next step. Step 8: Step 9:

Write User Constraint file wherein the FPGA pins are locked as per the hardware. Running the Xilinx Implementation Tools. Once synthesis is complete, you can place and route your design to fit into a Xilinx device (Spartan-III 400k), and you can also get some post place-and-route timing information about the design. This procedure runs you through the basic flow for implementation. Right-click on Implement Design, and choose the Run option, or double left-click on Implement Design.

Right-click on Generate Programming File, and choose the Run option, or double left-click on Generate Programming File. This will generate the Bit stream. Step 10: Double click on Configure Device to download the bit stream. Step 11

Apply Binary inputs (B3, B2, B1, B0) through DIP Switches (IL0, IL1, IL2, IL3) and 4 bit Gray Code outputs are observed on Output LEDs (OL0 TO OL3).

20.7 Conclusion:Design of Binary to Gray code converter is implemented in Protoboard and is verified according to the truth Table.

20.8 Assignments 1. Design a gray to binary converter and write the VHDL code to implement it in FPGA. 2. Design controllable Binary to Gray/Gray to Binary converter. 3. List the applications wherein gray code is used. Note – Refer the user constraint file(UCF) which is attached at the end of this manual

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LAB 21 Implementation of T Flip Flop 21.1 Introduction:The T flip-flop is a single input version of the JK flip-flop. It is obtained from the JK flip-flop when both the inputs are tied together. The designation T comes from the ability of the flip flop to “toggle” or complement, its state. Regardless of the present state, the flip-flop complements its output when the clock pulse occurs while input T=’1’. The characteristic table and characteristic equation shows that when T=0, Q(t+1) = Q, that is, the next state is the same as the present state and no change occurs. When T=1, then Q(t+1) = Q’, and the state of the flip-flop is complemented. In this lab, you will learn how to implement a T Flip Flop using Xilinx ISE Tool. • Write the functionality in the Xilinx project navigator. • Run a functional HDL simulation. • Synthesize your design with XST. • Take the synthesized design through the Xilinx implementation tools. • Download the bit stream file. • Check the performance of your design by applying inputs and verify the outputs.

21 2 Objectives:In this lab, you will be able to implement the T Flip Flop in FPGA and verify it on Mechatronics make Protoboard.

21.3 Design Description:Here T and CLK are the input signals and Q is the output signal. Truth Table of T flip-flop:Q 0 0 1 1

T 0 1 0 1

Q(t+1) 0 1 1 0

21.4 Experimental Set up:

21.5 Steps to implement the T Flip Flop Step 1: Start the Xilinx Project Navigator by using the desktop shortcut or by using the Start Æ Programs Æ Xilinx ISE Æ Project Navigator. Step 2: In the Project Navigator window go to FILE ÆNew projectÆSelect Device. Step 3: Click on the symbol of FPGA device and then right clickÆ Click on new source ÆVHDL module and give the name T Flip FlopÆDefine portsÆFinish. Step 4: Generate the Behavioural VHDL Code for the T Flip Flop. Step 5: Check syntax and remove errors if present.

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Step 6:

Simulate the design using ModelSim. Highlight TflipFlop_tb.vhd file in the Sources in Project window. To run the Functional Simulation, Click on the symbol of FPGA device and then right clickÆ Click on new sourceÆClick on test bench waveformÆGive file nameÆSelect entityÆFinishÆGive inputsÆ Click on simulate behavioural model Æobserve the output.

Step 7:

Synthesize the design using XST. Highlight TFLipFlop.vhd file in the Sources in Project window. To run the synthesis, rightclick on Synthesize, and choose the Run option, or double-click on Synthesize in the Processes for Current Source window. Synthesis will run, and a green check will appear next to Synthesize when it is successfully completed. A yellow exclamation mark indicates that a warning was generated, and a red cross indicates an error was generated. Warnings are OK.

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Step 8: Step 9:

If there are any errors, you can view the error through the console window otherwise continue on to the next step. Write User Constraint file wherein the FPGA pins are locked as per the hardware. Running the Xilinx Implementation Tools. Once synthesis is complete, you can place and route your design to fit into a Xilinx device (Spartan-III 400k), and you can also get some post place-and-route timing information about the design. This procedure runs you through the basic flow for implementation. Right-click on Implement Design, and choose the Run option, or double left-click on Implement Design.

Right-click on Generate Programming File, and choose the Run option, or double left-click on Generate Programming File. This will generate the Bit stream. Step 10: Double click on Configure Device to download the bit stream. Step 11: Apply input through DIP Switches (IL0) and output is displayed on LEDs.

21.6 Conclusion Design of T Flip Flop is implemented in Protoboards and is verified according to the truth Table.

21.7 Further assignments 1. Design JK, D and SR flip-flop to implement it in FPGA. 2. Design 3-Bit synchronous counter using component Instantiation (D-Flip Flop/ T Flip Flop). 3. Design 8-bit addressable latch (74Ls259). 4. Give the difference between a latch and a flip-flop. Note – Refer the user constraint file(UCF) which is attached at the end of this manual

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LAB 22 Scrolling Of Data On Seven-Segment Display Using Keyboard. 22.1 Introduction:In this lab we will learn how to interface keyboard, seven-segment display and Input Output LEDs to FPGA using Xilinx ISE Tool. Write the functionality in Xilinx Project Navigator, synthesize the design with XST, and take the synthesized design through the Xilinx implementation tools. Download the bit stream file into FPGA and see the scrolling display using keyboard.

22.2 Objective:In this lab, you will be able to • Use the keyboard, Input / Output LEDs to perform various functions that can be implemented using FPGA. • Observe the output on the display / LEDs.

22.3 Experimental Set up:-

22.4 Procedure:Step 1: Step 2:

Start the Xilinx Project Navigator by using the desktop shortcut or by using the Start ÆPrograms Æ Xilinx ISE Æ Project Navigator. In the Project Navigator window go on FILE ÆNew projectÆSelect Device.

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Step 3: Step 4: Step 5: Step 6:

Click on symbol of FPGA device and then right clickÆ Click on new source ÆVHDL module and give name keydis_scrollÆDefine portsÆFinish. Generate the Behavioral VHDL Code for the scrolling display. Check syntax, and remove errors if present. Synthesize the design using XST. Highlight keydis_scroll.vhd file in the Sources in Project window. To run synthesis Right-click on Synthesize, and choose the Run option, or double-click on Synthesize in the Processes for Current Source window. Synthesis will run, and a green check will appear next to Synthesize when it is successfully completed. A yellow exclamation mark indicates that a warning was generated, and a red cross indicates an error was generated. Warnings are OK.

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Step 7: Step 8:

Step 9:

If there are any errors, you can View Synthesis Report by expanding Synthesis, right-click and choose the View option, otherwise continue on to the next step. Write User Constraint file wherein the FPGA pins are locked as per the hardware. Running the Xilinx Implementation Tools. Once synthesis is complete, you can place and route your design to fit into a Xilinx device (Spartan3 400k), and you can also get some post place-and-route timing information about the design. This procedure runs you through the basic flow for implementation. Right-click on Implement Design, and choose the Run option, or double left-click on Implement Design. Right-click on Generate Programming File, and choose the Run option, or double left-click on Generate Programming File. This will generate the Bitstream. Double click on Configure Device to download the bitstream.

Step 10:

Apply input through SW1 & SW2 switches. Observe input/output LEDs. LEDs should glow with proper brightness.

Step 11:

Observe the scrolling of hexadecimal numbers by pressing respective keys.

To design Scrolling display using keyboard. refer following diagram

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22.5 Assignments 1. Write a code for up down counter and display the result on • Output LEDs. • Seven segment display. 2. Design a circuit that will increment the count from 1 to F only when Key1 is pressed. • Ex – Press Key 1 : 0001 on Output LEDs. • Press Key 1 : 0010 on Output LEDs and so on. 3. Implement Q2. to display results on any one of the seven segments. 4. This lab is for common anode display. What will be the change if you use a common cathode display? Note – Refer the user constraint file (UCF) which is attached at the end of this manual.

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LAB 23 Design Of 4-bit Arithmetic Logic Unit 23.1 Introduction In this lab, Design of 4 bit Arithmetic and Logic Unit can be verified / implemented in the FPGA using the Xilinx ISE Tool. The Arithmetic Logic Unit is the heart of the microprocessor. It is used to perform certain arithmetic operations, such as addition, subtraction etc. and logical operations such as AND, OR, EX-OR, etc. Accumulator Register For arithmetic operations, such as addition, subtraction, etc. and logical operations, such as AND, OR, EX-OR etc, one of the operands is in the accumulator. The result of the operations is also stored in the accumulator.

23.2 Objective In this lab, you will be able to • Observe the logical and arithmetic operation output. • Implement and verify the design using the Mechatronics Make VLSI protoboard.

23.3 Design Description:Below given is the block diagram of 4-bit Arithmetic Logic Unit.

It has four inputs (A, B, Opcode and Enable) and a single output (Out). A and B: 4 bit Binary Data inputs. Opcode: 4 Bit Opcode used to select the operation. Enable: ALU should pass the result to the output bus when enable line is High, and Tri-state the output bus when the Enable line is Low. ALU should use combinational logic to calculate an output based on the four-bit Opcode input. ALU should decode the 4 Bit Opcode according to the table given below Opcode 0001 0010 0011 0100

ALU Operation A+B A–B A Complement A*B

Opcode 0101 0110 0111 1000

ALU Operation A AND B A OR B A NAND B A XOR B

A and B operand can be applied through input switches. Output can be observed on 7 segment Display. Operand A (IL0 to IL3) Operand B (IL4 to IL7) Opcode can be applied through (IL8 to IL11)

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Addition When Opcode is “0001” then Addition is performed. Output of addition as well as the carry generated can be displayed on output LEDs.

Subtraction When Opcode is “0010” then Binary subtraction is performed. Output of subtraction as well as the borrow can be displayed on Output LEDs If operand A is less than operand B (A < B) answer of subtraction is Answer (A - B) = - (2’s complement of final answer)

Multiplication – Multiplication is done by normal shift & adds method.

23.4 Experimental Set up:

23.5 Procedure: Step 1: Start the Xilinx Project Navigator by using the desktop shortcut or by using the Start Æ Programs Æ Xilinx ISE Æ Project Navigator. Step 2:

In the Project Navigator window go on FILE ÆNew projectÆSelect Device.

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Step 3:

Click on symbol of FPGA device and then right clickÆ Click on new source ÆVHDL module and give name ALU_checkÆDefine portsÆFinish.

Step 4:

Generate the Behavioral VHDL Code for the scrolling display.

Step 5:

Check syntax, and remove errors if present.

Step 6:

Synthesize the design using XST. Highlight ALU_check.vhd file in the Sources in Project window. To run synthesis, right-click on Synthesize, and choose the Run Option, or double-click on Synthesize in the Processes for Current Source window. Synthesis will run, and a green check will appear next to Synthesize when it is successfully completed. A yellow exclamation mark indicates that a warning was generated, and a red cross indicates an error was generated. Warnings are OK.

If there are any errors, you can View Synthesis Report by Expanding Synthesis, right-click and choose the View option, otherwise continue on to the next step. Step 7:

Write User Constraint file wherein the FPGA pins are locked as per the hardware.

Step 8:

Running the Xilinx Implementation Tools. Once synthesis is complete, you can place and route your design to fit into a Xilinx device (Spartan3 400k), and you can also get some post place-and-route timing information about the design. This procedure runs you through the basic flow for implementation. Right-click on Implement Design, and choose the Run option, or double left-click on Implement Design. Right-click on Generate Programming File, and choose the Run option, or double left-click on Generate Programming File. This will generate the Bitstream.

Step 9:

Double click on Configure Device to download the bitstream.

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Step 10: Apply operand A, B & Opcode control signal through input switches. Step 11: Observe output of Arithmetic & Logical operation on 7-segment display.

23.6 Conclusion:Design of Arithmetic & logic Unit is implemented in FPGA and is verified according to the truth Table.

23.7 Assignments 1. Design a 6-bit ALU and verify it on the Mechatronics make Protoboard. 2. Whether latches are inferred for this code? If yes, give the number of latches inferred Note – Refer the user constraint file (UCF) which is attached at the end of this manual.

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LAB 24 Temperature Sensing Using ADC-DAC Interfacing. 24.1 Introduction:Most signals such as speech, biological signals, and various communication signals such as audio and video signals are analog. To process analog signals by digital means, it is first necessary to convert them into digital form. The devices used for this are Analog to Digital converters (ADCs). In many cases it is desirable to convert the processed digital signals into analog form. This is done by D/A converters (DACs). In this lab, ADC-DAC interface will be implemented in the FPGA using the Xilinx ISE Tool. The input to the ADC is given through a thermistor circuit. Thermistor is a thermally sensitive resistor whose function is to exhibit a large, predictable and precise change in electrical resistance when subjected to an increase in temperature. In protoboard, Negative Temperature Coefficient (NTC) thermistor is used. NTC thermistor exhibits a decrease in electrical resistance when subjected to an increase in body temperature. Resistance temperature characteristics of an NTC are shown below.

The slope or resistance ratio for thermistor is defined as the ratio of resistance at one temperature (usually 0°C) to the resistance at a second / higher temperature (usually 70°C). Slope or resistance ratio provides an introduction to the concept of rate of change of resistance with temperature and the sensitivity of the resistance of thermistor to temperature change.

24.2 Objective:In this lab, ADC-DAC interfacing is implemented and is verified with the help of a temperature sensor (thermistor). After completing this lab you will be able to observe and verify the characteristics of thermistor using FPGA.

24.3 Design Description:The thermistor used is a Negative Temperature Coefficient thermistor whose resistance decreases as temperature increases. Thermistor resistance at room temperature is 2K. As you go on increasing the temperature of the thermistor, the voltage at the output of DAC will go on decreasing. The output can be observed on a multimeter. Five channels of ADC are used, wherein Channel 1 gets the input from a thermistor circuit. Remaining four channels are used for external analog inputs.

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Output of ADC is then given to FPGA, Conversion Start, ADC clock and channel address signals are generated through FPGA. FPGA receives End of conversion (EOC) from ADC. FPGA will map ADC output directly to DAC input.

Digital to Analog converter accepts input from FPGA, converts digital data to Analog signal. Output of DAC is available on the connector. (Refer connector details given below)

24.5 Procedure:Step 1: Start the Xilinx Project Navigator by using the desktop shortcut or by using the Start Æ Programs Æ Xilinx ISE Æ Project Navigator Step 2: In the Project Navigator window go on FILE ÆNew projectÆSelect Device.

Step 3: Step 4: Step 5: Step 6:

Click on symbol of FPGA device and then right clickÆ Click on new source ÆVHDL module and give name adcdacmodiÆDefine portsÆFinish. Generate the Behavioral VHDL Code for the ADC-DAC interface. Check syntax, and remove errors if present. Synthesize the design using XST. Highlight adcdacmodi.vhd file in the Sources in Project window.

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To run synthesis, right-click on Synthesize, and choose the Run option, or double-click on Synthesize in the Processes for Current Source window. Synthesis will run, and a green check will appear next to Synthesize when it is successfully completed. A yellow exclamation mark indicates that a warning was generated, and a red cross indicates an error was generated. Warnings are OK.

Step 7: Step 8:

If there are any errors, you can View Synthesis Report by expanding Synthesis, right-click and choose the View option, otherwise continue on to the next step. Write User Constraint file wherein the FPGA pins are locked as per the hardware. Running the Xilinx Implementation Tools. Once synthesis is complete, you can place and route your design to fit into a Xilinx device (Spartan3 400K), and you can also get some post place-and-route timing information about the design. This procedure runs you through the basic flow for implementation. Right-click on Implement Design, and choose the Run option, or double left-click on Implement Design.

Step 9:

Right-click on Generate Programming File, and choose the Run option, or double left-click on Generate Programming File. This will generate the Bitstream. Double click on Configure Device to download the bitstream.

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Step 10: Measure the output at DAC_Out of (Vout5). It will be approximately equal to output voltage. Observe it to be decreasing. After some time the output voltage will remain (+/- 10) V. Then go on increasing the temperature of thermistor and simultaneously measure the constant. This is the point where the thermistor has gone into saturation i.e. its resistance has decreased to 0 Ω. Required control signals of ADC are generated through FPGA. Step 11: Observe and verify all signals on Test Points of Protoboard (Conversion start, End of Conversion, sampling clock).

24.6 Assignments 1. Write down the specifications of ADC and DAC. 2. If two more channels of ADC are used, what will be the change in the above code? 3. See the Place and Route report and give the number of global buffers, LUTs, and IOBs. Note – Refer the user constraint file (UCF) which is attached at the end of this manual.

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LAB 25 Design of LCD Controller 25.1 Introduction In this lab, 16 characters X 2-line LCD display is interfaced to the protoboard. The data to be displayed on the LCD can be sent through the FPGA by writing VHDL code using the Xilinx ISE Tool. A Liquid Crystal Display is commonly used in systems where low power consumption is necessary. An LCD display consists of crystal material placed between two plates. The crystal material is arranged between two segments or in the form of a dot matrix. The crystal material passes or blocks the light coming on it; so as to create a display. To display the character, certain segments or dots are driven by square wave pattern, which is supplied by a built in driver. The driver is interfaced with FPGA using signals such as data lines, control signals (RS-Register select, R/W-Read/Write, E-Enable).

25.2 Objective:After completing this lab, you will be able to • Observe data on the LCD display. • Display data in various fashion such as rotating mode, constant display etc.

25.3 Design Description:The LCD display interfaced here is a dot matrix Liquid Crystal Display that displays alphanumeric characters and symbols. Its FEATURES are, 1. Built in Dot Matrix LCD controller. 2. Display data RAM for 80 characters (80 X 8 bits). 3. Internal automatic RESET circuit at power ON. 4. Built in Oscillator circuit. (No external clock required). 5. Wide range of instruction functions.

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Pin

SYMBOL

FUNCTION

1.

Vss

Ground

2.

VDD

+5V Power Supply

3.

VL

Contrast Voltage

4.

RS

Data/Command Register select

5.

R/W

Read/write

6.

E

Enable

7.

D0-D7

Data Lines

8.

+VLED

+5V Backlight Supply Voltage

9.

-VLED

Backlight Ground

Initializing LCD Display:-Before writing any data to LCD or reading from it you have to first initialise the LCD using following commands. • Display clear • Character Font • No. of lines–(N=low) • Interface width 8 bits (DL=high) • Address counter Increment (I/D=High) • Display shift OFF (SH=low) • Display OFF (D=low) • Cursor OFF (C=low) • Blink OFF (B=low) After initialization you can write data to LCD or read data from it.

25.4 Experimental set up:-

25.5 Procedure:Step 1: Step 2:

Start the Xilinx Project Navigator by using the desktop shortcut or by using the Start Æ Programs Æ Xilinx ISE Æ Project Navigator. In the Project Navigator window go on FILE ÆNew projectÆSelect Device.

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Step 3: Step 4: Step 5: Step 6:

Click on symbol of FPGA device and then right clickÆ Click on new source ÆVHDL module and give name lcd_component8ÆDefine portsÆFinish. Generate the Behavioral VHDL Code for the LCD Controller. Check syntax, and remove errors if present. Synthesize the design using XST. Highlight lcd_controller8.vhd file in the Sources in Project window. To run synthesis, right-click on Synthesize, and choose the Run option, or double-click on Synthesize in the Processes for Current Source window. Synthesis will run, and a green check will appear next to Synthesize when it is successfully completed. A yellow exclamation mark indicates that a warning was generated, and a red cross indicates an error was generated. Warnings are OK.

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If there are any errors, you can View Synthesis Report by expanding Synthesis, right-click and choose the View option, otherwise continue on to the next step. Step 7: Write User Constraint file wherein the FPGA pins are locked as per the hardware. Step 8: Running the Xilinx Implementation Tools. Once synthesis is complete, you can place and route your design to fit into a Xilinx device (Spartan3 400K), and you can also get some post place-and-route timing information about the design. This procedure runs you through the basic flow for implementation. Right-click on Implement Design, and choose the Run option, or double left-click on Implement Design. Right-click on Generate Programming File, and choose the Run option, or double left-click on Generate Programming File. This will generate the Bitstream. Step 9: Double click on Configure Device to download the bitstream.

Step 10: Observe the data displayed on LCD. You can see BITMAPPER in the first row Cnt – XX A free running counter in the second row.

25.6 Assignments 1. Design LCD Controller to display the name of your college. 2. Do a scrolling display on the LCD. 3. How will you reduce the delay that has been introduced in the counter of the given functionality? 4. Design a calculator and display the result on LCD. Note – Refer the user constraint file (UCF) which is attached at the end of this manual.

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LAB 26 Lift Controller 26.1 Introduction:In this lab, an elevator is designed for a three storied building using the system controller approach. The goal of this lab is to learn more of the capabilities of VHDL and the Xilinx tool as well as to learn how to debug and build larger Digital design systems. Figure below shows the block diagram of Lift Controller.

First we shall try to understand the concept of finite state machines (FSM) in brief. • In layman’s terms all circuits or devices that go through a number of finite distinct states can be classified as FSM. • The best possible example that can be illustrated is that of a counter. Since the counter traverses a number of states before reaching its original state. • In FSM we see that the circuit in each distinct state has a distinct number of outputs.

• •

The generalized block diagram of FSM is shown above. In the above figure we observe that the next state not only depends on the circuit inputs but the present state also. Ð We have conveniently divided the FSM into three parts for the simplicity of understanding. Ð The next state logic decides which state the FSM will traverse depending on the present state and the circuit inputs (x). Ð The state register basically shows the clock dependency of the circuit i.e. the next state will be the present state only on the clock edge. Ð The output logic will determine the outputs at their respective states. Ð An example of the above figure is shown below. This figure is called a state diagram.

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o

• • •

We observe that for the FSM to go from state s0 to s1 a particular input has to be ‘1’ else it stays at s0 (next state logic). Also at every state there is an output defined e.g. at s1 the o/p is ‘0’ (output logic). Similarly for others we can understand that for the states to change certain conditions must be satisfied and that every state has its own set of outputs. Before the students start coding FSM they should realize that FSM is not the only way of making a circuit but it is just a way of representing an idea in a well-organized and structured manner. Thus any circuit that can be constructed using FSM can also be constructed using regular VHDL coding techniques.

26.2 VHDL Coding • • •

We have divided our explanation of FSM in three parts, same goes for our coding practice. Each part is coded in a separate process. A generalized form is shown below P1 : process (state) COMBINATIONAL PROCESS begin input combinational logic ( next state combinational logic ) end; P2 : process (clock, reset) CLOCKED PROCESS begin next state assignment end; P3 : process ( state ) OUTPUT PROCESS begin output logic end;

26.3 Objective After completing this lab, you will be able to tackle medium level projects involving FSM. Students can develop an idea of how to go about designing circuits involving FSM.

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26.4 Procedure Step 1: Step 2:

Start the Xilinx Project Navigator by using the desktop shortcut or by using theStart Æ Programs Æ Xilinx ISE Æ Project Navigator. In the Project Navigator window go on FILE ÆNew projectÆSelect Device.

Step 3: Click on symbol of FPGA device and then right clickÆ Click on new source ÆVHDL module and give name lift controllerÆDefine portsÆFinish. Step 4: Generate the Behavioral VHDL Code for the Lift Controller. Step 5: Check syntax, and remove errors if present. Step 6: Synthesize the design using XST. Highlight lift_controller.vhd file in the Sources in Project window. To run synthesis, right-click on Synthesize, and choose the Run option, or double-click on Synthesize in the Processes for Current Source window. Synthesis will run, and a green check will appear next to Synthesize when it is successfully completed. A yellow exclamation mark indicates that a warning was generated, and a red cross indicates an error was generated. Warnings are OK.

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Step 7: Step 8:

Step 9:

If there are any errors, you can View Synthesis Report by expanding Synthesis, right-click and choose the View option, otherwise continue on to the next step. Write User Constraint file wherein the FPGA pins are locked as per the hardware. Running the Xilinx Implementation Tools. Once synthesis is complete, you can place and route your design to fit into a Xilinx device (Spartan3 400K), and you can also get some post place-and-route timing information about the design. This procedure runs you through the basic flow for implementation. Right-click on Implement Design, and choose the Run option, or double left-click on Implement Design. Right-click on Generate Programming File, and choose the Run option, or double left-click on Generate Programming File. This will generate the Bitstream. Double click on Configure Device to download the bitstream.

Step 10: The output can be observed on the seven segment displays as well as the output LEDs.

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26.5 Assignments 1. Can you think of any real life application circuits that involve FSM? 2. Whether your microprocessor is FSM? If yes which states do they traverse? 3. Can you affect the same signal in a particular VHDL code using two FSMs? (Try it out) 4. Why do we specify each and every signal in all state outputs even though they do not change their output value? (Think about its hardware consequence if this practice is not followed). 5. Are latches and registers inferred by the same statement in VHDL? 6. What is Metastabilty in FSM timings? What is its importance as a problem? (Do some research on it) Note – Refer the user constraint file (UCF) which is attached at the end of this manual.

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Table Of Contents Introduction .....................................................................................................................................1 DSP Algorithm Design Flow 1 • • • • • • • • • • • • •

Design using System Generator:............................................................................................................. 1 Algorithm Verification and Implementation Design Flow.......................................................................... 2 Linking the System and FPGA Design Domains ..................................................................................... 2 System Modeling and Design.................................................................................................................. 2 Algorithm Development ........................................................................................................................... 3 Hardware Generation and Simulation ..................................................................................................... 3 Debug and Verification ............................................................................................................................ 3 Implementation of a core generated by MATLAB in Xilinx ISE tool. ........................................................ 4 Understanding the Number System ........................................................................................................ 5 Design Example for FIR Filter ................................................................................................................. 5 STEPS TO IMPLEMENT THE FILTER IN DSP-PROTOBOARD ............................................................ 6 ADC-DAC Controller in VHDL ................................................................................................................. 6 ADC-DAC Controller in Verilog ............................................................................................................... 9

LAB 1 ..............................................................................................................................................17 Generate Waveforms using DAC 17 1.1 Introduction ............................................................................................................................................ 17 1.2 Specifications of DAC AD7541: .............................................................................................................. 17 1.3 Objective ................................................................................................................................................ 18 1.4 Design Description ................................................................................................................................. 18 1.5 Experimental Set up ............................................................................................................................... 18 1.6 Procedure............................................................................................................................................... 18 1.7 Simulate the Design Using ModelSim .................................................................................................... 19 1.8 Synthesize the Design Using XST.......................................................................................................... 21 1.9 Running the Xilinx Implementation Tools ............................................................................................... 22 1.10 Download design into DSP Protoboard ................................................................................................ 23 1.11 Conclusion ........................................................................................................................................... 24

LAB 2 ..............................................................................................................................................26 Verification of Sampling Theorem using ADC-DAC 26 2.1 Introduction ............................................................................................................................................ 26 2.2 Objective ................................................................................................................................................ 26 2.3 Design Description:- ............................................................................................................................... 26 2.4 Experimental Set up:-............................................................................................................................. 27 2.5 Generate, Synthesize, and Place & Route in Xilinx ................................................................................ 30 2.6 For physical verification: ......................................................................................................................... 33 2.7 Assignments........................................................................................................................................... 33

LAB 3 ..............................................................................................................................................34 FIR filter using windowing method 34 3.1 Introduction ............................................................................................................................................ 34 3.2 Objective ................................................................................................................................................ 34 3.3 Procedure............................................................................................................................................... 34 3.4 Assignments........................................................................................................................................... 44

LAB 4 ..............................................................................................................................................45 Design of FIR filter 45 4.1 Introduction ............................................................................................................................................ 45 4.2 Procedure............................................................................................................................................... 45 4.3 Filter Design ........................................................................................................................................... 45 4.4 Simulate the FIR filter in Simulink........................................................................................................... 47 4.5 Generate Synthesize and Place and Route............................................................................................ 49 4.6 Download the bit file in the Device.......................................................................................................... 49 4.7 Assignments........................................................................................................................................... 50

LAB 5 ..............................................................................................................................................51

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Implementation of aliasing effect

51

5.1 Introduction ............................................................................................................................................ 51 5.2 Objective ................................................................................................................................................ 51 5.3 Design Description ................................................................................................................................. 51 5.4 Procedure............................................................................................................................................... 52 5.5 Simulate the Design Using Modelsim ..................................................................................................... 52 5.6 Synthesize the Design Using XST.......................................................................................................... 52 5.7 Running Xilinx Implementation tool ........................................................................................................ 52 5.8 Assignments........................................................................................................................................... 52

LAB 6 ..............................................................................................................................................53 IMPULSE RESPONSE OF GIVEN FILTER 53 6.1 Introduction ............................................................................................................................................ 53 6.2 Design Procedure Using MATLAB: ........................................................................................................ 54 6.3 Pulse Generator ..................................................................................................................................... 54

LAB 7 ..............................................................................................................................................56 Design Of A Bandpass Filter 56 7.1 Procedure............................................................................................................................................... 56 7.2 Assignments........................................................................................................................................... 56

LAB 8 ..............................................................................................................................................57 Design Of A Band Reject Filter 57 8.1 Procedure............................................................................................................................................... 57 8.2 Assignments........................................................................................................................................... 57

LAB 9 ..............................................................................................................................................58 Noise Removal 58 9.1 Noise Removal ....................................................................................................................................... 58 9.2 Hardware Description............................................................................................................................. 58 9.3 Filter Design Procedure using MATLAB ................................................................................................. 58 9.4 Filter Specifications: ............................................................................................................................... 60 9.5 Signal Generator: ................................................................................................................................... 60 9.6 Gateway In ............................................................................................................................................. 61 9.7 FIR Filter Design: ................................................................................................................................... 62 9.8 FDA Tool:-.............................................................................................................................................. 63 9.9 GATEWAY Out....................................................................................................................................... 63

LAB 10 ............................................................................................................................................65 Compiling MATLAB into an FPGA 65 10.1 Introduction .......................................................................................................................................... 65

LAB 11 ............................................................................................................................................70 Design of A High Pass Filter 70 11.1 Introduction .......................................................................................................................................... 70 11.2 Procedure............................................................................................................................................. 70 11.3 Filter Design ......................................................................................................................................... 70 11.4 Generate, Synthesize, and Place & Route ........................................................................................... 75 11.5 Conclusion ........................................................................................................................................... 76 11.6 Assignments......................................................................................................................................... 77

LAB 12 ............................................................................................................................................79 Multirate Signal Processing 79 12.1 Introduction .......................................................................................................................................... 79 12.2 Procedure............................................................................................................................................. 79 12.3 Assignments......................................................................................................................................... 86

LAB 12-A ........................................................................................................................................87 Decimator In Multirate Signal Processing 87 12-A.1 Introduction ....................................................................................................................................... 87

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12-A.2 Procedure ......................................................................................................................................... 87 12-A.3 Running The Design In Xilinx ISE Software Environment ................................................................. 90 12-A.4: Assignments .................................................................................................................................... 93

lab 12-B ..........................................................................................................................................94 Interpolator In Multirate Signal Processing 94 12-B .1 Introduction ...................................................................................................................................... 94 12-B.2 Procedure ......................................................................................................................................... 94 12-B.3 Assignments ................................................................................................................................... 101

LAB 13 ..........................................................................................................................................102 Analysis of Audio Signal Using Filters 102 13.1 Introduction ........................................................................................................................................ 102 13.2 Objective ............................................................................................................................................ 102 13.3 Design Description ............................................................................................................................. 102 13.4 Procedure........................................................................................................................................... 102 13.5 Experimental Set up ........................................................................................................................... 104 13.6 Further assignments........................................................................................................................... 104

LAB 14 ..........................................................................................................................................105 Implementation of Stepper Motor Controller 105 14.1 Introduction:- ...................................................................................................................................... 105 14.2 Objective ............................................................................................................................................ 105 14.3 Design Description:- ........................................................................................................................... 105 14.4 Procedure........................................................................................................................................... 107 14.5 Experimental Set up:- ......................................................................................................................... 109 14.6 Conclusion: - ...................................................................................................................................... 109 14.7 Further assignments........................................................................................................................... 109

LAB 15 ..........................................................................................................................................110 USB Controller 110 15.1 USB.................................................................................................................................................... 110 15.2 USB Interfacing:- ................................................................................................................................ 110 15.3 USB Interface Devices:- ..................................................................................................................... 110 15.4 Features of FT245BM ........................................................................................................................ 111 15.5 General Description of USB-FIFO (FTDI):-......................................................................................... 111 15.6 LAB Description.................................................................................................................................. 112 15.7 Design Description ............................................................................................................................. 112 15.8 Procedure:- ........................................................................................................................................ 113 15 .9 Experimental Setup ........................................................................................................................... 115 15.10 Conclusion ....................................................................................................................................... 115

LAB 16 ..........................................................................................................................................116 Implementation of 8:1 Multiplexer 116 16.1 Introduction: ....................................................................................................................................... 116 16.2 Objectives: ......................................................................................................................................... 116 16.3 Design Description: ............................................................................................................................ 116 16.4 Experimental Set up: .......................................................................................................................... 116 16.5 Steps to implement the 8:1 multiplexer in the FPGA .......................................................................... 117 16.6 Conclusion:- ....................................................................................................................................... 120 VHD Code for 8:1 Multiplexer:-................................................................................................................... 120 UCF for 8:1 Multiplexer:- .................................................................................Error! Bookmark not defined. 16.7 Assignments....................................................................................................................................... 121

LAB 17 ..........................................................................................................................................122 Implementation of 2:4 Decoder 122 17.1 Introduction:- ...................................................................................................................................... 122 17.2 Objectives:- ........................................................................................................................................ 122 17.3 Design Description:- ........................................................................................................................... 122 17.4 Experimental Set up:- ......................................................................................................................... 122 17.5 Steps to implement the 2:4 Decoder in the FPGA .............................................................................. 122

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17.6 Conclusion:- ....................................................................................................................................... 124

LAB 17-A ......................................................................................................................................126 Implementation of 8:3 Encoder 126 17-A .1 Introduction:-.................................................................................................................................. 126 17-A.2 Objectives: ...................................................................................................................................... 126 17-A.3 Design Description:......................................................................................................................... 126 17-A.4 Steps to implement the 8:3 Encoder in the FPGA........................................................................... 126 17-A.5 Experimental Set up:- ..................................................................................................................... 128 17-A.6 Conclusion:-.................................................................................................................................... 128 17-A.7 Assignments ................................................................................................................................... 128

LAB 18 ..........................................................................................................................................129 Implementation of 8:3 Encoder 129 18.1 Introduction:- ...................................................................................................................................... 129 18.2 Objectives:- ........................................................................................................................................ 129 18.3 Design Description:- ........................................................................................................................... 129 18.4 Experimental Set up:- ......................................................................................................................... 129 18.5 Steps to implement the 8:3 Encoder in the FPGA .............................................................................. 129 18.6 Conclusion:- ....................................................................................................................................... 132 18.7 Assignments....................................................................................................................................... 132

LAB 19 ..........................................................................................................................................133 Implementation of 2 Bit Comparator 133 19.1 Introduction:- ...................................................................................................................................... 133 19.2 Objectives:- ........................................................................................................................................ 133 19.3 Design Description:- ........................................................................................................................... 133 19.4 Experimental Set up:- ......................................................................................................................... 134 19.5 Steps to implement the 2 Bit Comparator in the FPGA....................................................................... 134

LAB 20 ..........................................................................................................................................136 Implementation Of Binary To Gray Code Converter 136 20.1 Introduction:- ...................................................................................................................................... 136 20.2 Objectives:- ........................................................................................................................................ 136 20.3 Design Description:- ........................................................................................................................... 136 20.4 Truth Table for Binary to Gray Code:.................................................................................................. 137 20.5 Experimental Set up: .......................................................................................................................... 137 20.6 Steps to implement the Binary to Gray code converter....................................................................... 137 20.7 Conclusion:- ....................................................................................................................................... 139 20.8 Assignments....................................................................................................................................... 139

LAB 21 ..........................................................................................................................................140 Implementation of T Flip Flop 140 21.1 Introduction:- ...................................................................................................................................... 140 21 2 Objectives:- ........................................................................................................................................ 140 21.3 Design Description:- ........................................................................................................................... 140 21.4 Experimental Set up: .......................................................................................................................... 140 21.5 Steps to implement the T Flip Flop ..................................................................................................... 140 21.6 Conclusion ......................................................................................................................................... 142 21.7 Further assignments........................................................................................................................... 142

LAB 22 ..........................................................................................................................................143 Scrolling Of Data On Seven-Segment Display Using Keyboard. 143 22.1 Introduction:- ...................................................................................................................................... 143 22.2 Objective:- .......................................................................................................................................... 143 22.3 Experimental Set up:- ......................................................................................................................... 143 22.4 Procedure:- ........................................................................................................................................ 143 22.5 Assignments....................................................................................................................................... 146

LAB 23 ..........................................................................................................................................147 Design Of 4-bit Arithmetic Logic Unit 147

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23.1 Introduction ........................................................................................................................................ 147 23.2 Objective ............................................................................................................................................ 147 23.3 Design Description:- ........................................................................................................................... 147 23.4 Experimental Set up: .......................................................................................................................... 148 23.5 Procedure:.......................................................................................................................................... 148 23.6 Conclusion:- ....................................................................................................................................... 150 23.7 Assignments....................................................................................................................................... 150

LAB 24 ..........................................................................................................................................151 Temperature Sensing Using ADC-DAC Interfacing. 151 24.1 Introduction:- ...................................................................................................................................... 151 24.2 Objective:- .......................................................................................................................................... 151 24.3 Design Description:- ........................................................................................................................... 151 24.5 Procedure:- ........................................................................................................................................ 152 24.6 Assignments....................................................................................................................................... 154

LAB 25 ..........................................................................................................................................156 Design of LCD Controller 156 25.1 Introduction ........................................................................................................................................ 156 25.2 Objective:- .......................................................................................................................................... 156 25.3 Design Description:- ........................................................................................................................... 156 25.4 Experimental set up:- ......................................................................................................................... 157 25.5 Procedure:- ........................................................................................................................................ 157 25.6 Assignments....................................................................................................................................... 159

LAB 26 ..........................................................................................................................................160 Lift Controller 160 26.1 Introduction:- ...................................................................................................................................... 160 26.2 VHDL Coding ..................................................................................................................................... 161 26.3 Objective ............................................................................................................................................ 161 26.4 Procedure........................................................................................................................................... 162 26.5 Assignments....................................................................................................................................... 164

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