Dsk6713 Techref Reva

TMS320C6713 DSK Technical Reference

2003

DSP Development Systems

TMS320C6713 DSK Technical Reference

506735-0001 Rev. A May 2003

SPECTRUM DIGITAL, INC. 12502 Exchange Drive, Suite 440 Stafford, TX. 77477 Tel: 281.494.4505 Fax: 281.494.5310 [email protected] www.spectrumdigital.com

IMPORTANT NOTICE Spectrum Digital, Inc. reserves the right to make changes to its products or to discontinue any product or service without notice. Customers are advised to obtain the latest version of relevant information to verify that the data being relied on is current before placing orders. Spectrum Digital, Inc. warrants performance of its products and related software to current specifications in accordance with Spectrum Digital’s standard warranty. Testing and other quality control techniques are utilized to the extent deemed necessary to support this warranty. Please be aware that the products described herein are not intended for use in life-support appliances, devices, or systems. Spectrum Digital does not warrant nor is Spectrum Digital liable for the product described herein to be used in other than a development environment. Spectrum Digital, Inc. assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does Spectrum Digital warrant or represent any license, either express or implied, is granted under any patent right, copyright, or other intellectual property right of Spectrum Digital, Inc. covering or relating to any combination, machine, or process in which such Digital Signal Processing development products or services might be or are used. WARNING This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments may cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures necessary to correct this interference.

Copyright © 2003 Spectrum Digital, Inc.

Contents

1

Introduction to the TMS320C6713 DSK Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Provides you with a description of the TMS320C6713 DSK Module, key features, and block diagram. 1.1 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.3 Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.4 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.5 Configuration Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.6 Power Supply ......................................................... 1-6 2 Board Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Describes the operation of the major board components on the TMS320C6713 DSK. 2.1 CPLD (programmable Logic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.1.1 CPLD Overview .................................................... 2-2 2.1.2 CPLD Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.1.3 USER_REG Register .............................................. 2-3 2.1.4 DC_REG Register .................................................. 2-4 2.1.5 Version Register .................................................. 2-4 2.1.6 MISC Register ..................................................... 2-5 2.2 Codec Interface ..................................................... 2-6 2.3 SRAM Interface ..................................................... 2-7 2.4 Flash ROM Interface ................................................ 2-7 2.5 LEDs and DIP Switches .............................................. 2-7 2.6 Daughter Card Interface .............................................. 2-8 3 Physical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Describes the physical layout of the TMS320C6713 DSK and its connectors. 3.1 Board Layout ........................................................ 3-2 3.2 Connector Index .................................................... 3-3 3.3 Expansion Connectors ................................................ 3-3 3.3.1 J4, Memory Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.3.2 J3, Peripheral Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.3.3 J1, HPI Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.4 Audio Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.4.1 J301, Microphone Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.4.2 J303, Audio Line In Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.4.3 J304, Audio Line Out Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.4.4 J302, Headphone Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.5 Power Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.5.1 J5, +5V Main Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.5.2 J6, Optional Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.6. Miscellaneous Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10

A B

3.6.1 J201, USB Port .................................................... 3.6.2 J8, External JTAG Connector ........................................ 3.6.3 JP3, PLD Programming Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 System LEDs ....................................................... 3.8 Reset Switch ....................................................... Schematics .............................................................. Contains the schematics for the TMS320C6713 DSK Mechanical Information .................................................. Contains the mechanical information about the TMS320C6713 DSK

3-10 3-10 3-11 3-11 3-11 A-1 B-1

About This Manual This document describes the board level operations of the TMS320C6713 DSP Starter Kit (DSK) module. The DSK is based on the Texas Instruments TMS320C6713 Digital Signal Processor. The TMS320C6713 DSK is a table top card to allow engineers and software developers to evaluate certain characteristics of the TMS320C6713 DSP to determine if the processor meets the designers application requirements. Evaluators can create software to execute onboard or expand the system in a variety of ways. Notational Conventions

This document uses the following conventions. The TMS320C6713 DSK will sometimes be referred to as the DSK. Program listings, program examples, and interactive displays are shown is a special italic typeface. Here is a sample program listing. equations !rd = !strobe&rw;

Information About Cautions This book may contain cautions. This is an example of a caution statement. A caution statement describes a situation that could potentially damage your software, or hardware, or other equipment. The information in a caution is provided for your protection. Please read each caution carefully. Related Documents Texas Instruments TMS320C67xx DSP CPU Reference Guide Texas Instruments TMS320C67xx DSP Peripherals Reference Guide

Table 1: Manual History Revision A

History Alpha Release

Chapter 1 Introduction to the TMS320C6713 DSK

Chapter One provides a description of the TMS320C6713 DSK along with the key features and a block diagram of the circuit board.

Topic 1.1 1.2 1.3 1.4 1.5 1.6

Page Key Features Functional Overview Basic Operation Memory Map Configuration Switch Settings Power Supply

1-2 1-3 1-4 1-5 1-6 1-6

1-1

Spectrum Digital, Inc 1.1 Key Features

HP OUT

Memory Exp 32

McBSPs MUX

8

8

JTAG

HPI

Ext. JTAG

32

Peripheral Exp

ENDIAN BOOTM 1 BOOTM 0 HPI_EN

Embedded JTAG

USB

PWR

JP4 5V

Voltage Reg

MUX

6713 DSP

Flash

JP2 3.3V

CPLD

JP1 1.26V

Host Port Int

AIC23 Codec

EMIF SDRAM

LINE IN

LINE OUT

MIC IN

The C6713 DSK is a low-cost standalone development platform that enables users to evaluate and develop applications for the TI C67xx DSP family. The DSK also serves as a hardware reference design for the TMS320C6713 DSP. Schematics, logic equations and application notes are available to ease hardware development and reduce time to market.

Config SW3 1 2 3 4

LED

DIP

0123

0123

Figure 1-1, Block Diagram C6713 DSK The DSK comes with a full compliment of on-board devices that suit a wide variety of application environments. Key features include: • A Texas Instruments TMS320C6713 DSP operating at 225 MHz. • An AIC23 stereo codec • 8 Mbytes of synchronous DRAM • 512 Kbytes of non-volatile Flash memory (256 Kbytes usable in default configuration) • 4 user accessible LEDs and DIP switches • Software board configuration through registers implemented in CPLD • Configurable boot options • Standard expansion connectors for daughter card use • JTAG emulation through on-board JTAG emulator with USB host interface or external emulator

1-2

• Single voltage power supply (+5V) TMS320C6713 DSK Module Technical Reference

Spectrum Digital, Inc 1.2 Functional Overview of the TMS320C6713 DSK The DSP on the 6713 DSK interfaces to on-board peripherals through a 32-bit wide EMIF (External Memory InterFace). The SDRAM, Flash and CPLD are all connected to the bus. EMIF signals are also connected daughter card expansion connectors which are used for third party add-in boards. The DSP interfaces to analog audio signals through an on-board AIC23 codec and four 3.5 mm audio jacks (microphone input, line input, line output, and headphone output). The codec can select the microphone or the line input as the active input. The analog output is driven to both the line out (fixed gain) and headphone (adjustable gain) connectors. McBSP0 is used to send commands to the codec control interface while McBSP1 is used for digital audio data. McBSP0 and McBSP1 can be re-routed to the expansion connectors in software. A programmable logic device called a CPLD is used to implement glue logic that ties the board components together. The CPLD has a register based user interface that lets the user configure the board by reading and writing to its registers. The DSK includes 4 LEDs and a 4 position DIP switch as a simple way to provide the user with interactive feedback. Both are accessed by reading and writing to the CPLD registers. An included 5V external power supply is used to power the board. On-board switching voltage regulators provide the +1.26V DSP core voltage and +3.3V I/O supplies. The board is held in reset until these supplies are within operating specifications. Code Composer communicates with the DSK through an embedded JTAG emulator with a USB host interface. The DSK can also be used with an external emulator through the external JTAG connector.

1-3

Spectrum Digital, Inc 1.3 Basic Operation The DSK is designed to work with TI’s Code Composer Studio development environment and ships with a version specifically tailored to work with the board. Code Composer communicates with the board through the on-board JTAG emulator. To start, follow the instructions in the Quick Start Guide to install Code Composer. This process will install all of the necessary development tools, documentation and drivers. After the install is complete, follow these steps to run Code Composer. The DSK must be fully connected to launch the DSK version of Code Composer. 1) Connect the included power supply to the DSK. 2) Connect the DSK to your PC with a standard USB cable (also included). 3) Launch Code Composer from its icon on your desktop. Detailed information about the DSK including a tutorial, examples and reference material is available in the DSK’s help file. You can access the help file through Code Composer’s help menu. It can also be launched directly by double-clicking on the file c6713dsk.hlp in Code Composer’s docs\hlp subdirectory.

1-4

TMS320C6713 DSK Module Technical Reference

Spectrum Digital, Inc 1.4 Memory Map The C67xx family of DSPs has a large byte addressable address space. Program code and data can be placed anywhere in the unified address space. Addresses are always 32-bits wide. The memory map shows the address space of a generic 6713 processor on the left with specific details of how each region is used on the right. By default, the internal memory sits at the beginning of the address space. Portions of the internal memory can be reconfigured in software as L2 cache rather than fixed RAM. The EMIF has 4 separate addressable regions called chip enable spaces (CE0-CE3). The SDRAM occupies CE0 while the Flash and CPLD share CE1. CE2 and CE3 are generally reserved for daughtercards.

Address 0x00000000 0x00030000

0x80000000 0x90000000 0xA0000000 0xB0000000

C67x Family Memory Type

6713 DSK

Internal Memory

Internal Memory

Reserved Space or Peripheral Regs

Reserved or Peripheral

EMIF CE0

SDRAM

EMIF CE1

Flash CPLD

EMIF CE2 EMIF CE3

0x90080000

Daughter Card

Figure 1-2, Memory Map, C6713 DSK

1-5

Spectrum Digital, Inc 1.5 Configuration Switch Settings The DSK has 4 configuration switches that allows users to control the operational state of the DSP when it is released from reset. The configuration switch block is labeled SW3 on the DSK board, next to the reset switch. Configuration switch 1 controls the endianness of the DSP while switches 2 and 3 configure the boot mode that will be used when the DSP starts executing. Configuration switch 4 controls the on-chip multiplexing of HPI and McASP signals brought out to the HPI expansion connector. By default all switches are off which corresponds to EMIF boot (out of 8-bit Flash) in little endian mode and HPI signals on the HPI expansion connector. Table 1: Configuration Switch Settings Switch 1

Switch 2

Switch 3

Switch 4

Configuration Description

Off

Little endian (default)

On

Big endian Off

Off

EMIF boot from 8-bit Flash (default)

Off

On

HPI/Emulation boot

On

Off

32-bit EMIF boot

On

On

16-bit EMIF boot Off

HPI enabled on HPI pins (default)

On

McASP1 enabled on HPI pins

1.6 Power Supply The DSK operates from a single +5V external power supply connected to the main power input (J5). Internally, the +5V input is converted into +1.26V and +3.3V using separate voltage regulators. The +1.26V supply is used for the DSP core while the +3.3V supply is used for the DSP's I/O buffers and all other chips on the board. The power connector is a 2.5mm barrel-type plug. There are three power test points on the DSK at JP1, JP2 and JP4. All I/O current passes through JP2 while all core current passes through JP1. All system current passes through JP4. Normally these jumpers are closed. To measure the current passing through remove the jumpers and connect the pins with a current measuring device such as a multimeter or current probe. It is possible to provide the daughter card with +12V and -12V when the external power connector (J6) is used.

1-6

TMS320C6713 DSK Module Technical Reference

Chapter 2 Board Components

This chapter describes the operation of the major board components on the TMS320C6713 DSK.

Topic 2.1 2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 2.1.6 2.2 2.3 2.4 2.5 2.6

Page CPLD (Programmable Logic) CPLD Overview CPLD Registers USER_REG Register DC_REG Register Version Register MISC Register AIC23 Codec Sychronous DRAM Flash Memory LEDs and DIP Switches Daughter Card Interface

2-2 2-2 2-3 2-3 2-4 2-4 2-5 2-6 2-7 2-7 2-7 2-8

2-1

Spectrum Digital, Inc 2.1 CPLD (Programmable Logic) The C6713 DSK uses an Altera EPM3128TC100-10 Complex Programmable Logic Device (CPLD) device to implement: • 4 Memory-mapped control/status registers that allow software control of various board features. • Control of the daughter card interface and signals. • Assorted "glue" logic that ties the board components together.

2.1.1 CPLD Overview The CPLD logic is used to implement functionality specific to the DSK. Your own hardware designs will likely implement a completely different set of functions or take advantage of the DSPs high level of integration for system design and avoid the use of external logic completely. The CPLD implements simple random logic functions that eliminate the need for additional discrete devices. In particular, the CPLD aggregates the various reset signals coming from the reset button and power supervisors and generates a global reset. The EPM3128TC100-10 is a 3.3V (5V tolerant), 100-pin QFP device that provides 128 macrocells, 80 I/O pins, and a 10 ns pin-to-pin delay. The device is EEPROM-based and is in-system programmable via a dedicated JTAG interface (a 10-pin header on the DSK). The CPLD source files are written in the industry standard VHDL (Hardware Design Language) and included with the DSK.

2-2

TMS320C6713 DSK Module Technical Reference

Spectrum Digital, Inc 2.1.2 CPLD Registers The 4 CPLD memory-mapped registers allows users to control CPLD functions in software. On the 6713 DSK the registers are primarily used to access the LEDs and DIP switches and control the daughter card interface. The registers are mapped into EMIF CE1 data space at address 0x90080000. They appear as 8-bit registers with a simple asynchronous memory interface. The following table gives a high level overview of the CPLD registers and their bit fields: The table below shows the bit definitions for the 4 registers in CPLD. Table 1: CPLD Register Definitions Offset

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0

USER_REG

USR_SW3 R

USR_SW2 R

USR_SW1 R

USR_SW0 R

USR_LED3 R/W 0(Off)

USR_LED2 R/W 0(Off)

USR_LED1 R/W 0(Off)

USR_LED0 R/W 0(Off)

1

DC_REG

DC_DET R

0

DC_STAT1 R

DC_STAT0 R

DC_RST R 0(No reset)

0

DC_CNTL1 R/W 0(low)

DC_CNTL0 R/W 0(low)

4

VERSION

6

MISC

CPLD_VER[3.0] R SCR_5 R/W 0

SCR_4 R/W 0

SCR_3 R/W 0

0 SCR_2 R/W 0

SCR_1 R/W 0

BOARD VERSION[2.0] R FLASH_PAGE R/W 0 (Flash A19=0)

McBSP1 ON/OFF Board R/W 0 (Onboard)

McBSP0 ON/OFF Board R/W 0 (Onboard)

2.1.3 USER_REG Register USER_REG is used to read the state of the 4 DIP switches and turn the 4 LEDs on or off to allow the user to interact with the DSK. The DIP switches are read by reading the top 4 bits of the register and the LEDs are set by writing to the low 4 bits. Table 2: CPLD USER_REG Register Bit

Name

R/W

7

USER_SW3

R

User DIP Switch 3(1 = Off, 0 = On)

Description

6

USER_SW2

R

User DIP Switch 2(1 = Off, 0 = On)

5

USER_SW1

R

User DIP Switch 1(1 = Off, 0 = On)

4

USER_SW0

R

User DIP Switch 0(1 = Off, 0 = On)

3

USER_LED3

R/W

User-defined LED 3 Control (0 = Off, 1 = On)

2

USER_LED2

R/W

User-defined LED 2 Control (0 = Off, 1 = On)

1

USER_LED1

R/W

User-defined LED 1 Control (0 = Off, 1 = On)

0

USER_LED0

R/W

User-defined LED 0 Control (0 = Off, 1 = On)

2-3

Spectrum Digital, Inc 2.1.4 DC_REG Register DC_REG is used to monitor and control the daughter card interface. DC_DET detects the presence of a daughter card. DC_STAT and DC_CNTL provide simple communications with the daughter card through readable status lines and writable control lines. The daughter card is released from reset when the DSP is released from reset. DC_RST can be used to put the card back in reset. Table 3: DC_REG Register Bit

Name

R/W

Description

7

DC_DET

R

Daughter Card Detect (1= Board detected)

6

0

R

Always zero

5

DC_STAT1

R

Daughter Card Status 1 (0=Low, 1 = High)

4

DC_STAT0

R

Daughter Card Status 0 (0=Low, 1 = High)

3

DC_RST

R/W

2

0

R

1

DC_CNTL1

R/W

Daughter Card Control 1(0 = Low, 1 = High)

0

DC_CNTL0

R/W

Daughter Card Control 0(0 = Low, 1 = High)

Daughter Card Reset (0=No Reset, 1 = Reset) Always zero

2.1.5 VERSION Register The VERSION register contains two read only fields that indicate the BOARD and CPLD versions. This register will allow your software to differentiate between production releases of the DSK and account for any variances. This register is not expected to change often, if at all. Table 4: Version Register Bit Definitions

2-4

Bit #

Name

R/W

Description

7

CPLD_VER3

R

Most Significant CPLD Version Bit

6

CPLD_VER2

R

CPLD Version Bit

5

CPLD_VER1

R

CPLD Version Bit

4

CPLD_VER0

R

Least Significant CPLD Version Bit

3

0

R

Always zero

2

DSK_VER2

R

Most Significant DSK Board Version Bit

1

DSK_VER1

R

DSK Board Version Bit

0

DSK_VER0

R

Least Significant DSK Board Version Bit

TMS320C6713 DSK Module Technical Reference

Spectrum Digital, Inc 2.1.6 MISC Register The MISC register is used to provide software control for miscellaneous board functions. On the 6713 DSK, the MISC register controls how auxiliary signals are brought out to the daughter-card connectors. McBSP0 and McBSP1 are usually used as the control and data ports of the on-board AIC23 codec. The power-on state of these bits (both 0s) represents that situation. Set the corresponding McBSP select bit to use the McBSP with a daughter card instead. The Flash and CPLD share CE1 which means that the highest DSP address bit (A21) is used to differentiate between the two. The FLASH_PAGE bit is driven to the Flash as a replacement for that address line which is connected to A19 of the Flash. On a standard DSK, the on-board Flash is not large enough for this bit to be significant. FLASH_PAGE is only useful if the board is re-populated with a larger pin-compatible Flash chip. The scratch bits are unused. They can be set to any value. Table 5: MISC Register Bit

Name

R/W

Description

7

SCRATCH_5

R/W

Scratch bit 5

6

SCRATCH_4

R/W

Scratch bit 4

5

SCRATCH_3

R/W

Scratch bit 3

4

SCRATCH_2

R/W

Scratch bit 2

3

SCRATCH_1

R/W

Scratch bit 1

2

FLASH_PAGE

R/W

Flash address bit 19

1

MCBSP1SEL

R/W

McBSP1 on/off board (0 = on-board, 1 = off-board)

0

MCBSP0SEL

R/W

McBSP0 on/off board (0 = on-board, 1 = off-board)

2-5

Spectrum Digital, Inc 2.2 AIC23 Codec The DSK uses a Texas Instruments AIC23 (part #TLV320AIC23) stereo codec for input and output of audio signals. The codec samples analog signals on the microphone or line inputs and converts them into digital data so it can be processed by the DSP. When the DSP is finished with the data it uses the codec to convert the samples back into analog signals on the line and headphone outputs so the user can hear the output. The codec communicates using two serial channels, one to control the codec’s internal configuration registers and one to send and receive digital audio samples. McBSP0 is used as the unidirectional control channel. It should be programmed to send a 16-bit control word to the AIC23 in SPI format. The top 7 bits of the control word should specify the register to be modified and the lower 9 should contain the register value. The control channel is only used when configuring the codec, it is generally idle when audio data is being transmitted, McBSP1 is used as the bi-directional data channel. All audio data flows through the data channel. Many data formats are supported based on the three variables of sample width, clock signal source and serial data format. The DSK examples generally use a 16-bit sample width with the codec in master mode so it generates the frame sync and bit clocks at the correct sample rate without effort on the DSP side. The preferred serial format is DSP mode which is designed specifically to operate with the McBSP ports on TI DSPs. The codec has a 12MHz system clock. The 12MHz system clock corresponds to USB sample rate mode, named because many USB systems use a 12MHz clock and can use the same clock for both the codec and USB controller. The internal sample rate generate subdivides the 12MHz clock to generate common frequencies such as 48KHz, 44.1KHz and 8KHz. The sample rate is set by the codec’s SAMPLERATE register. The figure below shows the codec interface on the C6713 DSK.

FSX1 CLKX1 TX1

McBSP0 SPI Format

CS SCLK SDIN

Digital

DR2 FSX2 CLKR CLKX FSR2 DX2

McBSP1 DSP Format

DOUT LRCOUT BCLK LRCIN DIN

Control Registers

AIC23 Codec 0 1 2 3 4 5 6 7 8 9 15

LEFTINVOL RIGHTINVOL LEFTHPVOL RIGHTHPVOL ANAPATH DIGPATH POWERDOWN DIGIF SAMPLERATE DIGACT RESET

MIC IN

LINE IN

Analog LINE OUT MIC IN

ADC

LINE IN DAC

LINE OUT HP OUT

HP OUT

Figure 2-1, TMS320C6713 DSK CODEC INTERFACE 2-6

TMS320C6713 DSK Module Technical Reference

Spectrum Digital, Inc 2.3 Synchronous DRAM The DSK uses a 64 megabit synchronous DRAM (SDRAM) on the 32-bit EMIF. The SDRAM is mapped at the beginning of CE0 (address 0x80000000). Total available memory is 8 megabytes. The integrated SDRAM controller is part of the EMIF and must be configured in software for proper operation. The EMIF clock is derived from the PLL settings and should be configured in software at 90MHz. This number is based on an internal PLL clock of 450MHz required to achieve 225 MHz operation with a divisor of 2 and a 90MHz EMIF clock with a divisor of 5. When using SDRAM, the controller must be set up to refresh one row of the memory array every 15.6 microseconds to maintain data integrity. With a 90MHz EMIF clock, this period is 1400 bus cycles.

2.4 Flash Memory Flash is a type of memory which does not lose its contents when the power is turned off. When read it looks like a simple asynchronous read-only memory (ROM). Flash can be erased in large blocks commonly referred to as sectors or pages. Once a block has been erased each word can be programmed once through a special command sequence. After than the entire block must be erased again to change the contents. The DSK uses a 512Kbyte external Flash as a boot option. It is visible at the beginning of CE1 (address 0x90000000). The Flash is wired as a 256K by 16 bit device to support the DSK's 16-bit boot option. However, the software that ships with the DSK treats the Flash as an 8-bit device (ignoring the top 8 bits) to match the 6713's default 8-bit boot mode. In this configuration, only 256Kbytes are readily usable without software changes.

2.5 LEDs and DIP Switches The DSK includes 4 software accessible LEDs (D7-D10) and DIP switches (SW1) that provide the user a simple form of input/output. Both are accessed through the CPLD USER_REG register.

2-7

Spectrum Digital, Inc 2.6 Daughter Card Interface The DSK provides three expansion connectors that can be used to accept plug-in daughter cards. The daughter card allows users to build on their DSK platform to extend its capabilities and provide customer and application specific I/O. The expansion connectors are for memory, peripherals, and the Host Port Interface (HPI) The memory connector provides access to the DSP’s asynchronous EMIF signals to interface with memories and memory mapped devices. It supports byte addressing on 32 bit boundries. The peripheral connector brings out the DSP’s peripheral signals like McBSPs, timers, and clocks. Both connectors provide power and ground to the daughter card The HPI is a high speed interface that can be used to allow multiple DSPs to communicate and cooperate on a given task. The HPI connector brings out the HPI specific control signals. Most of the expansion connector signals are buffered so that the daughter card cannot directly influence the operation of the DSK board. The use of TI low voltage, 5V tolerant buffers, and CBT interface devices allows the use of either +5V or +3.3V devices to be used on the daughter card. Other than the buffering, most daughter card signals are not modified on the board. However, a few daughter card specific control signals like DC_RESET and DC_DET exist and are accessible through the CPLD DC_REG register. The DSK also multiplexes the McBSP0 and McBSP1 of on-board or external use. This function is controlled through the CPLD MISC register.

2-8

TMS320C6713 DSK Module Technical Reference

Chapter 3 Physical Description

This chapter describes the physical layout of the TMS320C6713 DSK and its connectors.

Topic 3.1 3.2 3.3 3.3.1 3.3.2 3.3.3 3.4 3.4.1 3.4.2 3.4.3 3.4.4 3.5 3.5.1 3.5.2 3.6 3.6.1 3.6.2 3.6.3 3.7 3.8

Page Board Layout Connector Index Expansion Connectors J4, Memory Expansion Connector J3, Peripheral Expansion Connector J1, HPI Expansion Connector Audio Connectors J301, Microphone Connector J303, Audio Line In Connector J304, Audio Line Out Connector J302, Headphone Connector Power Connectors J5, +5 Volt Connector J6, Optional Power Connector Miscellaneous Connectors J201, USB Connector J8, External JTAG Connector JP3, PLD Programming Connector System LEDs Reset Switch

3-2 3-3 3-3 3-4 3-5 3-6 3-7 3-7 3-7 3-8 3-8 3-9 3-9 3-9 3-10 3-10 3-10 3-11 3-11 3-11

3-1

Spectrum Digital, Inc 3.1 Board Layout The C6713 DSK is a 8.75 x 4.5 inch (210 x 115 mm.) multi-layer board which is powered by an external +5 volt only power supply. Figure 3-1 shows the layout of the C6713 DSK.

J301

J6

J5

J201

J303

JP3

J304

J302

J3

SW1 D7-10

J4

J1

SW2

J8

Figure 3-1, TMS320C6713 DSK

3-2

TMS320VC6713 DSK Module Technical Reference

Spectrum Digital, Inc 3.2 Connector Index The TMS320C6713 DSK has many connectors which provide the user access to the various signals on the DSK. Table 1: TMS320C6713 DSK Connectors Connector

# Pins

Function

J4

80

Memory

J3

80

Peripheral

J1

80

HPI

J301

3

Microphone

J303

3

Line In

J304

3

Line Out

J303

3

Headphone

J5

2

+5 Volt

J6 *

4

Optional Power Connector

J8

14

External JTAG

J201

5

USB Port

JP3

10

CPLD Programming

SW3

8

DSP Configuration Jumper

Note: “*” Not populated 3.3 Expansion Connectors The TMS320C6713 DSK supports three expansion connectors that follow the Texas Instruments interconnection guidelines. The expansion connector pinouts are described in the following three sections. The three expansion connectors are all 80 pin 0.050 x 0.050 inches low profile connectors from Samtec or AMP. The Samtec SFM Series (surface mount) connectors are designed for high speed interconnections because they have low propagation delay, capacitance, and cross talk. The connectors present a small foot print on the DSK. Each connector includes multiple ground, +5V, and +3.3V power signals so that the daughter card can obtain power directly from the DSK. The peripheral expansion connector additionally provides both +12V and -12V to the daughter card. The recommended mating connector, whose part number is TFM-140-32-S-D-LC, is a surface mount connector that provides a 0.465” mated height. Note: I is on an Input pin O is on an Output pin Z is on a High Impedance pin

3-3

Spectrum Digital, Inc 3.3.1 J4, Memory Expansion Connector Table 2: J4, Memory Expansion Connector Pin

3-4

Signal

I/O

Description

Pin

Signal

I/O

Description

1

5V

Vcc

5V voltage supply pin

3

AEA21

O

EMIF address pin 21

2

5V

Vcc

5V voltage supply pin

4

AEA20

O

EMIF address pin 20

5

AEA19

O

7

AEA17

O

EMIF address pin 19

6

AEA18

O

EMIF address pin 18

EMIF address pin 17

8

AEA16

O

9

AEA15

EMIF address pin 16

O

EMIF address pin 15

10

AEA14

O

11

EMIF address pin 14

GND

Vss

System ground

12

GND

Vss

System ground

13

AEA13

O

EMIF address pin 13

14

AEA12

O

EMIF address pin 12

15

AEA11

O

EMIF address pin 11

16

AEA10

O

EMIF address pin 10

17

AEA9

O

EMIF address pin 9

18

AEA8

O

EMIF address pin 8

19

AEA7

O

EMIF address pin 7

20

AEA6

O

EMIF address pin 6

21

5V

Vcc

5V voltage supply pin

22

5V

Vcc

5V voltage supply pin

23

AEA5

O

EMIF address pin 5

24

AEA4

O

EMIF address pin 4

25

AEA3

O

EMIF address pin 3

26

AEA2

O

EMIF address pin 2

27

ABE3#

O

EMIF byte enable 3

28

ABE2#

O

EMIF byte enable 2

29

ABE1#

O

EMIF byte enable 1

30

ABE0#

O

EMIF byte enable 0

31

GND

Vss

System ground

32

GND

Vss

System ground

33

AED31

I/O

EMIF data pin 31

34

AED30

I/O

EMIF data pin 30

35

AED29

I/O

EMIF data pin 29

36

AED28

I/O

EMIF data pin 28

37

AED27

I/O

EMIF data pin 27

38

AED26

I/O

EMIF data pin 26

39

AED25

I/O

EMIF data pin 25

40

AED24

I/O

EMIF data pin 24

41

3.3V

Vcc

3.3V voltage supply pin

42

3.3V

Vcc

3.3V voltage supply pin

43

AED23

I/O

EMIF data pin 23

44

AED22

I/O

EMIF data pin 22

45

AED21

I/O

EMIF data pin 21

46

AED20

I/O

EMIF data pin 20

47

AED19

I/O

EMIF data pin 19

48

AED18

I/O

EMIF data pin 18

49

AED17

I/O

EMIF data pin 17

50

AED16

I/O

EMIF data pin 16

51

GND

Vss

System ground

52

GND

Vss

System ground

53

AED15

I/O

EMIF data pin 15

54

AED14

I/O

EMIF data pin 14

55

AED13

I/O

EMIF data pin 13

56

AED12

I/O

EMIF data pin 12

57

AED11

I/O

EMIF data pin 11

58

AED10

I/O

EMIF data pin 10

59

AED9

I/O

EMIF data pin 9

60

AED8

I/O

EMIF data pin 8

61

GND

Vss

System ground

62

GND

Vss

System ground

63

AED7

I/O

EMIF data pin 7

64

AED6

I/O

EMIF data pin 6

65

AED5

I/O

EMIF data pin 5

66

AED4

I/O

EMIF data pin 4

67

AED3

I/O

EMIF data pin 3

68

AED2

I/O

EMIF data pin 2

69

AED1

I/O

EMIF data pin 1

70

AED0

I/O

EMIF data pin 0

71

GND

Vss

System ground

72

GND

Vss

System ground

73

AARE#

O

EMIF async read enable

74

AAWE#

O

EMIF async write enable

75

AAOE#

O

EMIF async output enable

76

AARDY

I

EMIF asynchronous ready

77

ACE3#

O

Chip enable 3

78

ACE2#

O

Chip enable 2

79

GND

Vss

System ground

80

GND

Vss

System ground

TMS320VC6713 DSK Module Technical Reference

Spectrum Digital, Inc 3.3.2 J3, Peripheral Expansion Connector Table 3: J3, Peripheral Expansion Connector Pin

Signal

I/O

Description

Pin

Signal

I/O

Description

1

12V

Vcc

12V voltage supply pin

3

GND

Vss

System ground

2

-12V

Vcc

-12V voltage supply pin

4

GND

Vss

5

5V

Vcc

5V voltage supply pin

System ground

6

5V

Vcc

5V voltage supply pin

7

GND

Vss

9

5V

Vcc

System ground

8

GND

Vss

System ground

5V voltage supply pin

10

5V

Vcc

5V voltage supply pin

11

N/C

-

13

N/C

-

No connect

12

N/C

-

No connect

No connect

14

N/C

-

No connect

15

N/C

17

N/C

-

No connect

16

N/C

-

No connect

-

No connect

18

N/C

-

19

No connect

3.3V

Vcc

3.3V voltage supply pin

20

3.3V

Vcc

3.3V voltage supply pin

21

CLKX0

I/O

McBSP0 transmit clock

22

CLKS0

I

McBSP0 clock source

23

FSX0

I/O

McBSP0 transmit frame sync

24

DX0

O

McBSP0 transmit data

25

GND

Vss

System ground

26

GND

Vss

System ground

27

CLKR0

I/O

McBSP0 receive clock

28

N/C

-

No connect

29

FSR0

I/O

McBSP0 receive frame sync

30

DR0

I

McBSP0 receive data

31

GND

Vss

System ground

32

GND

Vss

System ground

33

CLKX1

I/O

McBSP1 transmit clock

34

CLKS1

I

McBSP1 clock source

35

FSX1

I/O

McBSP1 transmit frame sync

36

DX1

O

McBSP1 transmit data

37

GND

Vss

System ground

38

GND

Vss

System ground

39

CLKR1

I/O

McBSP1 receive clock

40

N/C

-

No connect

41

FSR1

I/O

McBSP1 receive frame sync

42

DR1

I

McBSP1 receive data

43

GND

Vss

System ground

44

GND

Vss

System ground

45

TOUT0

O

Timer 0 output

46

TINP0

I

Timer 0 input External interrupt 5

47

N/C

-

No connect

48

EXT_INT5

I

49

TOUT1

O

Timer 1 output

50

TINP1

I

Timer 1 input

51

GND

Vss

System ground

52

GND

Vss

System ground

53

EXT_INT4

I

External interrupt 4

54

N/C

-

No connect

55

N/C

-

No connect

56

N/C

-

No connect

57

N/C

-

No connect

58

N/C

-

No connect

59

RESET

O

System reset

60

N/C

-

No connect

61

GND

Vss

System ground

62

GND

Vss

System ground

63

CNTL1

O

Daughtercard control 1

64

CNTL0

O

Daughtercard control

65

STAT1

I

Daughtercard status 1

66

STAT0

I

Daughtercard status

67

EXT_INT6

I

External interrupt 6

68

EXT_INT7

I

External interrupt 7

69

ACE3#

O

Chip enable 3

70

N/C

-

No connect

71

N/C

-

No connect

72

N/C

-

No connect

73

N/C

-

No connect

74

N/C

-

No connect

75

DC_DET#

Vss

System ground

76

GND

Vss

System ground

77

GND

Vss

System ground

78

ECL KOUT

O

EMIF Clock

79

GND

Vss

System ground

80

GND

Vss

System ground

3-5

Spectrum Digital, Inc 3.3.3 J1, HPI Expansion Connector Table 4: J1, HPI Expansion Connector Pin

3-6

Signal

I/O

Description

Pin

Signal

I/O

Description

1

N/C

-

No connect

2

N/C

-

No connect

3

GND

Vss

System ground

4

HPI_RESETn

I

HPI reset input

5

CLKOUT3

O

Clock output3

6

N/C

-

No connect

7

GND

Vss

System ground

8

GND

Vss

System ground

9

HD1/AXR1[7]

I/O

HPI data 1

10

N/C

-

No connect

11

HD3/AMUTE1

I/O

HPI data 3

12

HD0/AXR1[4]

I/O

HPI data 0

13

HD5/AHCLKX1

I/O

HPI data 5

14

HD2/AFSX1

I/O

HPI data 2

15

HD7/GP0[3]

I/O

HPI data 7

16

HD4/GP0[0]

I/O

HPI data 4

17

GND

Vss

System ground

18

HD6/AHCLKR1

I/O

HPI data 6

19

HD8/GP0[8]

I/O

HPI data 8

20

GND

Vss

System ground

21

HD10/GP0[10]

I/O

HPI data 10

22

HD9/GP0[9]

I/O

HPI data 9

23

HD12/GP0[12]

I/O

HPI data 12

24

HD11/GP0[11]

I/O

HPI data 11

25

HD14/GP0[14]

I/O

HPI data 14

26

HD13/GP0[13]

I/O

HPI data 13

27

GND

Vss

System ground

28

HD15/GP0[15]

I/O

HPI data 15

29

HDS2z/AXR1[5]

I/O

Host data strobe 2

30

GND

Vss

System ground

31

GND

Vss

System ground

32

HASz/ACLKX1

I/O

Host address strobe

33

HDS1z/AXR1[6]

I/O

Host data strobe 1

34

GND

Vss

System ground

35

GND

Vss

System ground

36

HCNTL0/AXR1[3]

I/O

Host control 1

37

HCSz/AXR1[2]

I/O

Host chip select

38

GND

Vss

System ground

39

GND

Vss

System ground

40

HHWIL/AFSR1

I/O

Host half-word select

41

HCNTL1/AXR1[1]

I/O

Host control 1

42

GND

Vss

System ground

43

GND

Vss

System ground

44

HINTz/GP0[1]

I/O

Host interrupt

45

HRDYZ/ACLKR1

I/O

Host Ready

46

GND

Vss

System ground

47

GND

Vss

System ground

48

N/C

-

No connect

49

HR/Wz/AXR1[0]

I/O

Host R/W strobe

50

N/C

-

No connect

51

N/C

-

No connect

52

N/C

-

No connect

53

N/C

-

No connect

54

N/C

-

No connect

55

N/C

-

No connect

56

GND

Vss

System ground

57

N/C

-

No connect

58

N/C

-

No connect

59

N/C

-

No connect

60

N/C

-

No connect

61

GND

Vss

System ground

62

N/C

-

No connect

63

N/C

-

No connect

64

N/C

-

No connect

65

N/C

-

No connect

66

N/C

-

No connect

67

N/C

-

No connect

68

SCL0

I/O

I2C0 Clock System ground

69

N/C

-

No connect

70

GND

Vss

71

GND

Vss

System ground

72

SDA0

I/O

I2C0 Data

73

N/C

-

No connect

74

GND

Vss

System ground

75

GND

Vss

System ground

76

N/C

-

No connect

77

N/C

-

No connect

78

GND

Vss

System ground

79

GND

Vss

System ground

80

CLKOUT2/GP0[2]

I/O

GP I/O 0 bit 2

TMS320VC6713 DSK Module Technical Reference

Spectrum Digital, Inc 3.4 Audio Connectors The C6713 DSK has 4 audio connectors. They are described in the following sections. 3.4.1 J301, Microphone Connector The input is a 3.5 mm. stereo jack. Both inputs are connected to the microphone so it is monaural. The signals on the plug are shown in the figure below.

Ground Microphone In Microphone Bias Figure 3-2, Microphone Stereo Jack 3.4.2 J303, Audio Line In Connector The audio line in is a stereo input. The input connector is a 3.5 mm stereo jack. The signals on the mating plug are shown in the figure below.

Ground Right Line In Left Line In Figure 3-3, Audio Line In Stereo Jack

3-7

Spectrum Digital, Inc 3.4.3 J304, Audio Line Out Connector The audio line out is a stereo output. The output connector is a 3.5 mm stereo jack. The signals on the mating plug are shown in the figure below.

Ground Right Line Out Left Line Out Figure 3-4, Audio Line Out Stereo Jack

3.4.4 J303, Headphone Connector Connector J4 is a headphone/speaker jack. It can drive standard headphones or a high impedance speaker directly. The standard 3.5 mm jack is shown in the figure below.

Ground Right Headphone Left Headphone Figure 3-5, Headphone Jack

3-8

TMS320VC6713 DSK Module Technical Reference

Spectrum Digital, Inc 3.5 Power Connectors The C6713 DSK has 2 power connectors. They are described in the following sections.

3.5.1 J5, +5 Volt Connector Power (+5 volts) is brought onto the TMS320C6713 DSK via the J5 connector. The connector has an outside diameter of 5.5 mm. and an inside diameter of 2.5 mm. The A diagram of J5 is shown below. +5V J5

Ground PC Board

Front View Figure 3-6, TMS320C6713 DSK Power Connector 3.5.2 J6, Optional Power Connector Connector J6 is an optional power connector. It will operate with the standard personal computer power supply. To populate this connector use a Molex #15-24-4041. The table below shows the voltages on the respective pins. Table 5: J6, Optional Power Connector Pin #

Voltage Level

1

+12 Volts

2

-12 Volts

3

Ground

4

+5 Volts

WARNING ! Do not plug into J5 and J6 at the same time.

3-9

Spectrum Digital, Inc 3.6 Miscellaneous Connectors The C6713 DSK has 3 additional connectors to aid the user in developing with this product. They are described in the following sections.

3.6.1 J201, USB Connector Connector J201 provides a Universal Serial Bus (USB) Interface to the embedded JTAG emulation logic on the DSK. This allows for code development and debug without the use of an external emulator. The signals on this connector are shown in the below. Table 6: J201, USB Connector Pin #

USB Signal Name

1

USBVdd

2

D+

3

D-

4

USB Vss

5

Shield

6

Shield

3.6.2 J8, External JTAG Connector The TMS320C6713 DSK is supplied with a 14 pin header interface, J8. This is the standard interface used by JTAG emulators to interface to Texas Instruments DSPs. The pinout for the connector is shown in the figure below.

TMS TDI PD (+3.3V) TDO TCK-RET TCK EMU0

1 3 5 7 9 11 13

2 4 6 8 10 12 14

TRSTGND no pin (key) GND GND GND EMU1

Header Dimensions Pin-to-Pin spacing, 0.100 in. (X,Y) Pin width, 0.025-in. square post Pin length, 0.235-in. nominal

Figure 3-7, J8, JTAG INTERFACE

3-10

TMS320VC6713 DSK Module Technical Reference

Spectrum Digital, Inc 3.6.3 JP3, PLD Programming Connector This connector interfaces to the Altera CPLD, U12. It is used in the in the factory for the programming of the CPLD. This connector is not intended to be used outside the factory.

3.7 System LEDs TheTMS320C6713 DSK has four system light emitting diodes (LEDs). These LEDs indicate various conditions on the DSK. These function of each LED is shown in the table below. Table 7: System LEDs Reference Designator

Color

Function

On Signal State

D4

Green

USB Emulation in use. When External JTAG Emulator is used this LED is off.

D3

Green

+5 Volt present

1

D6

Orange

RESET Active

1

DS201

Green

USB Active, Blinks during USB data transfer

1

1

3.8 Reset Switch There are three resets on the TMS320C6713 DSK. The first reset is the power on reset. This circuit waits until power is within the specified range before releasing the power on reset pin to the TMS320C6713. External sources which control the reset are push button SW2, and the on board embedded USB JTAG emulator.

3-11

Spectrum Digital, Inc

3-12

TMS320VC6713 DSK Module Technical Reference

Appendix A Schematics

This appendix contains the schematics for the TMS320C6713 DSK. Board components with designators over 200 (e.g. DS201, R211) are part of Spectrum Digital’s embedded JTAG emulator and are not included in these schematics.

A-1

A

A-2

9

8

B

1

SH

REV

SH

2

A

B

3

A

10

A

4

A

11

A

REVI SI ON STATUS OF SHEETS

A

REV

SH

REV

5

A

12

A

6

A

13

A

7

B

14

A

APPLI CATI ON

NEXT ASSY

USED ON RLSE

MFG

QA

ENGR- MGR

ENGR

CHK

DWN

DATE

DATE

DATE

DATE

DATE

DATE

DATE

T he T M S 3 2 0 C 6 71 3 D S K d e sign is b as ed o n T M S 3 2 0 C 6 71 3 d e vice d e vice da ta sh e e t S P R S 1 8 6 B a n d e rra ta S P R Z1 7 3 E . T his sch e m a tic is su b je ct to ch a n ge w itho u t n otification. S p e ctru m D ig ita l In c. a ssu m e s n o lia bility for a p plica tio ns a ss ista n ce , cu sto m e r p rod u ct d e sign o r in frin g e m e n t o f p a te n ts d e scrib ed herein.

2 3 -A p ril-2 00 3

A

REV

B E TA

REVI SI ONS DATE

2 3-J an-20 03

APPROVED

D a te:

S ize B

T itle

Tu esd ay, A pril 29, 20 03

50 6 73 2

D ocum e nt N umb er

T M S 3 2 0 C 67 13 D SK

S h eet

1

of

13

S P E C T R U M D IG IT A L IN C O R P O R A T E D

DESCRI PTI ON

R ev B

Spectrum Digital, Inc

TMS320C6713 DSK Module Technical Reference

RES ET PUS HBUTTON

DGND

R 37 1K

R 54 1K

DGND

R 34 NU

DGND

3.3V

R 53 NU

H P I_ R E S E T#

3 .3V

5 6 7 8

R N 19D R N 19E R N 19F R N 19G

S W D IP-4 /S M

SW 1

10K 10K 10K 10K

DGND

10K 10K 10K

R N 19A R N 19B R N 19C

H E AD E R 5X 2

2 4 6 8 10

JP 3

1 3 5 7 9

P A D D LE S W IT C H

4 3 2 1

33

R 83

U S B _ D S P _R S T # S V S _R S T # P U S H B _R S

DGND

3 .3V

4 3

1 2

SW 2

R 36 1K

R 33 NU

C 119 0.1uF

R84 1 0K

P W B _R E V 2 P W B _R E V 1 P W B _R E V 0

2

M M B D 414 8 5 DGND

3

D11

T D [0..3 1]

C O D E C _C LK

T C E 2n T C E 3n TSDW En TSDCASn TSDRASn

T C E 1n

T E A [2..21]

4

S N 7 4A HC 1G 14

U8

T E A 21

IS R _ TC K IS R _ TM S IS R _TD I IS R _ TD O

98 8

62 15 4 73

87 6 36 92 99

29 23 20

97 94 93 35

10 12 90 9 14

40 13 1 00

42 64 41 63 44 45 46 58

TEA2 TEA3 TEA4

TD 0 TD 1 TD 2 TD 3 TD 4 TD 5 TD 6 TD 7

C68 0.1

0 .1

DGND

C38

TC K TM S TDI TD O

C L KIN E M U _R S Tn PONRSn PUSHBRSn H P IR S n

P W B _ RE V 2 P W B _ RE V 1 P W B _ RE V 0

USER_SW 3 USER_SW 2 USER_SW 1 USER_SW 0

D S P _ D C _C S 0 n D S P _ D C _C S 1 n D S P _ D C _W E n D S P _ D C _R E n D S P _ D C _O E n

DSP_CSn C P L D /FL A S H n

D S P _ AD D R 0 D S P _ AD D R 1 D S P _ AD D R 2

DSP_DQ0 DSP_DQ1 DSP_DQ2 DSP_DQ3 DSP_DQ4 DSP_DQ5 DSP_DQ6 DSP_DQ7

3 .3V

39 91 3 18 34 51 66 82 VC C IN T VC C IN T VC C IO VC C IO VC C IO VC C IO VC C IO VC C IO 0 .1

C 69

0 .1

C71

D C _C N T L 0 D C _C N T L 1

BRD_RSn DSP_RSn D S P _ R S n_ LE D

M C B S P _S E L 0 M C B S P _S E L 1

D C _ D BU F _D IR D C _D B U F _O E n D C _C N TL _O E n DC_RES ETn DC_DE Tn

0 .1

C39

57 32 19 17

16 56 61

60 30 48 21

67 47 68 71

80

76 85 84

69 83

52 37 54 79 31

75 81

25 96

0.1

C 70

DGND

0 .1

C40

3 .3V

E P M 31 28A T C 10 0-10

F LAS H _P AG E F LS H _ C E n F LS H _ W E n FL S H _O E n

R SV 0 R SV 1 R SV 2

S P AR E 0 S P AR E 1 S P AR E 2 S P AR E 3

U S E R _L E D 3 U S E R _L E D 2 U S E R _L E D 1 U S E R _L E D 0

C P LD _ C L K _ O U T

C 72 0.1

U 12

D C _S T A T 0 D C _S T A T 1

GND GND GND GND GND GND GND GND GND GND GND GND GND GND 11 26 33 38 43 53 59 65 74 78 86 88 89 95

3 .3V

3 1

F LS H O E n

F LS H W E n

F LS H C E n

F LAS H _P AG E

BRD_R ST# DSP_R ST#

D a te:

S ize B

T itle

R 97 R 98 R 57

R 22 R 24 R 39

D C _S T A T0 D C _S T A T1 F LS H C E n

D SP_R ST# B R D _R S T # F LAS H _ P AG E

D ocum e nt N umb er

GREEN

D7

R 79 15 0

Tu esd ay, A pril 29, 20 03

50 6 73 2

1K

1K

1K

10K

10K

10K

S h eet

GREEN

D8

R 80 1 50

3 .3V

2

GREEN

D9

R 81 150

P U L LU P /D O W N T O K E E P LO G IC IN R E S E T W H E N TH E C P LD IS N O T P R O G R A M M E D .

Y E L LO W

D6

R 78 150

R 23

C P LD _ M CB S P 1_ M U X

T M S 3 2 0 C 67 13 D SK

CPLD

TP15

TP20 TP

TP19 TP

TP16 TP

TP10 TP

U S E R _ LE D 3 U S E R _ LE D 2 U S E R _ LE D 1 U S E R _ LE D 0

TP

C P L D _M CB S P 0 _M U X C P L D _M CB S P 1 _M U X

D C_ E M IFA _DIR D C _E M IF A _OE # D C _C N T L _O E # D C _R S T # D C _D E T

D C _C N T L 0 D C _C N T L 1

D C _S T A T0 D C _S T A T1

R 40

10 K

10K

R 56

D C _E M IF A _OE # C P LD _ M CB S P 0_ M U X

10K

10K

R 35

U S B _D S P _ R S T #

of

13

R ev A

G REEN

D 10

R82 1 50

DGND

3 .3V

Spectrum Digital, Inc

A-3

C LK M O D E 0

D S PIO _3 .3V

D C _T IN P 1 D C _ TO U T 0 D C _ TO U T 1

13 GND

2B1 2B2 2B3 2B4 2B5

DGND

TIN P 1 T OUT 0 T OUT 1

15 16 19 20 23 12

E IN T 4 E IN T 5 E IN T 6 E IN T 7 TIN P 0

1 I

DGND

4

1

50 MHz

GND

CLK

V CC

CT1 0 + 10

O F Fn

U14

3

DGND

O

E X C C E T 10 3U E 1 E M I FILTE R

NU

P la ce a ll P LL e xte rna l co m p one nts a s clo se to t he D SP . A ll P L L externa l com pon en ts m u s t be on a sin gle side of the bo ard . R51

5

8

C 92 0.1

R 50

R17

C 11 3 0.0 1

L5

33

D S P _ C O R E _ C LK

F errite C hip

3.3V

N O -P O P

TP28

D S P _R S T #

N O -P O P O P T ION A L

C22

D S P _ TD I DSP_ TM S DSP_ TCK D S P _T R S T #

DGND

DGND

C 1 14 0 .1

0 .1 D G N D

C 121

2 5 6 9 10

24

S N 74 C B T D 3 3 84P W

2OE

2 A1 2 A2 2 A3 2 A4 2 A5

1OE

V cc 1B1 1B2 1B3 1B4 1B5

M a x im ize the dista nce be tw ee n sw itc hing sign als D G N D and th e PLL extern al c om pone nts .

36 0

R 77

1 14 17 18 21 22

1 A1 1 A2 1 A3 1 A4 1 A5

U21

GN D

A-4 2

D C _E IN T4 D C _E IN T5 D C _E IN T6 D C _E IN T7 D C _T IN P 0

3 4 7 8 11

X DS _4.1 V

A 13

A3 Y11

C4

C5

A7 B7 A6 B6

G2 F2

C13 C2 C1 D2 E3

U 10 E

T M S 3 20 C 67 13 G D P

C LKIN E C LK IN

C LK M O D E 0

P LLH V

TDI TM S TC K TR ST n

T INP 0/A X R0_ 3 T IN P1/A H C LK X 0

C LK O U T 2 /G P 2 CLKO UT3

EMU0 EMU1 EMU2 EMU3 EMU4 EMU5

TD O

T O U T 0/A X R 0 _2 T O U T 1/A X R 0 _4

N MI G P 4 /E X TINT 4/A M U T E IN 1 G P 5 /E X TINT 5/A M U T E IN 0 G P 6 /E X TIN T6 G P 7 /E X TIN T7

RESE Tn

Y 12 D10

D9 B9 D3 B 10 C11 B 12

A8

G1 F1

R25 R26

DSP_EMU0 DSP_EMU1 DSP_EMU2 DSP_EMU3 DSP_EMU4 DSP_EMU5

DSP_TDO

33 33

C LK O U T 2 C LK O U T 3

D a te:

S ize B

T itle

T M S 3 2 0 C 67 13 D SK

Tu esd ay, A pril 29, 20 03

50 6 73 2

D ocum e nt N umb er S h eet

3

of

13

R ev A

Spectrum Digital, Inc

TMS320C6713 DSK Module Technical Reference

TEA2 TEA3 TEA4 TEA5 TEA6 TEA7 TEA8 TEA9 T E A 10 T E A 11 T E A 12 T E A 13 T E A 14 T E A 15 T E A 16 T E A 17 T E A 18 T E A 19 T E A 20 T E A 21

TP 3

TA R D Y

33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33

TP

R N 8H R N 8G R N 8F R N 8E R N 8D R N 8C R N 8B R N8 A R N 9H R N 9G R N 9F R N 9E R N 9D R N 9C R N 9B R N9 A R N 12H R N 12G R N 12F R N 12E

NEAR DSP E A2 E A3 E A4 E A5 E A6 E A7 E A8 E A9 E A1 0 E A1 1 E A1 2 E A1 3 E A1 4 E A1 5 E A1 6 E A1 7 E A1 8 E A1 9 E A2 0 E A2 1 Y6 V7 W7 V8 W8 Y8 V9 Y9 V 10 W 13 V 14 W 14 Y14 W 15 Y15 V 16 Y16 W 17 Y18 U18

J1 7 Y5

T D [0..31 ]

TD 0 TD 1 TD 2 TD 3 TD 4 TD 5 TD 6 TD 7 TD 8 TD 9 TD 1 0 TD 1 1 TD 1 2 TD 1 3 TD 1 4 TD 1 5 TD 1 6 TD 1 7 TD 1 8 TD 1 9 TD 2 0 TD 2 1 TD 2 2 TD 2 3 TD 2 4 TD 2 5 TD 2 6 TD 2 7 TD 2 8 TD 2 9 TD 3 0 TD 3 1 RN 6 A RN 6 B RN 6 C RN 6 D RN 6 E RN 6 F RN 6 G RN 6 H RN 5 A RN 5 B RN 5 C RN 5 D RN 5 E RN 5 F RN 5 G RN 5 H RN 4 A RN 4 B RN 4 C RN 4 D RN 4 E RN 4 F RN 4 G RN 4 H RN 3 A RN 3 B RN 3 C RN 3 D RN 3 E RN 3 F RN 3 G RN 3 H 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 ED 0 ED 1 ED 2 ED 3 ED 4 ED 5 ED 6 ED 7 ED 8 ED 9 ED 10 ED 11 ED 12 ED 13 ED 14 ED 15 ED 16 ED 17 ED 18 ED 19 ED 20 ED 21 ED 22 ED 23 ED 24 ED 25 ED 26 ED 27 ED 28 ED 29 ED 30 ED 31 K18 K19 L1 8 L1 9 M 19 M 20 N18 N19 N20 P18 P20 R19 R20 T18 T20 T19 V4 W4 Y3 V2 V1 U2 U1 U3 T1 T2 R3 R2 P1 P2 P3 N3 T M S 320 C 6 713 G D P

U 10A

E A2 E A3 E A4 E A5 E A6 E A7 E A8 E A9 E A1 0 E A1 1 E A1 2 E A1 3 E A1 4 E A1 5 E A1 6 E A1 7 E A1 8 E A1 9 E A2 0 E A2 1

HOLDn A R DY

A B E0 n A B E1 n A B E2 n A B E3 n

A C E0 n A C E1 n A C E2 n A C E3 n

H O LD A n BUSREQ

A W E n /S D W E n /S S W E n A O E n /S D R A S n /S SO E n A R En/S D C AS n/S S A DS n

E C LK O U T

ED 0 ED 1 ED 2 ED 3 ED 4 ED 5 ED 6 ED 7 ED 8 ED 9 ED10 ED11 ED12 ED13 ED14 ED15 ED16 ED17 ED18 ED19 ED20 ED21 ED22 ED23 ED24 ED25 ED26 ED27 ED28 ED29 ED30 ED31

R N 12D R N 12C R N 7D R N 7C R N 12B R N 12A R N 7B R N7 A

33 33 33 33 33 33 33 33 V 20 U 19 Y4 V5

3.3V

V 17 W 18 W6 V6

TP 5 TP 4

V 12 A S DW E # W 10 A SD R A S# V 11 A SD C A S# TP TP

R 48 R 45 R 47

Y 10

J18 J19

R 42 R 55

FL S H C E n FL S H O E n FL S H W E n B R D _R S T #

FL AS H _ P AG E

33 33 33

33 33

R58

TC E 0n

T B E 0n T B E 1n T B E 2n T B E 3n

V CC

V SS V SS

NC1 NC2 NC3

R Y /B Y

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 D Q 10 D Q 11 D Q 12 D Q 13 D Q 14 D Q 15/A -1

256 K x 16

A M 29LV 4 00B

BYT E CE OE WE RES ET

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A 10 A 11 A 12 A 13 A 14 A 15 A 16 A 17 A 18 A 19

U 15

TSDW En TSDRASn TSDCASn

47 26 28 11 12

25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 16 9

TCE 1n TCE 2n TCE 3n

TA E C L K O U T 2

TE C LK O U T

1 0K

TE A 2 TE A 3 TE A 4 TE A 5 TE A 6 TE A 7 TE A 8 TE A 9 TE A 10 TE A 11 TE A 12 TE A 13 TE A 14 TE A 15 TE A 16 TE A 17 TE A 18 TE A 19 TE A 20

27 46

10 13 14

15

29 31 33 35 38 40 42 44 30 32 34 36 39 41 43 45

37

DGND

TD 0 TD 1 TD 2 TD 3 TD 4 TD 5 TD 6 TD 7 TD 8 TD 9 TD1 0 TD1 1 TD1 2 TD1 3 TD1 4 TD1 5

3 .3V

+

C T1 3 10

+

0 .1

0.1

C 75

DGND

TE A 16 TE C LK O U T 1 0K

C73

R59

TCE 0n TSD RASn TSDCASn TSDW En

TBE 3n TBE 2n TBE 1n TBE 0n

0.1

C 95

86 72 58 44 84 78 52 46 38 32 12 6

70 69 68 67

20 19 18 17

73 57 30 14

59 28 71 16

23 22 21 24 66 65 64 63 62 61 60 27 26 25

U13

V DD V DD V DD V DD V D DQ V D DQ V D DQ V D DQ V D DQ V D DQ V D DQ V D DQ

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 D Q 10 D Q 11 D Q 12 D Q 13 D Q 14 D Q 15 D Q 16 D Q 17 D Q 18 D Q 19 D Q 20 D Q 21 D Q 22 D Q 23 D Q 24 D Q 25 D Q 26 D Q 27 D Q 28 D Q 29 D Q 30 D Q 31

0.1

C97

0.1

C 74

2 M x 32

43 29 15 1 81 75 55 49 41 35 9 3

2 4 5 7 8 10 11 13 74 76 77 79 80 82 83 85 31 33 34 36 37 39 40 42 45 47 48 50 51 53 54 56

DGND

0 .1

C45

3.3V

M T 48 LC 2M 32B 2T G -6

V SS V SS V SS V SS V S SQ V S SQ V S SQ V S SQ V S SQ V S SQ V S SQ V S SQ

NC NC CLK CKE

CS R AS C AS WE

NC NC NC NC

DQM3 DQM2 DQM1 DQM0

B A1 B A0 NC A 10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

D a te:

S ize B

T itle

T M S 3 2 0 C 67 13 D SK

Tu esd ay, A pril 29, 20 03

50 6 73 2

D ocum e nt N umb er S h eet

4

of

13

TD 0 TD 1 TD 2 TD 3 TD 4 TD 5 TD 6 TD 7 TD 8 TD 9 TD1 0 TD1 1 TD1 2 TD1 3 TD1 4 TD1 5 TD1 6 TD1 7 TD1 8 TD1 9 TD2 0 TD2 1 TD2 2 TD2 3 TD2 4 TD2 5 TD2 6 TD2 7 TD2 8 TD2 9 TD3 0 TD3 1

F L A S H & S D R A M & C O N F IG

CT 5 10

1 0K

R41

3.3V

3 .3V

T E A 14 T E A 13 T E A 15 T E A 12 T E A 11 T E A 10 TEA9 TEA8 TEA7 TEA6 TEA5 TEA4 TEA3 TEA2

T E A [2..2 1]

R ev A

3.3V

Spectrum Digital, Inc

A-5

A-6

C P LD _M CB S P 1_M U X

L R CIN

LRC O UT

A IC 2 3S D AT A IN

A IC 23S D A T A OU T

BCLK

D C _FS X 1

D C _F S R 1

D C _D X 1

D C _D R 1

D C _CL K X 1

D C _C LK R 1

D C _C LK S 1

1 .6K

R1 1 DGND

2

5V

DGND

R12 3 60

1 15

2 3 5 6 11 10 14 13

1 15

2 3 5 6 11 10 14 13

GND

4A

3A

2A

1A

8

12

9

7

4

16

GND

4A

3A

2A

1A

V CC

8

12

9

7

4

16

S N 74 C B T3 25 7P W

S OE

1B1 1B2 2B1 2B2 3B1 3B2 4B1 4B2

U3

S N 74 C B T3 25 7P W

S OE

1B1 1B2 2B1 2B2 3B1 3B2 4B1 4B2

U4 V CC

D CIS O -4.1V D1 L M 4 04 0D CIM 3-4.1

DGND

DGND

E1 M1 L3

U 10 D

FSR1 F SX 1

D X1

CLKS1 CLKR1 C L KX 1 DR1 C LK S 0/A HC L K R 0 C LK R 0/AC L K R 0 C LK X 0 /AC LKX 0

K3 H3 G3

M3 L1

M2 L2

R49 1 0K

R 46 10 K

3.3V

T M S 3 20 C 67 13 G D P

FS R1/A X R0 _7 FSX 1

D R 1/SD A 1 D X1 A XR 0 _5

C LK S /S C L1 C LKR 1/A X R0 _6 C LK X 1/AM U TE 0

R 44 10K

R43 10 K

SCL0 S DA 0

F S R 0/AF S R 0 F SX 0 /AFS X0

D R0/A X R0_ 0 D X0/AX R 0 _1

N1 N2

J3 H1

J1 H2

0.1

0 .1

DGND

12

FSR0

33 33

R 28

9

F SX 0

R 27

7

D X0

8

12

4

C L KX 0

16

8

9

7

4

16

DR0

CLKR 0

DGND CLKS0

C 28

C 13

S OE

1B1 1B2 2B1 2B2 3B1 3B2 4B1 4B2 1 15

2 3 5 6 11 10 14 13

S OE

1B1 1B2 2B1 2B2 3B1 3B2 4B1 4B2 1 15

2 3 5 6 11 10 14 13

S DA 0

S C L0

S N 7 4C B T 3 2 57P W

GND

4A

3A

2A

1A

V CC

U1

S N 7 4C B T 3 2 57P W

GND

4A

3A

2A

1A

V CC

U9

D a te:

S ize B

T itle

Tu esd ay, A pril 29, 20 03

50 6 73 2

D ocum e nt N umb er 5

C T L_F S X 0

C T L_D X 0

C T L_C L K X 0

S h eet

C P LD _ M CB S P 0_ M U X

T M S 3 2 0 C 67 13 D SK

MCB SP

DGND

R 18 36 0

D C _FS X 0

D C _D X 0

D C _CL K X 0

D C _F S R 0

D C _D R 0

D C _C L K R 0

D C _C L K S 0

of

13

R ev A

Spectrum Digital, Inc

TMS320C6713 DSK Module Technical Reference

TM S 32 0 C 6 71 3G D P

U 10 C

H IN Tn /G P 1 H C N T L1/A X R 1 _1 H C N T L0/A X R 1 _3 H H W IL /A FSR 1 H R W n /A X R1 _0 H AS n/AC L K X1 H C Sn /A X R1 _2 H D S1n /A X R1 _6 H D S2n /A X R1 _5 H D R Y n/A C LK R 1

H D 15/G P 15 H D 14/G P 14 H D 13/G P 13 H D 12/G P 12 H D 11/G P 11 H D 10/G P 10 H D 9 /G P 9 H D 8 /G P 8 H D 7 /G P 3 H D 6 /A HC LK R 1 H D 5/A H C L KX 1 H D 4 /G P 0 H D 3 /A M U TE 1 H D2/A F SX 1 H D1 /A X R1 _7 H D0 /A X R1 _4

H D 15 H D 14 H D 13 H D 12 H D 11 H D 10 HD9 HD8 HD7 HD6 HD5 HD4 HD3 HD2 HD1 HD0 H IN T n H C N T L1 H C N T L0 H HW IL HRW n H AS n HCSn H D S 1n H D S 2n HRDYn

B14 C14 A 15 C15 A 16 B16 C16 B17 A 18 C17 B18 C19 C20 D18 D20 E20 J2 0 G 19 G 18 H20 G 20 E18 F 20 E19 F 18 H19

C LK O U T 3

HRW n

HRDYn

H C N T L1

HCSn

H D S 1n

H D S 2n

HD8 H D 10 H D 12 H D 14

HD1 HD3 HD5 HD7

C LK M O D E 0

DGND

HD12

HD8 HD4 HD3 HD14

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 S F M 140 L2 S D LC

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79

J1

iP U

iP U iP D iP U iP U

E ND IAN B O O T -1 B O O T -0 H P I_ E N

DGND

C LK O U T 2

S DA 0

S C L0

R29 R30

R85 R86 R87 R3

3.3V

1K 1K

DGND

3 .3V

R 19 10K

D a te:

S ize B

T itle

Tu esd ay, A pril 29, 20 03

50 6 73 2

D ocum e nt N umb er

T M S 3 2 0 C 67 13 D SK

S h eet

6

H P I_ R E S E T#

of

H P I D A U GH T E R C A R D C AN R E S E T D S P V IA THIS S IG N A L. S IGN A L IS C O M B IN E D W IT H O TH E R D S P RESET S O URCES.

1K 1K 1K 1K

H O S T P O R T /M c A S P

H IN T n

H HW IL

H C N T L0

H AS n

HD9 H D 11 H D 13 H D 15

HD0 HD2 HD4 HD6

8 7 6 5 S W D IP-4/S M P E N C IL SW IT C H

1 2 3 4

SW 3

O FF - O P E N O N - C LO S E D

D E V IC E C O NFIGUR ATION

13

R ev A

Spectrum Digital, Inc

A-7

A-8

D C_E M IFA _ DIR

D C _E M IF A _OE #

TD [0.. 31]

TE A [2 ..21 ]

D C _C N T L _O E #

DGND

DGND

4 10 15 21

48 1 25 24

47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26

42 31

4 10 15 21

48 1 25 24

47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26

42 31 V cc V cc

GND GND GND GND

1B 1 1B 2 1B 3 1B 4 1B 5 1B 6 1B 7 1B 8 2B 1 2B 2 2B 3 2B 4 2B 5 2B 6 2B 7 2B 8

GND GND GND GND

1B 1 1B 2 1B 3 1B 4 1B 5 1B 6 1B 7 1B 8 2B 1 2B 2 2B 3 2B 4 2B 5 2B 6 2B 7 2B 8

V cc V cc

S N 74 LV TH 1 62 45A

GND GND GND GND

1OE 1 DIR 2OE 2 DIR

1 A1 1 A2 1 A3 1 A4 1 A5 1 A6 1 A7 1 A8 2 A1 2 A2 2 A3 2 A4 2 A5 2 A6 2 A7 2 A8

V cc V cc

U 16

3.3V

S N 74 LV TH 1 62 45A

GND GND GND GND

1OE 1 DIR 2OE 2 DIR

1 A1 1 A2 1 A3 1 A4 1 A5 1 A6 1 A7 1 A8 2 A1 2 A2 2 A3 2 A4 2 A5 2 A6 2 A7 2 A8

V cc V cc

D C _E MIFA _ D IR =1 F O R W RITE S

TD 1 6 TD 1 7 TD 1 8 TD 1 9 TD 2 0 TD 2 1 TD 2 2 TD 2 3 TD 3 1 TD 3 0 TD 2 9 TD 2 8 TD 2 7 TD 2 6 TD 2 5 TD 2 4

TD 0 TD 1 TD 2 TD 3 TD 4 TD 5 TD 6 TD 7 TD15 TD14 TD13 TD12 TD11 TD10 TD 9 TD 8

U 17

3.3V

28 34 39 45

2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23

7 18

28 34 39 45

2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23

7 18

DGND

D C _D 1 6 D C _D 1 7 D C _D 1 8 D C _D 1 9 D C _D 2 0 D C _D 2 1 D C _D 2 2 D C _D 2 3 D C _D 3 1 D C _D 3 0 D C _D 2 9 D C _D 2 8 D C _D 2 7 D C _D 2 6 D C _D 2 5 D C _D 2 4

DGND

D C _D 0 D C _D 1 D C _D 2 D C _D 3 D C _D 4 D C _D 5 D C _D 6 D C _D 7 D C _D 1 5 D C _D 1 4 D C _D 1 3 D C _D 1 2 D C _D 1 1 D C _D 1 0 D C _D 9 D C _D 8

DGND

R14 1K

3.3V R 13 10 K

T A E C L K O U T2

T B E 3n T B E 2n T B E 1n T B E 0n T C E 3n T C E 2n TSDCASn TSDRASn TSDW En D C _ AR D Y

DGND

T E A 21 T E A 20 T E A 19 T E A 18

DGND

T E A 17 T E A 16 T E A 15 T E A 14 T E A 13 T E A 12 T E A 11 T E A 10 TEA9 TEA8 TEA7 TEA6 TEA5 TEA4 TEA3 TEA2

4 10 15 21

48 1 25 24

47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26

42 31

4 10 15 21

48 1 25 24

47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26

42 31

GND GND GND GND

1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8

V cc V cc

GND GND GND GND

1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8

V cc V cc

S N 74L V TH 1 624 5A

GND GND GND GND

1O E 1DIR 2O E 2DIR

1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8

V cc V cc

U6

3 .3V

S N 74L V TH 1 624 5A

GND GND GND GND

1O E 1DIR 2O E 2DIR

1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8

V cc V cc

3 .3V

28 34 39 45

2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23

7 18

28 34 39 45

2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23

U5 7 18

DGND

D C _A 2 1 D C _A 2 0 D C _A 1 9 D C _A 1 8

DGND

D C _A 1 7 D C _A 1 6 D C _A 1 5 D C _A 1 4 D C _A 1 3 D C _A 1 2 D C _A 1 1 D C _A 1 0 D C_ A 9 D C_ A 8 D C_ A 7 D C_ A 6 D C_ A 5 D C_ A 4 D C_ A 3 D C_ A 2

3 .3V

33

D C _E C L K O U T

0.1

0.1

#O E L L H

0 .1

C99

0 .1

C94

0 .1

C21

0 .1

C16

DIR L H X

D a te:

S ize B

T itle

T M S 3 2 0 C 67 13 D SK

Tu esd ay, A pril 29, 20 03

50 6 73 2

D ocum e nt N umb er S h eet

7

of

13

R ev B

O P E R AT IO N A <-- B A --> B IS O LA TION

DGND

0.1

C 11 7

3 .3V

DGND

0.1

C 96

3 .3V

DGND

0.1

C 18

3 .3V

DGND

0.1

C 14

3 .3V

D A U G H T E R C A R D B U F F E R IN G

R 403 1K

R15

D C _B E 3# D C _B E 2# D C _B E 1# D C _B E 0# D C _C E 3# D C _C E 2# D C _AR E # D C _AO E # D C _AW E # TARDY

C 98

0.1

0.1

C 118

C 11 5

0.1

0.1

C 1 16

C 19

0.1

0.1

C20

C 15

C17

D C _A[2 1..2 ]

D C _ D [31 ..0 ]

Spectrum Digital, Inc

TMS320C6713 DSK Module Technical Reference

DC_ECL KO UT

D C _ C N T L0 DC_ST AT0 D C _ E IN T 7

D C _ TIN P 0 D C _ E IN T 5 D C _ TIN P 1

DC_DR1

D C _ C LK S 1 D C _D X 1

DC_DR0

D C _ C LK S 0 D C _D X 0

5V

3.3V

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79

C O N N E C T O R 40 X 2

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80

J3

E xte rna l P erip he ral Interfa ce

DGND

-12V

DGND

12V 3.3V

D C _ C N T L1 DC_ST AT1 D C _ E IN T 6

DC_RS T#

D C _ E IN T 4

DC_ TOUT 1

DC_ TOUT 0

D C _ C LK R 1 D C _ FS R 1

D C _ CLK X 1 D C _ FS X 1

D C _ C LK R 0 D C _ FS R 0

D C _ CLK X 0 D C _ FS X 0

5V

R 65 10K

3 .3V

DC_D ET

D C _AR D Y

D C _ A[21..2]

D C _D [31..0]

R 16 4.7K

3.3V

R2

0

D C _ C E 2#

D C _ AW E #

D C _ B E 2# D C _ B E 0#

5V

DGND

3 .3V

D C _D 6 D C _D 4 D C _D 2 D C _D 0

D C _D 14 D C _D 12 D C _D 10 D C _D 8

D C _D 22 D C _D 20 D C _D 18 D C _D 16

D C _D 30 D C _D 28 D C _D 26 D C _D 24

D C_ A 4 D C_ A 2

D C _A 1 2 D C _A 1 0 D C_ A 8 D C_ A 6

D C _A 2 0 D C _A 1 8 D C _A 1 6 D C _A 1 4

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79

D C _D 7 D C _D 5 D C _D 3 D C _D 1

D C _D 1 5 D C _D 1 3 D C _D 1 1 D C _D 9

D C _D 2 3 D C _D 2 1 D C _D 1 9 D C _D 1 7

D C _D 3 1 D C _D 2 9 D C _D 2 7 D C _D 2 5

D C_A 5 D C_A 3

D C _A 13 D C _A 11 D C_A 9 D C_A 7

D C _A 21 D C _A 19 D C _A 17 D C _A 15

DGND

3.3V

D C _AR E # D C _AO E # D C _C E 3 #

D C _B E 3 # D C _B E 1 #

D a te:

S ize B

T itle

Tu esd ay, A pril 29, 20 03

50 6 73 2

D ocum e nt N umb er

T M S 3 2 0 C 67 13 D SK

S h eet

D A U G H T E R CA R D I/F

C O N N E C T O R 40 X 2

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80

J4

E xterna l M e m ory In terface

5V

8

of

13

R ev A

Spectrum Digital, Inc

A-9

DGND

R 34 7 NU

-12V

JP 4 N O -P O P

0

12V

R 99

WARNI NG: DO NOT SUPPLY POWER TO BOTH POWER CONNECTORS AT THE SAME TI ME!

NU M ole x 5 3-109-04 10

+5 GND -12 + 12

4 3 2 1

CENT ER SHU NT S LE EV E

J6

2.5 M M JA C K R A SM 7 12

J5

POWER INPUT

DGND

R 3 46 NU

1 2

1

TP3 2

+

CT16 47 uF

TO BE POPULATED BY T H E U S E R IF NEEDED.

T estP o int

G REEN

D3

R 52 18 0

DGND

5V

SYSTEM PO W ER M EASUREM ENT P O IN T S . R IS 25 12 B O DY , 6 V IA S FR O M P A D T O P L A N E

0.0 25 O H M S FO R P O W E R M EASUREM EN T

O P T IO N A L, P OW E R S U P P L Y L O A D R ES IS TO R S , 2 512 BODY

CT 9 13 12 11

16 15 14

21 20 19 18 17

T P S 54 3 1 0P W P

PGND3 PGND2 PGND1

VIN3 VIN2 VIN1 PH1 PH2 PH3 PH4 PH5

A G ND V S E NS E COMP PW RGD BOO T

A G ND 3 .3 s q in A G N D, m in th ermal pad

P O W E RP A D RT SYNC S S /EN A VB IA S

U7

10 uF LE S R

71 .5K

13 12 11

16 15 14

21 20 19 18 17

T P S 54 3 1 0P W P

PGND3 PGND2 PGND1

VIN3 VIN2 VIN1 PH1 PH2 PH3 PH4 PH5

A G ND V S E NS E COMP PW RGD BOO T

A G ND 3 .3 s q in A G N D, m in th ermal pad

P O W E RP A D RT SYNC S S /EN A VB IA S

U2

6 7 8 9 10

1 2 3 4 5

6 7 8 9 10

1 2 3 4 5

M1 1 25_ P H

M3 1 25_ P H

DGND

M2 12 5_P H

M4 12 5_P H

DAUGHTERCARD STANDOFF GR OUNDING

0 .1u F

C7

0.0 39u F

CT 3

C8

R9

C on ne ct a t pin 1

E M I S U P P R E S IO N . LOC A T E N E A R E A C H R E G UL A TO R . 6 V IA S F R O M P A D T O P L AN E O R D IR E C T T IE .

0 .1u F

0 .1u F

+

71 .5K 1%

R31

C64

C6

B LM 41P 7 50 S P T C9 0 .1u F

L2

+

10 uF LE S R

0.0 39u F

0 .1u F

B LM 41P 7 50 S P T C63 0 .1u F

L4

C 66

C65

C on nec t at pin 1

C3

2.7 u H

C4 0.01u F

L1

K E EP T R A C ES A M IN IM U M O F 0.0 70 IN C HE S F R O M TH E S E H O LE S .

0.047 uF

C2 5 60 pF

R5 1.6 5K 1%

L3 +

R 21

10 7 1 %

10 0uF 4 V

CT 4

1 0K 1 %

3 30 0pF C37

S e ts Voltage

+

CT 2 100 uF 4V

R7 10 K 1%

C5 3 300 pF

O P T IO N A L C R OS S C O U P LE

2.7 u H

C 36 82 00 pF

R6 24 .3K 1%

1.26V -> 24.3K 1% 1.2V -> 2 8.0 K 1%

0.047 uF

C 10

C 12 4 70 pF

R11 2 K 1%

R10 3 .74 K 1%

C1 10 00p F

R8 107 1%

100 0p F

C 11

R 20

JP 1

JP 2

0

0 R4

N O -P O P

N O -P O P

R 66

3 .3V @ 1.5Am p M ax

N O -P O P

C 127

3.3V

+

TP31 TP

1 00 uF

CT1

TP 2 TP

D a te:

S ize B

T itle

Tu esd ay, A pril 29, 20 03

50 6 73 2

D ocum e nt N umb er

T M S 3 2 0 C 67 13 D SK

POW ER

S h eet

9

D S P _CV D D

of

13

R ev B

DSP PO W ER M EASUREM ENT P O IN T S . R IS 2 512 B O DY , 6 V IA S F R O M P A D T O P LA N E

V A L U E S C A LC U LA T E D W IT H SW IF T D E S IG N T O O L 2 .0. F O L LO W TP S 5 431 0 E V M LA Y O U T

S V S _ R S T#

D S PIO _3 .3V

TP

TP 1

0 .02 5 O H M S F O R P O W E R M EASU REM ENT

1 00 uF

C T1 5

D S P _ CV D D

+

D S PIO _3 .3V

10 K

R38

E A C H R E G U LA T O R C AN S U P P L Y U P T O 3 A O F C U R R E N T . H O W E V E R C O M P O N E N T V A LU E S H A V E B E E N S E L E C TE D FOR 1.5 A O P E R A TIO N .

1 .26V @ 1.5Am p M ax

S E N S E _D SP _C V D D

M U R S 12 0T 3 D 16

M U R S 12 0T 3

D 15

M U R S 12 0T 3

D 14

M U R S 12 0T 3

D 13

M U R S 12 0T 3

D 12

3.3V

1 2

A-10 1 2

5V

Spectrum Digital, Inc

TMS320C6713 DSK Module Technical Reference

A4 A9 A 10 B2 B 19 C3 C7 C 18 D5 D6 D 11 D 14 D 15 F4 F 17 K1 K4 K 17 L4 L17 L20 R4 R 17 U6 U 10 U 11 U 14 U 15 V3 V 18 W2 W 19

D S P _CV D D

U 10G

CT14 10

DGND

+

+

C T1 1 10

T M S 32 0 C 671 3G D P

C V DD C V DD C V DD C V DD C V DD C V DD C V DD C V DD C V DD C V DD C V DD C V DD C V DD C V DD C V DD C V DD C V DD C V DD C V DD C V DD C V DD C V DD C V DD C V DD C V DD C V DD C V DD C V DD C V DD C V DD C V DD C V DD

C 30 0.1

C 32 0.1

C 1 05 0 .1

+

C50 0 .1

CT 6 10

DGND

C 10 8 0.1

A 17 B3 B8 B 13 C 10 D1 D 16 D 19 F3 H 18 J2 M 18 R1 R 18 T3 U5 U7 U 12 U 16 V 13 V 15 V 19 W3 W9 W 12 Y7 Y 17

+

D S PIO _3 .3 V U 1 0H

CT 8 10

C 46 0.1

C 24 0 .1

C 23 0 .1

TM S 32 0 C 6 71 3G D P

D V DD D V DD D V DD D V DD D V DD D V DD D V DD D V DD D V DD D V DD D V DD D V DD D V DD D V DD D V DD D V DD D V DD D V DD D V DD D V DD D V DD D V DD D V DD D V DD D V DD D V DD D V DD TM S 32 0 C 671 3G D P

R SV R SV R SV R SV R SV R SV R SV

C29 0 .1

C25 0 .1

C 33 0.1

C 34 0.1

C62 0 .1

C58 0 .1

C 90 0.1

C 88 0.1

C 109 0 .1

C 112 0 .1

C35 0.1

C 1 10 0.1

C 100 0.1

C 104 0.1

C 1 06 0 .1

C 1 01 0 .1

C 10 3 0.1

C 52 0.1

C 1 02 0 .1

C54 0 .1

C 78 0.1

C 56 0.1

C 41 0 .1

C 80 0 .1

C 85 0 .1

DGND

C26 0.1

C47 0.1

C83 0.1

C 77 0.1

C 81 0.1

C 31 0.1

C 48 0.1

DGND

A ll c a p a c ito rs o n t h is s h e e t a r e d e c o u pli n g c a p a c it o rs for the D S P . T he y sho uld be pla ced as close as po ssible to the D S P .

DGND

R 60 1 0K

A5 B5 C 12 D7 D 12 A 12 B 11

U 10J

C51 0 .1

C59 0 .1

D S PIO _ 3.3V

C79 0 .1

C27 0 .1

D S P _CV D D

DGND

U 10I V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS

T M S 32 0 C 671 3G D P

V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS

P19 T4 T1 7 U4 U8 U9 U 13 U 17 U 20 W1 W5 W 11 W 16 W 20 Y1 Y2 Y13 Y19 Y20

DGND

D a te:

S ize B

T itle

Tu esd ay, A pril 29, 20 03

50 6 73 2

D ocum e nt N umb er

T M S 3 2 0 C 67 13 D SK

S h eet

10

of

13

D S P P O W E R & D E C O U P L IN G

D S PIO _3.3 V

D S P _ CV D D

A1 A2 A 11 A 14 A 19 A 20 B1 B4 B 15 B 20 C6 C8 C9 D4 D8 D 13 D 17 E2 E4 E 17 F 19 G4 G 17 H4 H 17 J4 J9 J10 J11 J12 K2 K9 K 10 K 11 K 12 K 20 L9 L10 L11 L12 M4 M9 M 10 M 11 M 12 M 17 N4 N 17 P4 P 17

R ev A

Spectrum Digital, Inc

A-11

DGND

3 .3V

2

.1uF

C 12 2

15 0

R89

T_TCK_ RET

T _T C K

T _E M U 1

T _E M U 0

H U R R ICA N E _ D E Tn

T_TR STn

T _ T MS

T _T D I

T _T D O

3 .3V

5

DGND

3

R90

L TS T -C 15 0G K T U S B IN U S E

D4

4

4

3 .3V 4 7K

S N 74 A HC 1G 1 4

U 18

4 7K

3 .3V

5

2

1

U 23

S N 74L VC 1 G 3 2

DGND

3

1 3 5 7 9 11 13 8 10 12 14

2 4

4

U22 2 S N 74A HC 1 G 14

H E AD E R 7 x2, E m ulation

X D S_T V D

J8

5V

X D S _E M U 0 T _E M U 0 X D S _E M U 1 T _E M U 1 X D S _T C K T_T CK X D S _T C K R E T T_ TCK_ R ET

1.6K

R93

1 15

2 3 5 6 11 10 14 13

1 15

2 3 5 6 11 10 14 13

R 10 0 33

GND

4A

3A

2A

1A

V CC

2 2p F DGND

R95

C 126 100 1%

HUR_ TCKR TN

8

HUR_ TCK

12

DGND

M U X _E M U 0 M U X _E M U 1

9

7

4

16

S N 74 C B T3 25 7P W

S OE

1B1 1B2 2B1 2B2 3B1 3B2 4B1 4B2

U 25

D S P _ TD O

D S P _ TD I

DGND

D S P _ TR S T #

S N 74 C B T3 25 7P W

12

9

7

4

16

D S P _ TM S

GND

4A

3A

2A

1A

V CC

X DS _4.1 V

ROUTE TR ACES AS ONE GROUP. MATCH S IG NAL LENGTH.

8

S OE

1B1 1B2 2B1 2B2 3B1 3B2 4B1 4B2

U 19

DGND

0.1

C 12 3

DGND

D5 L M 4 04 0D CIM 3-4.1

X DS _4.1 V

JTAG MULTI PLEXERS

X D S _T D O T_ TDO X D S_ TD I T_ T D I X D S _T M S T_ T MS X D S _T R S T # T_ T R S Tn

DGND

R 88 1K

1 2

3.3V

3.3V

DGND

R 91

D a te:

S ize B

T itle

2

1

3.3V

DGND

1K

HUR_EMU5 HUR_EMU4 HUR_EMU3 HUR_EMU2 HUR_EMU1 HUR_EMU0

5

RN2C RN2D R N2 A RN2B RN2E RN2F RN2G RN2H

3 .3V

4

33

Tu esd ay, A pril 29, 20 03

S h eet

R 94 3 0.1 K

DGND

11

of

DGND

0.1

C 12 5

13

R ev A

H U R R ICA N E _D E T n

3.3V

DSP_TCK

D1 D2 D3 D4 D5 D6 D7 D8 D9 D 10 D 11 D 12 D 13 D 14 D 15

E M U L A T IO N

D ocum e nt N umb er

50 6 73 2

R 92

33

GND GND GND GND GND GND GND TY P E 1 GND GND GND GND GND GND GND

GND GND GND GND GND GND GND TY P E 0 GND GND GND GND GND GND GND

S N 74 LVC 1G 32

U 24

DGND

C 12 4 .1 uF

R96

S N 7 4L VC 1 G 32 4

DGND

EM U18 EM U17 EM U16 EM U15 EM U14 EM U13 EM U12 EM U11 EM U10 EM U9 EM U8 EM U7 EM U6 EM U5 EM U4 EM U3 EM U2 EM U1 EM U0 TC K R T N TC L K TD O TD I TM S TR S T n ID3 ID2 ID1 ID0 TV D H E AD E R 4x1 5

U 26

C2 B3 C4 C5 B5 C6 B6 C7 C9 B9 C 10 B 10 C 11 B 11 C 12 C 13 B 13 C 14 B 14 C8 B 12 B7 B4 B2 C3 C 15 C1 B 15 B1 B8

A1 A2 A3 A4 A5 A6 A7 A8 A9 A 10 A 11 A 12 A 13 A 14 A 15

D S P _E M U 2 D S P _E M U 3 D S P _E M U 4 D S P _E M U 5

D S P _E M U 1

D S P _E M U 0

L O C A CT E R -P A C K N E AR D S P J7

42 42 42 42 42 42 42 42

T M S 3 2 0 C 67 13 D SK

2

1

DGND

3

R 67

3.3V

5 3

5

A-12 3

DSP JTAG HEADER

Spectrum Digital, Inc

TMS320C6713 DSK Module Technical Reference

A

B

C

C O D E C _C LK

5

C T L_D X 0 C T L_C LK X 0 C T L_F S X 0

B C LK LR CIN A IC 23S D AT A IN A IC 23S D A T A OU T LR C O U T

R 32 33

A IC 23 A udio

C T L_D A T A C T L_ C LK C T L _C S

D A T A _B C LK D A TA _S Y N CIN D AT A _DIN D A T A _D O U T D A T A _S Y N C O U T

C O D E C _S Y S C LK

A IC 23 A udio

S N 74LVC 1G 32

4

3.3V

5 3

D

5

2

1

DGND

4

GND

A IC 3.3V

U 11

.1uFD G N D

C 67

4

DGND

3.3V

C LK _12M H Z

U S B _D S P _R S T #

S V S _R S T #

3

3

3.3V

U S B /Em ulation

C LK _24M H Z

C LK _12M H Z

U S B _D S P _R S T #

PONRSn

3.3V

U S B /Em ulation

GND

T _ T C K _R E T

T_ TR ST n T_ TC K T_ TM S T _T D I T_ TD O T _E M U 0 T _E M U 1

5V

2

2

5V

DGND

D ate:

S ize B

T it le

T uesday, A pril 29, 2003

506732

D ocum ent N umber

T M S 3 2 0 C 67 13 D SK

1

S heet

Hierarc h aric al B loc k s

T_ TCK_ RET

T_ TR STn T _T C K T _ T MS T _T D I T _T D O T _E M U 0 T _E M U 1

1

12

of

13

R ev A

A

B

C

D

Spectrum Digital, Inc

A-13

A-14

A

B

4 2 1

5

D A T A _S Y N C O U T

D AT A _DIN D A TA _S Y N CIN D A T A _B C LK D A T A _D O U T

C T L _C S

C T L_ C LK

A IC 3.3V

A IC 3.3V

1 2 3 4

1 2 3 4

C 335 C 336 NO POP NO POP

C T L_D A T A

R 338 0

L305 B LM 21P 221S N

L304 B LM 21P 221S N

C 320 NO POP

C 318 NO POP

10K

R N 315

10K

R N 314

8 7 6 5

8 7 6 5

R 335

C 330 NO POP R 334

R 328 NO POP

C ontrol P ort

R 336 4.7K

4.7K

4.7K

47pF

1 2 3 4 33

R N 316

R 326

R 345

C 334 470nF

C 333 470nF

1uF

R 337 4.7K

C 321

C 315

4

33

8 7 6 5

4.7K

10uF

10uF

10uF

C 319

C O D E C _S Y S C LK

A IC 23CS

A IC 23LR C IN

S P IM OD E

C 331

C 326 0.1uF

C 325

C 322 0.1uF

C 332 0.1uF

+

Line In

3

C 329 NO POP

R 327 0

R 325 2.2K +

J303

M icrophone In

4 2 1

3

4

+

C

D

J301

L301 H Z 0805E 601R

+

21

4 5 7 3

23 24 22

17 18 20 19

14 8 16

CS

B Vdd D Vdd DGND

DOUT

R LIN E _O U T LLIN E _O U T

RHPO UT LH P O U T

3

T LV320A IC23

D IN LR CIN LR C O U T B C LK

S DIN S C LK MODE

X T I/MC LK XTO C LK O U T

A G ND HPGND

PW Package

M IC _BIAS M IC _IN LLIN E _IN R LIN E _IN

AV dd H P Vdd VM ID

U 307

3.3VA

3

1 27 28

6

13 12

10 9

25 26 2

15 11

GND

0.1uF

C 341

R LIN E _O U T

0.1uF

C 342 +

LLIN E _O U T

L309

10uF

C 343

2

A IC 3.3V

B LM 21P 221S N

A IC 3.3V

C 337 470nF C 338 470nF

2

+

C 323220uF

R 340

R 339

D ate:

S ize B

T it le

T uesday, A pril 29, 2003

506732

D ocum ent N umber

1

S heet

10uF

R 312

C 347

+

3.3VA

10uF

0

2.2

13

J302

4 2 1

3

of

13

R ev A

Line O ut

J304

4 2 1 H ead P hone O ut

3

R 343 0

C 340 NO POP

R 331 0

C 317 NO POP

1

C 346

T M S 320 C 6713 D SK

+

R 344

C 345 NO POP

L307 B LM 21P 221S N

L306 B LM 21P 221S N

C 328 NO POP

L303 B LM 21P 221S N

L302 B LM 21P 221S N

C 344 NO POP

B LM 21P 221S N

C 339 NO POP

A U D IO

A IC 3.3V

C 316 NO POP

C 327 NO POP

R 342 47K

R 333 47K

A IC 3.3V L308

R 341 47K

100

100

R 332 47K

C 324 220uF

+

5

A

B

C

D

Spectrum Digital, Inc

TMS320C6713 DSK Module Technical Reference

Appendix B Mechanical Information

This appendix contains the mechanical information about the TMS320C6713 DSK produced by Spectrum Digital.

B-1

THIS DRAWING IS NOT TO SCALE

Spectrum Digital, Inc

B-2

TMS320C6713 DSK Module Technical Reference

Printed in U.S.A., May 2003 506735-0001 Rev. A