Dissertation 3 : Mohammed S Agamy

SINGLE STAGE POWER FACTOR CORRECTED THREE-LEVEL RESONANT CONVERTERS

by

Mohammed S. Agamy

A thesis submitted to the Department of Electrical and Computer Engineering In conformity with the requirements for the degree of Doctor of Philosophy

Queen’s University Kingston, Ontario, Canada (January, 2008)

©Mohammed Agamy, 2008

Abstract In this thesis, a new approach for single-stage power factor correction converters is proposed to increase their power ratings to be in the multiple kilowatts levels. The proposed techniques are based on the utilization of modified three-level resonant converter topologies. These topologies provide low component stresses, high frequency operation, zero voltage switching, applicability under a wide range of input and output conditions as well as added control flexibility. The proposed control algorithms are based on a combination of variable frequency and asymmetrical pulse width modulation control or variable frequency and phase shift modulation control. In either case, the variable frequency control is used to tightly regulate the output voltage, whereas, pulse width or phase shift modulation is used to regulate the dc-bus voltage as well as the input power factor. New converter topologies, their operation and steady state and dynamic analyses are presented in details. A modelling approach based on average multiple frequency methods is also proposed. This approach leads to the development of a full order state space model with the two control variables explicitly separated allowing a better controller design. The model can be used either at high level of detail expressing the non-linearities of the system or it can readily be simplified to a linear decoupled model for approximate solutions. Finally, a discrete time controller for the proposed converters, which is suitable for FPGA implementation, is presented. Analytical, simulation and experimental results are provided to verify the proposed concepts.

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Acknowledgements First of all I would like to express my gratitude and appreciation to my thesis advisor, Prof. Praveen Jain. His continuous advice, guidance, feedback and encouragement are much behind the realization of this work. I also owe a lot to my committee members, whose advice and feedback were a valuable contribution to the thesis. I would like to thank Mr. Djilali Hamza, ePEARL senior laboratory engineer, for his help and invaluable advice during the experimentation phase of this project. I cannot, of course, forget the role of many people whose advice and discussions helped solve a lot of the issues during the course of my thesis. For this, I would like to thank Mr. Haibo Zhang from CHiL Semiconductor and my current and former colleagues at ePEARL, Wennan Guo, Sayed Ali Khajehoddin, John Lam, Andrew Mason, Shangzhi Pan, Darryl Tschirhart and Zhongming Ye. I would also like to express special thanks to Mrs. Bernice Ison, the graduate program assistant and Ms. Debie Fraser, the graduate secretary at the Department of Electrical and Computer Engineering at Queen’s University for their great help with all the procedural and paper work throughout my time in the Ph.D. program at Queen’s University. Last but not least I would like to thank my wife and my parents for their love and support without which I could not have been able to make it through the frustrations of the past few years.

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To my Parents, Wife & Layla

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Statement of Originality (Required only for Division III Ph.D.)

I hereby certify that all of the work described within this thesis is the original work of the author. Any published (or unpublished) ideas and/or techniques from the work of others are fully acknowledged in accordance with the standard referencing practices.

(Mohammed S. Agamy) (January, 2008)

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Table of Contents Abstract

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Acknowledgements..........................................................................................................iiiii Statement of Originality...................................................................................................... v Table of Contents............................................................................................................... vi List of Figures ..................................................................................................................... x List of Tables ................................................................................................................. xviii List of Symbols and Acronyms...................................................................................... xviii Chapter 1 Introduction ........................................................................................................ 1 1.1 Techniques of Power Factor Correction………………………………………2 1.1.1 Passive Power Factor Correction……………………………………2 1.1.2 Active Power Factor Correction…………………………………….3 1.2 Review of SSPFC Topologies………………………………………………...7 1.2.1 Single Switch Topologies…………………………………………...7 1.2.2 Two Switch Topologies……………………………………………..8 1.2.3 Four Switch Topologies……………………………………………..9 1.2.4 Resonant Converters as Power Factor Correctors…………………10 1.2.5 Comments on the Existing SSPFC Topologies……………………11 1.3 Development of High Power SSPFC Topologies...…………………………12 1.4 Thesis Objectives……….……………………………………………………14 1.5 Thesis Contributions...….……………………………………………………15 1.6 Thesis Organization………………………………………………………….16 Chapter 2 Three-Level Converters with Variable Frequency Asymmetrical Pulse Width Modulation Control......................................................................................... 17 vi

2.1 Introduction…………………………………………………………………..17 2.2 Proposed Converter Topology and Principle of Operation…………………..18 2.2.1 Proposed Topology………………………………………………...18 2.2.2 Principle of Operation……………………………………………...21 2.2.3 Control Method…………………………………………………….27 2.3 Operation in Continuous Conduction Mode…………………………………29 2.4 Steady State Analysis………………………………………………………..32 2.4.1 Analysis of the Boost Operation (from ac input to dc-bus)………..32 2.4.2 Analysis of the Resonant Circuit (from dc-bus to output)…………40 2.5 Simulation Results…………………………………………………………...44 2.6 Experimental Results………………………………………………………...55 2.7 Variations to the Proposed Topology………………………………………..62 2.8 Summary……………………………………………………………………..65 Chapter 3 Three-Level Converters with Variable Frequency Phase Shift Modulation Control ............................................................................................................ 67 3.1 Introduction…………………………………………………………………..67 3.2 Converter Topology and Principle of Operation…………………………….68 3.2.1 The Modified Converter Topology………………………………..68 3.2.2 Principle of Operation……………………………………………..69 3.2.3 Control Method……………………………………………………78 3.3 Restrictions on the Converter Operation…………………………………….79 3.4 Steady State Analysis………………………………………………………..80 3.4.1 Analysis of the Boost Operation (from ac input to dc-bus)………..81

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3.4.2 Analysis of the Resonant Circuit…………………………………..84 3.5 Simulation Results…………………………………………………………...91 3.6 Experimental Results………………………………………………………...98 3.7 Variations to the Proposed Circuit………………………………………….104 3.8 A Comparative View of the Different proposed SSPFC Topologies………104 3.9 Summary……………………………………………………………………108 Chapter 4 Multiple Frequency Average Modelling of Three-Level Single-Stage PFC Converters ..................................................................................................... 109 4.1 Introduction…………………………………………………………………109 4.2 Modelling Issues of SSPFC Converters…………………………………….109 4.3 The Proposed Averaging Multiple Frequency Model……………………...111 4.4 Modelling VFAPWM Converters…………………………………………..113 4.4.1 Case 1: Continuous Conduction Mode…………………………...113 4.4.2 Case 2: Discontinuous Conduction Mode………………………...122 4.5 Modelling of VFPSM Converters…………………………………………..129 4.6 Small Signal Approximation………………………………………………..137 4.7 Decoupled Model…………………………………………………………...146 4.8 Example Controller Design Based on the Decoupled Model………………147 4.9 Summary……………………………………………………………………151 Chapter 5 Discrete Time Realization of the VFPWM and VFPSM Controllers ............ 153 5.1 Introduction…………………………………………………………………153 5.2 Discrete Model of the Converter……………………………………………154 5.3 Cycle by Cycle Controller………………………………………………….156

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5.4 Simulation Results………………………………………………………….158 5.5 Summary……………………………………………………………………166 Chapter 6 Summary and Conclusions............................................................................. 167 6.1 Summary of Contributions………………………………………………….167 6.2 Suggested Future Work……………………………………………………..169 6.3 Conclusion………………………………………………………………….169 References ....................................................................................................................... 171 Appendix A Fundamentals ............................................................................................. 185 A.1 Voltage Stress Reduction in SSPFC Converters…………………………...185 A.2 Resonant Converters Characteristics………………………………………186 A.3 Derivation of the Three-level Converter…………………………………...189 Appendix B Simulation Schematics ............................................................................... 191 B.1 Three Level Resonant SSPFC Converter with VFAPWM Control………..191 B.1.1 Operation in DCM………………………………………………..191 B.1.2 Operation in CCM………………………………………………..193 B.2 Three Level Resonant SSPFC Converter with VFPSM Control…………...194 B.3 Mathematical Model of the Three Level SSPFC Converter……………….195 Appendix C Circuit Layouts and Selected Components................................................. 198 Appendix D Converter Modelling .................................................................................. 210 Appendix E Matlab Programs......................................................................................... 213 E.1 Circuit Performance Analysis………………………………………………213 E.2 Digital Controller…………………………………………………………...215 Appendix F Comparison of the Proposed Converters .................................................... 224

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List of Figures Figure 1.1 Block diagram of standard two-stage PFC converters……………………... 4 Figure 1.2 Other two-stage PFC techniques …………………………………………... 6 Figure 1.3 PWM full bridge single-stage converter with Lin directly connected to the isolation transformer………………………………………………………. 10 Figure 1.4 Resonant converters used for PFC………………………………………… 13 Figure 2.1 The proposed single stage three- level PFC circuit topology………………. 20 Figure 2.2 Switching sequence during one switching cycle for VFPWM control…….. 22 Figure 2.3 Equivalent circuits for each operation stage for the converter in DCM……. 25 Figure 2.4 Equivalent circuits for each operation stage for the converter in CCM……. 26 Figure 2.5 Block diagram of the proposed VFAPWM controller……………………... 28 Figure 2.6 Example of input voltage to resonant circuit at high duty cycle…………… 31 Figure 2.7 Effect of DC-bus voltage selection on the harmonic content of the input current for the case of Vs=90V RMS………………………………………. 35 Figure 2.8 Effect of DC-bus voltage selection on the harmonic content of the input current for the case of Vs=220V RMS……………………………………... 36 Figure 2.9 Determination of Lin for discontinuous conduction mode…………………..37 Figure 2.10 Frequency response of the series parallel resonant circuit………………... 42 Figure 2.11 Output Voltage vs. duty ratio D for different values of switching frequency fs………………………………………………………………… 43 Figure 2.12 Output Voltage vs. turns-ratio for different values of duty ratio D………. 43 Figure 2.13 Output Voltage vs. load resistance for different values of switching frequency fs………………………………………………………………… 43

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Figure 2.14 Input Power Factor at different values of load current…………………… 46 Figure 2.15 For Vs=90V (a) Input voltage (vs) and input line current (is) and (b) peak harmonic current content………………………………………………….. 47 Figure 2.16 For Vs=265Vrms (a) Input Voltage (vs) and input line current (is) and (b) peak harmonic current content for operation under DCM ………………... 48 Figure 2.17 For Vs=90V (a) Input Voltage (vs) and input line current (is), (b) peak harmonic current content………………………………………………….. 49 Figure 2.18 For Vs= 265V RMS (a) Input Voltage (vs) and input line current (is), (b) peak harmonic current content for operation under CCM…………………. 50 Figure 2.19 Switch voltage vds and switch current id to illustrate the Zero Voltage Switching: (a) for switch S1, (b) for switch S4 in DCM ………………….. 51 Figure 2.20 Switch voltage vds and switch current id to illustrate the Zero Voltage Switching: (a) for switch S1 (b) for switch S4 in CCM………………….. 52 Figure 2.21 DC bus Voltage at different values of load current for DCM…………….. 53 Figure 2.22 Converter efficiency at different values of load current…………………... 54 Figure 2.23 Dc-bus voltage at different values of load current for CCM……………… 55 Figure 2.24 Experimental input voltage vs and filtered input current is current harmonics, input voltage 110 V……………………………………………. 57 Figure 2.25 Experimental (a) input current is and (b) current harmonics, input voltage 55 V (CCM)……………………………………………………………….. 58 Figure 2.26 Experimental results: input power factor for different values of load current……………………………………………………………………… 58 Figure 2.27 vds and vgs to show zero voltage switching for the different switches……. 59

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Figure 2.28 Resonant circuit voltage (vab) and current (ir) to illustrate lagging resonant current at different conditions……………………………………………… 60 Figure 2.29 Experimental results: dc-bus voltage for different values of load current 60 Figure 2.30 Experimental results: Conversion efficiency for different values of load current……………………………………………………………………… 61 Figure 2.31 Switching frequency variation for different values of load current………. 61 Figure 2.32 Three-level resonant LLC converter configuration used with VFAPWM control……………………………………………………………………… 64 Figure 2.33 Frequency response of the LLC circuit for a 300 kHz design…………….. 65

Figure 3.1 The proposed topology of the three-level resonant SSPFC converter with auxiliary circuit…………………………………………………………….. 71 Figure 3.2 Switching sequence for frequency + Phase shift control…………………... 72 Figure 3.3 Equivalent circuits for each operation stage for the converter……………... 75 Figure 3.4 Discharge modes of the input inductor……………………………………... 78 Figure 3.5 A Simplified block diagram of the proposed VFPSM control closed loop system……………………………………………………………………… 82 Figure 3.6 Effect of dc-bus voltage selection on the harmonic content of the input current for the case of Vs= 90V RMS, fs=180 kHz………………………… 86 Figure 3.7 Effect of dc-bus voltage selection on the harmonic content of the input current for the case of Vs= 265V RMS, fs= 180 kHz………………………. 87 Figure 3.8 Gain and phase plots for the resonant circuit for different turn ratios………88 Figure 3.9 Gain and phase plots for the resonant circuit for different Cp/Cs…………... 88

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Figure 3.10 Variation of the output voltage with duty ratio and frequency…………… 89 Figure 3.11 Variation of the output voltage with capacitor ratio……………………… 90 Figure 3.12 Simulation results: input Power Factor at different values of output load current……………………………………………………………………… 92 Figure 3.13 Simulation results: (a) Input Voltage (vs) and filtered input current (is) at Vs=90V RMS (b) harmonic content of the input current………………….. 93 Figure 3.14 Simulation results: (a) Input Voltage (vs) and filtered input current (is) at Vs=265V RMS, (b) Harmonic content of input current…………………… 94 Figure 3.15 Simulation results: switch drain source voltage and drain current to illustrate zero voltage switching…………………………………………… 95 Figure 3.16 Simulation results: Resonant circuit voltage (vAB) and resonant current (ir) to illustrate ZVS………………………………………………………... 96 Figure 3.17 Simulation results: dc-bus Voltage (Vbus) at different values of output load current………………………………………………………………… 97 Figure 3.18 Simulation results: Estimated converter efficiency at different values of output load current………………………………………………………… 98 Figure 3.19 Experimental input voltage vs and filtered input current is current harmonics, input voltage 110 V RMS at high output current……………… 100 Figure 3.20 Experimental input voltage vs and filtered input current is current harmonics, input voltage 110 V RMS at 20% full load condition…………. 100 Figure 3.21 Experimental results: input power factor versus output load current……... 101 Figure 3.22 vds and vgs to show ZVS…………………………………………………... 101

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Figure 3.23 Resonant circuit voltage (vab) and current (ir) to illustrate lagging resonant current at different conditions……………………………………………… 102 Figure 3.24 Experimental results: dc-bus voltage versus output load current…………. 102 Figure 3.25 Experimental results: Conversion efficiency versus output load current…. 103 Figure 3.26 Three-level resonant converter configurations used with VFPSM control.. 105 Figure 3.27 Input power-factor versus output current…………………………………. 106 Figure 3.28 Dc-bus voltage of different configurations under different input voltage versus output current……………………………………………………….. 107 Figure 3.29 Efficiency of different converter configurations versus output current…... 107

Figure 4.1 Equivalent Circuits for the two stages of operation (CCM)………………... 115 Figure 4.2 Open loop steady state output voltage at different values of control inputs.. 121 Figure 4.3 Equivalent Circuits for the three stages of operation (DCM) ………………125 Figure 4.4 Input inductor current in discontinuous conduction mode…………………. 128 Figure 4.5 Discharge modes of the input inductor……………………………………... 130 Figure 4.6 Compensated response dc-bus voltage to duty cycle………………………. 143 Figure 4.7 Simulation results: Input current with 50% step load change at t=0.1s…… 144 Figure 4.8 Experimental results: Input current with 50% step load change…………… 144 Figure 4.9 Simulation results: Output voltage with 50% step load variation at t=0.1 sec………………………………………………………………………….. 145 Figure 4.10 Experimental results: Output voltage: (a) during start time and (b) with a 50% step load change……………………………………………………….145 Figure 4.11 Simplified block diagram of the decoupled circuit……………………….. 146

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Figure 4.12 Actual and estimated input current………………………………………... 151

Figure 5.1 Root locus of the closed loop transfer function at the output stage in Zdomain………………………………………………………………………156 Figure 5.2 Simplified block diagram of the proposed control scheme for the case of VFAPWM Control…………………………………………………………. 157 Figure 5.3 Simplified block diagram of the proposed control scheme for the case of VFPSM control…………………………………………………………….. 158 Figure 5.4 Flow chart of the control algorithm………………………………………… 159 Figure 5.5 (a) Input current , (b) Dc-bus voltage and (c) Output voltage at minimum input voltage and 50% step load change at t=0.1s…………………………. 161 Figure 5.6 (a) Input current (b) Dc-bus voltage and (c) Output voltage at maximum input voltage and 50% step load change at t=0.1s…………………………. 162 Figure 5.7 (a) Output voltage error and (b) frequency variation for the case of maximum input voltage……………………………………………………. 163 Figure 5.8 (a) Output voltage error and (b) frequency variation for the case of minimum input voltage…………………………………………………….. 164 Figure 5.9 Output of duty cycle counter (a) at start up and (b) at steady state………… 165 Figure 5.10 The resultant duty ratio during the converter start up…………………….. 165

Figure B.1 PSIM simulation schematic of the power circuit for the converter described in figure 2.1………………………………………………………191

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Figure B.2 PSIM simulation schematic of the control circuit for the converter in figure A.1…………………………………………………………………... 192 Figure B.3 PSIM simulation schematic of the three level resonant SSPFC converter operating in CCM………………………………………………………….. 193 Figure B.4 PSIM simulation schematic of the three level resonant SSPFC converter operating with VFPSM control…………………………………………….. 194 Figure B.5 Matlab / Simulink schematic of the mathematical model of the three level SSPFC converter…………………………………………………………… 195 Figure B.6 Expansion of the equations expressing dynamics of the resonant current… 196 Figure B.7 Expansion of the equations expressing dynamics of the series resonant capacitor voltage…………………………………………………………… 196 Figure B.8 Expansion of the equations expressing dynamics of the parallel resonant capacitor voltage…………………………………………………………… 197 Figure B.9 Expansion of the equations expressing dynamics of the dc-bus voltage…... 197

Figure C.1 Power circuit for VFAPWM converter: Input to dc-bus…………………... 198 Figure C.2 Power circuit of the VFAPWM converter: resonant tank to output……….. 199 Figure C.3 Power circuit for VFPSM converter: Input to dc-bus……………………… 199 Figure C.4 Power circuit of the VFPSM converter: resonant tank to output………….. 200 Figure C.5 Implementation of the VFPSM Controller………………………………… 200 Figure C.6 Implementation of the VFAPWM Controller……………………………… 201 Figure C.7 Implementation of gate signal isolation and gate drive circuits…………… 202

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Figure C.7 PCB layout of board 1 of the VFAPWM converter………………………...203 Figure C.8 PCB layout of board 2 of the VFAPWM converter………………………...203 Figure C.9 PCB layout of board 1 of the VFPSM converter…………………………... 204 Figure C.10 PCB layout of board 2 of the VFPSM converter…………………………. 204 Figure C.11 Isolation transformer test results………………………………………….. 205 Figure C.12 Isolation transformer test results………………………………………….. 206 Figure C.13 Experimental sample switching signals…………………………………... 207 Figure C.14 Experimental sample switching signals…………………………………... 207

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List of Tables Table 2.1 Converter parameters for VFAPWM operation……………………………...45 Table 2.2 Comparison between theoretical and experimental results…………………. 62 Table 3.1 Converter parameters for VFPSM operation………………………………... 91 Table 3.2 Comparison between theoretical and experimental results…………………..103 Table 3.3 Comparison between the two controllers…………………………………….105 Table 5.1 Required FPGA design parameters…………………………………………..160 Table C.1 Component part numbers…………………………………………………… 208 Table F.1 Comparison between PFC topologies………………………………………..224

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List of Symbols and Acronyms Acronyms AC: Alternating Current APWM: Asymmetrical Pulse Width Modulation CCM: Continuous Conduction Mode DC: Direct Current DCM: Discontinuous Conduction Mode DF: Distortion Factor EMI: Electromagnetic Interference MFA: Multiple Frequency Average PF: Power Factor PFC: Power Factor Correction PSM: Phase Shift Modulation PWM: Pulse Width Modulation RMS: Root Mean Square SMPS: Switch Mode Power Supply SSPFC: Single Stage Power Factor Correction VFAPWM: Variable Frequency Asymmetrical Pulse Width Modulation VFPSM: Variable Frequency Phase Shift Modulation ZVS: Zero Voltage Switching.

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Symbols 1. Circuit Parameters Cb1: Dc-bus capacitor 1 Cb2: Dc-bus capacitor 2 Cf: Flying capacitor Co: Output filter capacitor Cp: Parallel resonant capacitor Cs: Series resonant capacitor Dc1: Clamping diode 1 Dc2: Clamping diode 2 Daux1: Auxiliary diode 1 Daux1: Auxiliary diode 2 Lin: Input boost inductor Lo: Output filter inductor Lp: Parallel resonant inductor Ls: Series resonant inductor N1: Number of turns on the primary winding of the isolation transformer N2: Number of turns on the secondary winding of the isolation transformer Naux1: Number of turns on the primary winding of the auxiliary transformer Naux2: Number of turns on the secondary winding of the auxiliary transformer Rac: Ac equivalent resistance of the load connected at the output of the resonant circuit RL: Load resistance

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2. Variables Used in Analysis φ : Phase angle between the input voltage and input current cosφ: Displacement factor A: Plant matrix of the circuit Adc: Dc-components of the plant matrix of the circuit Adq: High frequency dq-component of the plant matrix of the circuit Adql: Low frequency dq-component of the plant matrix of the circuit B: Input matrix Bdc: Dc-components of the input matrix Bdq: High frequency dq-component of the input matrix Bdql: Low frequency dq-component of the input matrix D: Duty cycle d: fraction of the switching cycle during which the input inductor current decays to zero in discontinuous conduction mode d2: fraction of the switching cycle during which the input inductor current decays to zero through Cb2 for VFPSM control d3: fraction of the switching cycle during which the input inductor current decays to zero through Cb1 and Cb2 for VFPSM control fl: Power line frequency (50 or 60 Hz) fo: Resonant frequency fs: Switching frequency gi, gv: Switching function gains Io: Output current Is(n): Peak value of the nth harmonic of the input current xxi

Is RMS: Root mean square value of the input current iLin: Input inductor current iLin(dc): Dc-component of the input inductor current iLinq: High frequency cosine component of the input inductor current iLind: High frequency sine component of the input inductor current iLinql: Low frequency cosine component of the input inductor current iLindl: Low frequency sine component of the input inductor current ip: Transformer primary current ir: Resonant current ir(dc): Dc-component of the resonant current irq: High frequency cosine component of the resonant current ird: High frequency sine component of the resonant current is(t): Source current K: Observer gain matrix k: Switching cycle number n: Harmonic order Pav: Average power Po: Output power Q: Quality factor s: Laplace domain variable Ts: Switching period V1: Voltage across capacitor Cb1 V1(dc): Dc-component of the voltage across capacitor Cb1

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V1q: High frequency cosine component of the voltage across capacitor Cb1 V1d: High frequency sine component of the voltage across capacitor Cb1 V1ql: Low frequency cosine component of the voltage across capacitor Cb1 V1dl: Low frequency sine component of the voltage across capacitor Cb1 V2: Voltage across capacitor Cb2 V2(dc): Dc-component of the voltage across capacitor Cb2 V2q: High frequency cosine component of the voltage across capacitor Cb2 V2d: High frequency sine component of the voltage across capacitor Cb2 V2ql: Low frequency cosine component of the voltage across capacitor Cb2 V2dl: Low frequency sine component of the voltage across capacitor Cb2 Vbus: DC-bus voltage Vbus(ref): Reference value for the DC-bus voltage Vm : Peak of the sinusoidal input voltage Vo: Output voltage Vs(dc) : Average value of the input voltage Vs(rms): Root mean square value of the input voltage Vs(n): Peak value of the nth harmonic of the input voltage vAB: The input voltage to the resonant tank vcs: Voltage across the series resonant capacitor vcs(dc): Dc-component of the series resonant capacitor voltage vcsq: High frequency cosine component of the series resonant capacitor voltage vcsd: High frequency sine component of the series resonant capacitor voltage vp: Voltage across the parallel resonant capacitor

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vp(dc): Dc-component of the parallel resonant capacitor voltage vpq: High frequency cosine component of the parallel resonant capacitor voltage vpd: High frequency sine component of the parallel resonant capacitor voltage vs(t): Source voltage x: State vector xdc: Dc-component of the state vector xdq: High frequency dq-component of the state vector xdql: Low frequency dq-component of the state vector Zp(n): Equivalent impedance of the parallel branch of the resonant circuit at harmonic order n Ztot (n): Equivalent impedance of the resonant circuit at harmonic order n γ: Phase shift angle for VFPSM control

θ pn : The angle of Zp(n) θ n : The angle of Ztot (n) σ: Switching function ωl: Angular power line frequency ωs : Angular switching frequency ωo: Angular resonant frequency

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___________________________________________________________________Chapter1: Introduction

Chapter 1 Introduction

The power supply unit is an essential circuit block in all electronic equipment. It is the interface between the ac mains and the rest of the functional circuits of the equipment. These functional circuits usually need power at one or more fixed dc voltage levels. Switch mode power supplies (SMPS) are most commonly used for powering electronic equipment since they provide an economical, efficient and high power density solution compared to linear regulators. Switch mode ac/dc converters are the first building block to supply power from ac mains to down-stream converters for the electronics circuits (normally known as loads). Therefore, they should provide performance characteristics that are acceptable by both the ac mains and the output load. From the ac mains point of view, a power supply should provide good power quality, such that, the input current and input voltage are purely sinusoidal at the line frequency (50 or 60 Hz) and are in phase. Whereas, from the load point of view, a well regulated output voltage with low ripples is required. In order to conserve energy, high overall power conversion efficiency is required. However, conventional ac/dc switch mode power supplies introduce some adverse effects on the ac side. Examples of such effects are, distortion of input current/voltage, input voltage dip due to the presence of bulk capacitors and electromagnetic interference (EMI) due to high frequency switching [1]. In recent years power factor correction (PFC) circuitry have

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___________________________________________________________________Chapter1: Introduction

become integral part of the ac/dc power supply design to meet the input power quality requirement as per standards such as IEC 1000-3-2 [2], IEC 1000-3-4 [3] and IEEE-5191992 [4]. A brief description of the PFC techniques is given in the subsequent sections.

1.1 Techniques of Power Factor Correction Many methods have been used to remove current harmonics and thus improve the overall system power factor. There are two main methods to eliminate or at least reduce the input line current harmonics: 1. Passive power factor correction 2. Active power factor correction 1.1.1 Passive Power Factor Correction Passive PFC is the simplest and most straightforward method to eliminate input current harmonics. This is achieved by using passive reactive elements either at the input or at the output side of input rectifier employed in the design of ac/dc converter. Advantages of this method are high efficiency, low EMI and simple implementation. However, the main drawbacks particularly at the low frequency are the size, weight and cost. Several passive PFC techniques have been investigated in the literature. It is shown in [6] that a series tuned passive LC filter at the fundamental operating frequency is a suitable way for obtaining unity power factor in high frequency ac power distribution systems. However, for 50/60 Hz, power distribution systems, the LC filter is tuned at the fifth harmonic frequency and a series tuned LC filter is connected in parallel to the rectifier to trap the third harmonic current to prevent damping the fundamental component [7-11].

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___________________________________________________________________Chapter1: Introduction

1.1.2 Active Power Factor Correction In this approach, switching converters are used to shape the input current drawn by the ac/dc converter into a sinusoidal waveform that is in phase with the input voltage waveform. Therefore, the power factor reaches almost unity and the ac/dc converter emulates a pure resistive load. Active PFC has many advantages over passive PFC such as higher power factor, lower harmonic content, smaller converter size due to the ability to use high switching frequencies, lighter weight and higher reliability. On the other hand active PFC presents a more challenging converter design and control problem as compared to the passive approach [12]. Active PFC can be implemented by controlling the conduction time of the converter switches to force the ac current to follow the waveform of the applied ac voltage. Usually two control loops are required to achieve this: first a wide bandwidth inner current loop to shape the input current; second, a narrow bandwidth outer loop is designed to regulate the output dc voltage of the load. There are two-stage and single-stage power factor correction techniques. These techniques are discussed below. A. Two-stage power factor correction Two-stage PFC using an input current shaper followed by a dc/dc converter is the fundamental approach for active PFC. A block diagram of this technique is shown in figure 1.1. The power factor pre-regulator allows the rectifier to draw current from the supply during the whole power cycle, instead of the current pulses drawn by the traditional diode rectifier, and this current is made to follow a sinusoidal reference in phase with the supply voltage [13-15]. The most widely used pre-regulator circuit is the boost converter and it can be operated either in discontinuous conduction mode (DCM) in 3

___________________________________________________________________Chapter1: Introduction

the voltage mode control or in continuous conduction mode (CCM) in the current mode control. Buck and buck-boost converters can also be used as input current shapers but some distortion must be allowed in the case of buck converters; whereas efficiency is degraded and component stresses are high in the case of buck-boost converters [16-22]. The boost converter provides superior performance at the expense of the necessity of having the output voltage higher than the peak input voltage [23]. Pulse width modulation (PWM) is most commonly used to achieve those two tasks. Several control methods can be used for input current shaping, such as average current mode control, peak current mode control or hysterisis control and nonlinear carrier control [24-27]. The dc/dc converter stage (mostly an isolated converter) can be a forward, a flyback or any other step down converter. This method is known for its superior performance, such as high power factor, low input harmonics, good hold up time and optimized design of the dc/dc converter, but this is achieved at the cost of additional semi-conductor switches and control circuitry; converter size and efficiency. Two-stage ac/dc converter

Power Factor Pre-regulator

vs(t)

Dc-Dc Converter

Load

Diode Rectifier Dc-bus Figure 1.1 Block diagram of standard two-stage PFC ac/dc converter

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Other methods for two-stage PFC include the use of active shunt regulators [2830] and active power filters [31-34]. In these cases, shown in figure 1.2, the objective is to reduce the percentage of power processed by the additional stage to increase the conversion efficiency. In the case of shunt regulators, they are connected at the input of the dc/dc converter or directly to the output to supply part of the required energy. Whereas, active power filters are connected in parallel at the input terminals in order to provide the harmonic content in the converter current instead of these harmonics being supplied by the ac mains. Active power filters are more useful in very high power applications. B. Single-stage power factor correction Since regulatory agencies on the power factor, do not require a perfectly sinusoidal input line current, efforts have been made to obtain smaller converters with fewer switches that could comply with the regulations and be more cost effective. This led to the emergence of single-stage power factor corrected (SSPFC) converters. SSPFC circuits are required to provide the features of both the power factor preregulators in addition to those of the dc/dc converter cascaded with it. These features are: i.

A well regulated output voltage.

ii.

Isolation between the input ac mains and the output load on the dc side.

iii. A sinusoidal input line current with low harmonic distortion that meets the requirements of IEC 100-3-2 and IEC 1000-3-4 standards. iv. High efficiency by eliminating/reducing switching and conduction losses. v.

Small component sizes and reasonable voltage and current ratings.

The basic SSPFC circuits were introduced in the early 1990s by Madigan et. al. This was achieved by integrating the boost input current shaping converter with either a flyback 5

___________________________________________________________________Chapter1: Introduction

Load

vs(t)

Dc-Dc Converter

Power Factor Pre-regulator Diode Rectifier Active Shunt Regulator

Connection made either to dc/dc converter or to Output

Dc-Dc Converter

vs(t)

Load

Diode Rectifier Active Power Filter Connection can be made either to input or output of the diode rectifier Figure 1.2 Other two-stage PFC techniques (a) Active shunt regulator, (b) Active power filter or a forward converter [35]. Several SSPFC topologies have been introduced in the literature [36-41], but these single-stage converters had limitations on their output power and the range of input voltage. Several single-stage topologies use a small energy storage capacitance leading to large low frequency ripples in the output voltage. If a larger capacitor is used to reduce these ripples, it introduces another drawback that results in uncontrolled floating dc-bus capacitor voltage. This capacitor voltage can reach very high levels especially at light load conditions. This imposes a high voltage stress on the converter switches. Many attempts have been made to reduce this voltage stress by using

6

___________________________________________________________________Chapter1: Introduction

output or dc-bus voltage feedback as was presented in [42, 43]. But the main limitation of the SSPFC topologies is on the practical power processing capability. The objective of this thesis is therefore, to increase the practical power processing capability of SSPPC techniques. Before, a comprehensive list of the thesis objectives is given; it is beneficial to review state-of-the-art SSPFC converter topologies in the following section.

1.2 Review of SSPFC Topologies 1.2.1 Single Switch Topologies As mentioned earlier, the basic SSPFC converter is a result of the combination of the boost input current shaper with a flyback converter or a buck converter such that a single switch is used in common by the two converters. The former is called boost integrated with flyback rectifier/energy storage dc/dc converter (BIFRED), while the latter is called boost integrated with buck rectifier/energy storage dc/dc converter (BIBRED) [44]. In both of these circuits as well as others based on their concept in [45], the boost input current shaper operates in discontinuous conduction mode to achieve automatic current shaping, while the output of the converter may operate in either continuous or discontinuous conduction mode. However, if the output current is in continuous conduction mode the dc-bus voltage varies with the output load. For universal input applications, it will suffer high voltage stress at high input voltage and light load, which requires expensive capacitors and increases the switch voltage stress. Therefore, one of the suggestions to solve this problem is to operate both the input current shaper and the dc/dc converter in the discontinuous conduction mode, but this leads to undesirable ripples and oscillations in the output voltage [41-46]. In [41, 44] a 7

___________________________________________________________________Chapter1: Introduction

compromise between the THD and the capacitor voltage stress is made in order to maintain the continuous conduction mode at the output. The voltage stress on the bulk capacitor can also be reduced by introducing a feedback loop in the power circuit [42, 45]. In [42] a converter operating on the same principle but with employing an additional flyback transformer and a snubber circuit to reduce the turn off spikes is presented. This converter operates at slightly higher efficiency (approximately 81%) compared to the circuits presented in [45] because of the reduced losses and the power processing times are reduced due to the input feed forward features of this topology. However, this gain in efficiency is still insufficient to make these converters useful for high power levels, due to the existence of circulating currents. In addition to this, the output operates in DCM, which is also undesirable 1.2.2 Two Switch Topologies Half-bridge converters have also been studied for SSPFC applications either in symmetrical or asymmetrical modes of operation. Although they are able to provide high input power factor they still suffer from high circulating currents, high dc-bus voltages or discontinuous output current [47, 48]. Other examples of two switch SSPFC circuits use auxiliary circuits in order to obtain a reduced bulk capacitor voltage. References [36] and [49] present an SSPFC rectifier based on a forward converter. This converter has an auxiliary circuit whose purpose is to get a reduced bulk capacitor voltage stress. This converter is designed such that it always operates in the discontinuous conduction mode. This provides high power factor, however, this comes at the expense of an increased current stress on the power circuit components. This results in high conduction losses and thus reduced efficiency.

8

___________________________________________________________________Chapter1: Introduction

This makes the operation of the converter restricted to a low output power range. The aforementioned SSPFC converters are not recommended for operation above 200 W because of the low efficiency. 1.2.3 Four Switch Topologies Full-bridge circuits are used as single-stage PFC converters for higher power levels. SSPFC circuits based on full bridge converters are presented in [50-52]. In [50] a PWM controlled full bridge is presented. In this case, natural current shaping for the input current is achieved. This topology, shown in figure 1.3, has an input inductor directly connected to the isolation transformer through two diodes. The voltage stress on the storage capacitor in this case is limited to 450 V but this comes at the expense of higher low frequency distortion in the input current. If these low frequency distortions are to be eliminated, the dc-bus capacitor voltage will take much higher values. The resulting conversion efficiency also makes the application of this converter limited to low power levels. In [52] another PWM technique is used to control the converter, such that it is possible to produce a continuous input current that is sinusoidal and in phase with the input voltage. An auxiliary circuit is used in order to obtain zero voltage switching (ZVS) for the full bridge switches. Full bridge topologies have also been studied for three phase applications. In [53] a three-phase single-stage full bridge ac/dc converter was proposed, using a boost integrated bridge converter with an auxiliary circuit and a switching sequence set to achieve ZVS over a wide range of loading. The drawbacks of this method are that it operates with discontinuous current at both input and output. The part count is the same as that of the two-stage method due to the use of an auxiliary circuit to achieve ZVS. The input voltage range is limited due to the high dc-bus voltage stress. The converter 9

___________________________________________________________________Chapter1: Introduction

efficiency is less than 90%, which is better than previously presented single-stage topologies, but not considered good for a three-phase application and still needs improvement to be suitable for high power operation. 1.2.4 Resonant Converters as Power Factor Correctors Resonant converters have many attractive properties, such as zero voltage switching, high power densities due to the operation at high switching frequency, low cost and high efficiency. Therefore, they have also been studied in their operation in high input power factor mode. The LC series resonant converter is not applicable for PFC operation due its voltage step down characteristics. Therefore, it cannot maintain line current into the valley of the rectified input ac voltage waveform and hence must be shut off typically when the line voltage falls below 50% of its peak value. LC parallel and LCC series/parallel resonant converters, shown in figure 1.4, have voltage step up capabilities; therefore, they can be used in high power factor operation modes [54 & 55].

Lin is(t) Load vs(t)

Input Filter

CB

Co

Vo

Diode Rectifier

Figure 1.3 PWM full bridge single-stage converter with Lin directly connected to the isolation transformer [50]

10

___________________________________________________________________Chapter1: Introduction

The series/parallel resonant converter generally has lower component stresses compared to the parallel resonant converter. On the other hand, this converter requires a wide frequency swing to maintain ZVS over the line half cycle. The second problem is the high component of low frequency current at the output and thus the existence of low frequency oscillation in the output voltage, due to the lack of a storage capacitor in these circuits. Furthermore, the switching frequency range required to regulate the output voltage for universal line input is very wide, which makes EMI filter design much more difficult. In [57 & 58] series parallel resonant converters are employed as single stage power factor correctors. They can be operated with and without active current control giving good results in both cases but still the range of input voltage and output power for these converters is limited. Other topologies and control methods for full bridge resonant circuits operating as single stage power factor correctors are demonstrated in [59-63] but their efficiency, component stresses and/or compromised distortion of the input current waveform still limit their applicability to the range of output power to a few hundred watts. 1.2.5 Comments on the Existing SSPFC Topologies The review of present single-stage power factor correction circuits has indicated at least one of the following problems: •

High component voltage and current stresses.

•

High circulating currents.

•

Low frequency oscillations in the output.

•

High ripple in the output voltage.

•

Wide range of frequency variation in the resonant circuits.

11

___________________________________________________________________Chapter1: Introduction

•

High circuit complexity with a large number of components.

Because of above drawbacks the practical power ratings for the present single-stage power factor corrected converters are only several hundred watts.

1.3 Development of High Power SSPFC Converter Topologies Review of the above topologies shows that single-stage full bridge converter can provide higher power if the dc-bus voltage can be clamped and/or the voltage stress across the switches can be reduced. Three-level dc/dc converters proposed in [64-68] have low voltage stress across the switches while operated from a high dc-bus voltage. Furthermore, different techniques for three-level soft-switched PWM and resonant converters have been presented in [69-75]. Proper switching sequence for these converters provides zero voltage switching for a wide range of input voltage and output loads. Due to the features and performance of the three-level dc/dc converters, they are considered good candidates for front end power factor corrected converters. Several topologies for this application have been proposed in the literature [76-81]. As an example of these topologies, a two-stage converter that has a three-level boost preregulator followed by a dc/dc converter is presented in [76]. The use of three-level boost and a dc/dc converter that is composed of two series connected half bridge converters operating with phase shift modulation leads to the reduction of voltage stress across the capacitors compared to the equivalent PWM converter. Moreover, the current stress is shared equally among all switches resulting in high converter efficiency. The drawback of this method is the high component count and the need for two 3-winding high frequency transformers.

12

___________________________________________________________________Chapter1: Introduction

The use of three-level topologies as three phase single-stage converters is presented in [79] but they still suffer extremely high voltage stress across switches, leading to the use of switches of high voltage rating, despite the use of a three-level topology. The efficiency is also low, making it impractical for high power applications. Appendix A contains further details on the fundamentals of both the three-level converters and resonant circuits.

Ls is(t)

Lo Load Ci

Ein

Cp

vs(t)

Co

Vo

Diode Rectifier

Ls is(t)

Cs Lo Load

Ci

Ein

Cp

vs(t)

Co

Vo

Diode Rectifier

Figure 1.4 Resonant converters used for PFC: (a) LC parallel resonant converter, (b) LCC series/parallel resonant converter

13

___________________________________________________________________Chapter1: Introduction

New methods to overcome these limitations are proposed in this thesis. The resonant circuits, three-level converters and boost power factor pre-regulators are combined to form single-stage high power factor converter circuits, which are suitable for high power outputs.

1.4 Thesis Objectives The techniques proposed in this thesis integrate the boost power factor preregulator, three-level and resonant dc/dc converters. The following are the objectives of this thesis: 1. Development of single-stage power factor correction topologies suitable for higher power applications (in the range of multiple kilowatts) and with the following features; •

Tightly regulated output voltage with minimal low-order harmonic components. The converter should be able to provide this output for the universal input voltage range (90-265Vrms).

•

An input ac line current that complies with the IEC1000-3-2 and IEC10003-4 standards and gives a high power factor.

•

Elimination/reduction of the switching losses. This can be achieved by operating the resonant circuit above its resonance frequency, in addition to the use of the rectified line current to assist in obtaining ZVS of the switches.

•

Reduce the dc-bus voltage, and regulate it to a fixed level throughout the different input and load conditions.

14

___________________________________________________________________Chapter1: Introduction

•

Balance the voltages in the three-level converter, in order to be able to use switches of smaller ratings, as the voltage stress per switch is half that of the dc-bus. This leads to higher conversion efficiency; therefore, the converter becomes more suitable for higher power applications.

2. Development and implementation of different control strategies for optimum operation of the proposed converters. 3. Modelling and analysis of the proposed converter topologies to study their steadystate and dynamic performance. 4. Experimentation to verify the proof-of-concept, performance validation and assessment of accuracy of the proposed modelling and analysis. 5.

Investigation of a discrete-time control method suitable for variable frequency and phase-shift

or

asymmetrical

pulse

width

modulation

control

for

the

implementation of a flexible and reliable digital controller.

1.5 Thesis Contributions The major contributions presented in this thesis are summarized as follows: (i)

A single-stage three-level resonant converter topology is proposed by integrating the three-level half-bridge resonant dc-dc converter with the boost power factor pre-regulator.

(ii)

A variable frequency asymmetrical pulse width modulation (VFAPWM) control method is proposed. Variable frequency control is used to regulate the output voltage to the required level, where the APWM control is used for input current shaping as well as dc-bus voltage regulation.

(iii)

A variable frequency phase shift modulation controller (VFPSM) is proposed.

15

___________________________________________________________________Chapter1: Introduction

(iv)

A state space approach using combined averaging and multiple frequency techniques is proposed for modelling the proposed converters. This modelling procedure can be used for either continuous or discontinuous conduction mode. This approach enables the separation of both frequency and duty ratio (or phase shift) as two explicit control variables.

(v)

A discrete time control algorithm for SSPFC converters is presented. A variable sampling rate has been used to minimize storage and processing requirements for the controller.

(vi)

The proposed topology and control methods are applied to different resonant topologies.

(vii)

A variable structure controller based on the decoupled system model is proposed.

1.6 Thesis Organization This thesis is organized as follows: chapter 2 presents a new single-stage threelevel resonant ac/dc converter topology. A new variable frequency asymmetrical pulse width modulation controller is also proposed in this chapter. In chapter 3, a new variable frequency phase shift modulation controller is proposed as well as modification to the proposed converter topology is given. In both chapters, the different possible modes of operation and alternative converter topologies are also presented. Modelling of the proposed converters is given in chapter 4. This is based on a combination of averaging and multiple frequency modelling. The proposed technique gives a detailed converter model by explicitly separating the control variables. In chapter 5, a discrete time control technique for the three-level SSPFC converters is presented and finally in chapter 6, conclusions and summary of the thesis are given.

16

____________________________Chapter 2: Variable Frequency Asymmetrical Pulse Width Modulation

Chapter 2 Three-Level Converters with Variable Frequency Asymmetrical Pulse Width Modulation Control

2.1 Introduction It was concluded in chapter 1 that the problem related to the high voltage stress across the circuit components in single-stage power factor corrected ac-dc converters can be solved by using three-level topologies. Further, the added levels of switching circuits, in the three-level converters, can also give more degrees of freedom in control to shape the input and output waveforms. Three-level converters, therefore, have strong potential to be employed in the design of single-stage power factor corrected ac-dc converters. Three-level topologies have been utilized as power factor pre-regulators in twostage ac-dc converters using only one control variable [74-76]. A three-level, single-stage converter topology was presented in [77]. But this topology suffers with high input current distortion, high-voltage stress, and increased circulating current. The purpose of this chapter is, therefore, to develop a single-stage ac-dc converter topology for high power applications that has high efficiency and high input power factor. This objective is obtained by combining features of boost power factor corrected preregulators, resonant converters and three-level dc-dc converters, and simultaneous use of two control variables, namely; switching frequency and the duty ratio. A new single-

17

____________________________Chapter 2: Variable Frequency Asymmetrical Pulse Width Modulation

stage, three-level resonant ac-dc converter topology is conceived and presented. A variable frequency with asymmetrical pulse width modulation (VFAPWM) control technique is proposed. The operation, steady–state analysis, and control of the converter are studied. Performance characteristics of the converter are derived. Simulation and experimental results are presented. The proposed converter provides low input current distortion, low voltage stress, reduced circulating current, high conversion efficiency and well regulated output voltage. The chapter is organized as follows. In section 2 a new single-stage, power factor corrected (SSPFC) converter topology is proposed, its principle of operation is described and a new variable frequency asymmetrical pulse width modulation control method is proposed. Section 3 addresses the applicability of the proposed converter to operate in continuous conduction mode, and its limitations. In section 4, the steady state analysis is illustrated and the key design curves for the proposed converter are given. Sections 5 and 6 demonstrate the validity of the proposed methods through simulation and experimental results respectively. In section 7, different variations of the proposed topology are presented. Section 8 presents some concluding remarks.

2.2 Proposed Converter Topology and Principle of Operation 2.2.1 Proposed Topology The proposed converter topology integrates the operation of the boost power factor pre-regulator with the three-level resonant dc-dc converter. Figure 2.1 shows a three-level series-parallel LCC (Ls, Cs, Cp) resonant converter circuit with an input boost inductor (Lin) directly connected to the lower pair of the switches. The boost inductor can operate in either the continuous or discontinuous conduction mode. The dc-bus is 18

____________________________Chapter 2: Variable Frequency Asymmetrical Pulse Width Modulation

comprised of the two capacitors (Cb1) and (Cb2). These capacitors provide the necessary hold up time and greatly reduce the effect of low frequency ripples at the output voltage. If the capacitors are designed to have equal values and operate symmetrically, each should carry half the dc-bus voltage in the steady-state condition. The two diodes (Dc1) and (Dc2) serve to clamp the switch voltages to half that of the dc-bus. The series-parallel resonant converter is used due to the fact that it is able to operate in a buck-boost mode according to the applied switching frequency. This feature is required in order to be able to adjust the output voltage throughout the power line cycle. Other features that are characteristic to LCC resonant circuit are fast output regulation and low output voltage ripple as well as: input/output isolation; zero voltage switching; the use of an LC output filter, which results in an almost ripple free output voltage; and high conversion efficiency. Therefore, by designing the converter to operate close to its resonant frequency, high efficiency can be obtained for a wide range of input voltage and output load current. Other types of resonant circuits that have voltage step up and step down capabilities such as series resonant LLC can also be used for this application, which will be illustrated in a later section. The input filter is used to reduce the high frequency components of the input current, which is especially important in the case of discontinuous input inductor current operation. The output stage is comprised of a Schottky rectifier followed by an LC filter (Lo and Co) to smooth the output voltage waveform.

19

20 iLin

Figure 2.1 The proposed single stage three- level PFC circuit topology

Input rectifier

Output rectifier

____________________________Chapter 2: Variable Frequency Asymmetrical Pulse Width Modulation

____________________________Chapter 2: Variable Frequency Asymmetrical Pulse Width Modulation

2.2.2 Principle of Operation The stages of operation for this converter during one switching cycle are almost the same for continuous and discontinuous conduction modes with a few minor differences that are outlined in the following discussion. The different stages of operation of this converter can be described using the timing diagram shown in figure 2.2 and the equivalent circuits shown in figures 2.3 and 2.4. These stages of operation are given as follows: Stage 1 (t0
resonant circuit. •

In case of discontinuous conduction the input inductor current rises from zero to its peak value (ILin(max)).

•

In continuous conduction mode it rises from an initial minimum value (ILin(min)) to its maximum value (ILin(max)).

Note that the minimum and maximum values here indicate those during one switching cycle not absolute maxima and minima. It is also worth mentioning that the maximum values of input inductor current are different in continuous and discontinuous modes. This stage of operation ends at t1=DTs, where D is the duty ratio of the boost stage and Ts is the switching period.

21

____________________________Chapter 2: Variable Frequency Asymmetrical Pulse Width Modulation

Stage 2 (t1
Vbus 2

(the voltage across Cb2), the clamping diode Dc2 turns on and clamps the switch voltage to half the dc-bus voltage. The voltage across the resonant circuit decreases to zero and the resonant current circulates through switch S3 and clamping diode Dc2. at the end of this period the current in the boost inductor is also diverted to the upper switches, discharging their drain-source capacitors. vgs4 S4

t

vgs3 S3

t

vgs2 S2

t

vgs1 S1 vAB

t

Vbus/2 t

iL in

ILin(max){DCM}

-Vbus/2

IIin(max){CCM} ILin(min){CCM} t

DTs t1 t2 t3

dTs (1-D)Ts

t4 t5 t6

Ts Figure 2.2 Switching sequence during one switching cycle for VFAPWM control for the circuit proposed in figure 2.1. 22

____________________________Chapter 2: Variable Frequency Asymmetrical Pulse Width Modulation

Stage 3 (t2
Vbus . The inductor current continues to charge the dc-bus capacitors. The 2

resonant current contributes to the discharge of the switch capacitances and when they are fully discharged, both currents flow through the body diodes of switches S1 and S2 as the voltage across the resonant circuit rises to

Vbus . 2

Stage 4 (t3
Vbus , with 2

capacitor Cb1 delivering energy to the output through the resonant circuit. The current flowing through the switches in this case is the difference between the resonant current and the boost inductor current. Stage 5 (t4
Vbus (the voltage across Cb1), the 2

clamping diode Dc1 turns on and clamps the switch voltage to half the dc-bus voltage. The resonant circuit voltage again drops to zero, with the resonant current circulating through S2 and Dc1. •

For the case of discontinuous conduction mode, the inductor current will have decayed to zero at this point and the only current circulating in the circuit will be the resonant current.

•

For continuous conduction mode, the input inductor current will continue flowing through the body diodes of switches S1 and S2 until the end of stage 6.

23

____________________________Chapter 2: Variable Frequency Asymmetrical Pulse Width Modulation

Stage 6 (t5
Vbus . The resonant current is diverted to discharge the drain-source capacitors 2

of switches S3 and S4. When these capacitors are fully discharged, the body diodes of the switches start conducting. The cycle is then repeated with switches S3 and S4 being turned ON with zero voltage switching and the boost inductor starts charging in the new switching cycle. The following remarks can be made regarding the operation of the proposed converter: •

This operation scheme shows that the input voltage to the resonant circuit is not symmetrical. However, the dc-component of the current is blocked by the series capacitor and the higher frequency harmonics are attenuated by the resonant circuit. The current flowing in the resonant circuit can, therefore, be considered sinusoidal and has a frequency equal to the switching frequency ⎛⎜ f s = 1 ⎞⎟ . ⎟ ⎜ ⎝

•

Ts ⎠

Both input current and resonant current provide zero voltage switching for the upper switches, while only resonant current provides zero voltage switching for the lower switches.

•

The current stress on the lower switches is higher than those on the upper switches, since the lower switches carry the sum of the input and resonant currents while the upper switches carry their difference only. The voltage stress on all switches is equal to

Vbus . 2

24

____________________________Chapter 2: Variable Frequency Asymmetrical Pulse Width Modulation

S1

+

S1

Cb1

Vbus/2 Dc1 -

+

Cb1

Vbus/2 Dc1 -

Cs

Ls

Cs

Ls

N1

S2 Lin

Lin

Cp

Cp

iLin

iLin S3

S3

Dc2

V(rectified)

Dc2

V(rectified)

+ Cb2 Vbus/2

S4

+ Cb2 Vbus/2

S4

-

-

Stage 2

Stage 1

S1

+

S1

Cb1

Vbus/2 Dc1 -

+ Vbus/2 Dc1 -

Cs

Ls

Cb1

Cs

Ls

N1

S2

N1

S2

Lin

Lin Cp

iLin

Cp

iLin

S3 Dc2

V(rectified)

S3 Dc2

V(rectified)

+ Cb2 Vbus/2

S4

S4

-

+ Cb2 Vbus/2 -

Stage 3

Stage 4

S1

+ Vbus/2 Dc1 -

S1 Cb1

+ Vbus/2 Dc1 -

Ls

Cs

Cb1

Ls

N1

Cs

N1

S2

S2

Lin

Lin

Cp

Cp

iLin

N1

S2

iLin

S3 Dc2

V(rectified)

S4

S3 Dc2

V(rectified)

+ Cb2 Vbus/2

S4

-

+ Vbus/2

Cb2

-

Stage 6

Stage 5

Figure 2.3 Equivalent circuits for each operation stage for the converter shown in figure 2.1 operating in DCM 25

____________________________Chapter 2: Variable Frequency Asymmetrical Pulse Width Modulation S1

+

S1

Cb1

Vbus/2 Dc1 -

+

Cb1

Vbus/2 Dc1 -

Cs

Ls

Cs

Ls

N1

S2

N1

S2

Lin

Lin

Cp

Cp

iLin

iLin S3

S3

Dc2

V(rectified)

S4

Dc2

V(rectified)

+ Cb2 Vbus/2

+ Cb2 Vbus/2

S4

-

-

Stage 2

Stage 1

S1

+ Vbus/2 Dc1 -

S1

Cb1

+ Vbus/2 Dc1 -

Cs

Ls

Cb1

Ls

N1

S2

Cs

N1

S2

Lin

Lin Cp

iLin

Cp

iLin

S3 Dc2

V(rectified)

S4

S3 Dc2

V(rectified)

+ Cb2 Vbus/2

S4

+ Cb2 Vbus/2

-

-

Stage 3

Stage 4

S1

S1

+

Cb1

+

Cb1

Vbus/2 Dc1 -

Vbus/2 Dc1 Ls

Ls

Cs

Cs

N1

N1 S2

S2 Lin

Lin

Cp

Cp

iLin

iLin

S3

S3

S4

+ Vbus/2

Dc2

V(rectified)

Dc2

V(rectified)

Cb2

S4

+ Vbus/2

Cb2

-

-

Stage 6

Stage 5

Figure 2.4 Equivalent circuits for each operation stage for the converter shown in figure 2.1 operating in CCM 26

____________________________Chapter 2: Variable Frequency Asymmetrical Pulse Width Modulation

2.2.3 Control Method In the three-level resonant converter topologies, more than one variable can be used for the control purpose. In the proposed topology here, two different control variables are used simultaneously to control both the output voltage and the dc-bus voltage. Options for these control variables are: 1) switching frequency (fs) of the resonant converter to control the output voltage and 2) duty ratio (D) of the lower switches to regulate the dc-bus voltage. An asymmetrical pulse width modulation control in which the bottom switches have a duty ratio of D and the upper switches have a duty ratio of (1-D) is employed. The input voltage to the resonant circuit, therefore, is a variable frequency asymmetrical voltage. With this type of control, the dc-bus voltage can be adjusted to a desired level regardless of the load current. Figure 2.5 shows a block diagram of the proposed ac-dc converter including the power and control circuitry. Whether the input inductor current is measured as a feedback signal or not depends on the continuous or discontinuous conduction mode of converter operation. Another advantage of using two control variables is that the required change in the values of switching frequency and duty ratio is lower. This results in operating the converter closer to the resonant frequency of the circuit and still maintaining zero voltage switching under wide input voltage and load range. In discontinuous conduction mode the input current automatically follows the sinusoidal input voltage, whereas in continuous conduction mode active current control is required to sinusoidally shape the input current. However, continuous conduction mode has the advantage of having lower high-frequency ripples in the input current but requires complex control circuitry.

27

Figure 2.5 Block diagram of the proposed VFAPWM controller

____________________________Chapter 2: Variable Frequency Asymmetrical Pulse Width Modulation

28

____________________________Chapter 2: Variable Frequency Asymmetrical Pulse Width Modulation

2.3 Operation in Continuous Conduction Mode As mentioned in the previous section, continuous conduction mode of operation gives lower high-frequency ripples in the input current. In order to achieve such mode of operation, a current mode control method is required to get a sinusoidal input current in phase with the input voltage as compared to voltage mode control used for the case of discontinuous conduction mode. Therefore, an additional input current feedback signal is required. For the purpose of sinusoidal current the duty ratio of the boost converter must change continuously along the half-cycle of the input line voltage. Therefore, near the peaks of the input sinusoid it should be at its minimum, whereas, at the valleys of the input voltage signal a duty ratio very close to unity is required to boost the voltage to the required level at the dc-bus. On the other hand, having such a high duty ratio leads to a voltage waveform at the input of the resonant circuit taking the form shown in figure 2.6a. The harmonic analysis of this waveform shows that the input voltage to the resonant circuit will primarily be composed of a dc-component that will be blocked by the series resonant capacitor, whereas the fundamental ac-component at the switching frequency becomes very low. A higher duty ratio is needed the closer we get to the zero crossing of the input voltage sine wave, and thus the fundamental component of the input voltage to the resonant circuit is insufficient to provide the desired output voltage. This leads to undesirable high low frequency ripples, due to dips in the output load voltage at double the frequency of the input voltage. Therefore, the circuit gain has to be greatly increased to compensate, especially at lower input voltage and higher output load current. Nevertheless, relying only on increasing the circuit gain leads to an increase in the

29

____________________________Chapter 2: Variable Frequency Asymmetrical Pulse Width Modulation

circulating currents in the resonant circuit, leading to higher conduction losses. Therefore, a trade-off has to be made, in which some harmonic distortion is allowed in the input current, while still ensuring that the IEC standards of harmonic content are met. In this case, if the dc-bus voltage is set to a higher level at the lower line voltage levels, the required increase in the circuit gain is less and thus, the efficiency does not have to be severely penalized in order to maintain the output voltage level. The following changes have to be made in the circuit parameters in this case: •

The minimum limit of the dc-bus voltage has to be increased in order to accommodate the reduced input to output voltage conversion ratio without the need for an excessive increase in the voltage gain of the resonant circuit or excessive limitation of the duty ratio that would cause distortion in the input line current.

•

The maximum allowable duty ratio for the boost operation has to be limited (as an example, in this case it is set to attain a maximum value of 0.92)

•

The transformer turns-ratio must be increased to increase the converter voltage gain.

•

The ratio of the value of parallel to series resonant capacitors may also be increased to adjust the gain of the resonant circuit.

•

The input inductor Lin must be increased to ensure continuous conduction mode. An acceptable harmonic distortion level in the input current has to be kept into consideration while selecting the value of Lin. It is also worth noting that despite the increased asymmetry in the voltage input to

the resonant circuit, the voltage across the resonant capacitors remains balanced due to the fact that they are charged in series by the input inductor current and the energy discharged is equivalent to that of the shorter period of DTs or (1-D)Ts, because of the

30

____________________________Chapter 2: Variable Frequency Asymmetrical Pulse Width Modulation

blocking action of the series capacitor that prevents any dc current component from flowing through the resonant circuit. 400

vAB (V)

200

0

-200

-400

Ts

2Ts

Time (multiples of Ts) (a)

3Ts

VAB(n) (peak) (V)

300

200

100

0 fs

Frequency (multiples of fs) (b)

2fs

Figure 2.6 Illustrative example of input voltage to resonant circuit (vAB) at high duty cycle: (a) voltage waveform, (b) its harmonic content

31

____________________________Chapter 2: Variable Frequency Asymmetrical Pulse Width Modulation

2.4 Steady State Analysis The operation of the proposed converter at steady state can be separated into two main sections: the first is from the ac input to the dc-bus, and the second from the dc-bus to the output through the resonant circuit. The two variables controlling the operation in both sections are the duty ratio (D) and the switching frequency (fs). Dead times between switching transitions are neglected in the analysis as these times are very short compared to power transfer and freewheeling modes. The following subsections include a detailed description of the steady state operation for the whole converter in addition to key design and performance characteristics curves. All these derivations are still made under the assumption that the switching frequency is much higher than the power line frequency, and thus the input ac voltage can be considered constant during the switching cycle. 2.4.1 Analysis of the Boost Operation (from ac input to dc-bus) The operation in this part of the converter differs according to whether the input inductor is operating in the discontinuous or continuous conduction mode. 2.4.1.1 Discontinuous Conduction Mode For discontinuous conduction mode operation, the input current starts and end at zero, and at the end of energy storage time (stage 1 described in section 2.2.2) in one switching cycle it can be given as: Lin

diLin ( ch arg ing ) dt

= vs

(2.1)

k

i Lin ( ch arg ing ) (t = Dk Ts k ) = i Lin

peak

=

v s k Dk Ts

k

Lin

(2.2)

where, iLin: is the input inductor current, which is the rectified input current (is) i Lin = i s ,

(2.3)

32

____________________________Chapter 2: Variable Frequency Asymmetrical Pulse Width Modulation

vs: is the input ac supply voltage, D: is the duty ratio, Ts: is the switching period

Ts =

1 , such that, fs is the switching frequency, fs

Lin: is the input inductor, and subscript (k): denotes the switching cycle where calculation is made. During the freewheeling mode (stage 3 described in section 2.2.2), the current decays to zero, and is thus given by: Lin

di Lin ( disch arg ing ) dt

= vs

k

− Vbus ( k )

i Lin ( ch arg ing ) (t = ( Dk + d k )Ts k ) = 0 = iin

(2.4)

peak

−

(Vbus ( k ) − v s k )d k Ts

k

Lin

(2.5)

where, Vbus: is the dc-bus voltage (the sum of the voltages across capacitors Cb1 and Cb2) dkTs|k: is the time required for the current to decay to zero. By substituting from (2.2) in (2.5) dk can be expressed as: dk =

vs

k

Vbus ( k ) − v s

(2.6)

Dk k

Therefore, the average input inductor current over one switching cycle is given by: i Lin ( ave) k

( d k + Dk )Ts k ⎞ 1 ⎛⎜ Dk Ts k ⎟ i dt i dt = + Lin ( ch arg ing ) Lin ( disch arg ing ) ∫ ∫ 0 ⎜ ⎟ Ts k Dk Ts k ⎝ ⎠

(2.7)

Equation (2.7) can thus be solved as:

i Lin ave ) k

⎡ vs k =⎢ ⎢⎣ Lin f s

k

2 ⎛ vs k +⎜ ⎜ Vbus ( k ) − v s Lin f s k ⎝

(

)

k

⎞⎤ D 2 ⎟⎥ k ⎟⎥ 2 ⎠⎦

(2.8)

Therefore, the average value of the AC input current per switching cycle can be given by:

33

____________________________Chapter 2: Variable Frequency Asymmetrical Pulse Width Modulation

i s ( ave ) k

⎧⎡ v ⎪ s k = sgn( v s ) ⎨ ⎢ ⎪⎩ ⎢⎣ L in f s

k

2 ⎛ vs k ⎜ + ⎜ V bus ( k ) − v s L in f s k ⎝

(

)

k

⎞ ⎤ D 2 ⎫⎪ ⎟⎥ k ⎬ ⎟⎥ 2 ⎪⎭ ⎠⎦

(2.9)

where, sgn(vs): takes the values ± 1 according to the sign of the input voltage. From equations (2.8) and (2.9), it is apparent that the harmonic content of the input current depends on the switching frequency, duty ratio as well as the dc-bus voltage level. The distortion level is inversely proportional to the switching frequency, directly proportional to the square of the duty ratio and inversely proportional to the difference between the output and input voltages, that is, the higher the dc-bus voltage the lower the distortion. Figures 2.7 and 2.8 show the effect of the dc-bus voltage on the harmonic content of the input current. High and low switching frequencies are considered. From these two figures it can be seen that, as an example the dc-bus voltage can be chosen to be 400V for the case of an input voltage of 110V RMS and 600V for an input voltage of 220V RMS. The condition of discontinuous conduction mode can be guaranteed if the input inductor (Lin) satisfies the following condition [34]: Lin ≤

2 Vbus Ts D(1 − D) 2 2 Po

(2.10)

where, Po is the required output power. Figure 2.9 shows the applicable values for Lin in both high and low frequency cases, to supply an output power of 2.3kW. The curves represent the critical values of Lin, the inductor value has to be less than these critical values to maintain DCM. The selection of Lin influences the allowable range of duty ratio operation. That is, the higher the input inductor, the lower the permissible range of duty ratio swing can be made. As an example, in figure 2.9 (a) for Lin=1µH, the allowable D changes from 0.035 to 0.8. It is 34

____________________________Chapter 2: Variable Frequency Asymmetrical Pulse Width Modulation

also worth noting that the input inductor value has to be below the curve of the minimum input voltage range at full load, such that discontinuous conduction would be guaranteed even at the maximum input current. Based on the relations in figures 2.7 and 2.8, a dc-bus voltage range can be selected to range from 350V to 650 V for an input voltage range of 90Vrms to 265Vrms, therefore, (2.11)

Vbus ( ref ) = 1.22Vm + 195 where, Vbus(ref) is the reference value for the dc-bus voltage and Vm is the peak of the sinusoidal input waveform. 2.4.1.2 Continuous Conduction Mode

For continuous conduction mode, the input inductor has to satisfy the condition in (2.12) and the duty ratio are, therefore, related to the circuit voltages by equations (2.13) and (2.14) as follows: 2 Vbus Ts D(1 − D) 2 Lin > 2 Po

(2.12)

V bus 1 = V m sin ω l t 1 − D (t )

Therefore , D ( t ) = 1 −

(2.13)

V m sin ω l t V bus

(2.14)

where, the notation D(t) indicates that the duty ratio changes during the line frequency half-cycle. Using average current mode control, the whole converter is seen by the supply as an equivalent resistor Re whose value varies continuously with the sinusoidal cycle of the input voltage in such a way that the average power remains balanced between the input and the output [13]. For average current mode control, the value of Re is determined by the control signal generated from the dc-bus voltage and input current control signal.

35

____________________________Chapter 2: Variable Frequency Asymmetrical Pulse Width Modulation

0.4

Harmonic Current/Fundamental

Selected DC-bus Voltage

3rd Harmonic

0.3

IEC 1000-3-4 (3rd harmonic)

0.2

5th Harmonic IEC 1000-3-4 (5th harmonic)

0.1

IEC 1000-3-4 (7th harmonic) 7th Harmonic

IEC 1000-3-4 (9th harmonic)

9th Harmonic

0

200

300

400

500

600

DC-bus Voltage Vbus (V) (a)

Harmonic Current/Fundamental

0.4

3rd Harmonic

Selected DC-bus Voltage

0.3

IEC 1000-3-4 (3rd harmonic)

0.2

5th Harmonic

0.1

IEC 1000-3-4 (5th harmonic) IEC 1000-3-4 (7th harmonic)

7th Harmonic

IEC 1000-3-4 (9th harmonic)

9th Harmonic

0 200

300

400

500

600

DC-bus Voltage Vbus (V) (b) Figure 2.7 Effect of DC-bus voltage selection on the harmonic content of the input current for the case of Vs=90V RMS: (a) fs=750kHz, D=0.5, (b) fs=190kHz, D=0.5

36

____________________________Chapter 2: Variable Frequency Asymmetrical Pulse Width Modulation

18 IEC1000-3-2

IEC1000-3-4

16

IEC Standard Calculated

Harmonic Current Is-n(A)

14 12 3rd Harmonic

10 5th Harmonic

8

Selected DC-bus Voltage 3rd Harmonic

7th Harmonic 9th Harmonic

6

5th Harmonic 7th Harmonic 9th Harmonic

4 2 0 350

400

450

500

550

600

DC-bus voltage (V) (a)

650

700

750

18 IEC1000-3-4

16

IEC1000-3-2

IEC Standard Calculated

Harmonic Current (A)

14 12

3rd Harmonic

10

5th Harmonic 7th Harmonic

8

9th Harmonic Selected DC-bus Voltage

6

3rd Harmonic 5th Harmonic 7th Harmonic

4

9th Harmonic

2 0

350

400

450

500

550

600

650

700

750

DC-bus Voltage Vbus (V) (b) Figure 2.8 Effect of DC-bus voltage selection on the harmonic content of the input current for the case of Vs=220V RMS: (a) fs=750kHz, D=0.25, (b) fs=190kHz, D=0.25

37

____________________________Chapter 2: Variable Frequency Asymmetrical Pulse Width Modulation

20

f=700kHz, Vbus=600V

18

f=600kHz, Vbus=600V

16

f=1150kHz,Vbus=400V

f=1150kHz,Vbus=600V

f=700kHz, Vbus=400V

Lin (µH)

14

f=600kHz, Vbus=600V

12

Discontinuous Conduction Mode

10

Selected Lin= 1µH

8 6 4 2 1 0 0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

D (a) 70 f=250kHz, Vbus=400V f=250kHz, Vbus=600V f=170kHz, Vbus=400V f=170kHz, Vbus=600V

60

Lin (µH)

50

Discontinuous Conduction Mode

40

Selected Lin=5µH

30 20 10 5 0

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

D (b) Figure 2.9 Determination of Lin for discontinuous conduction mode and the range of duty ratio variation: (a) fs=750 kHz, (b) fs= 190kHz In this case the average input current in one switching cycle is given as in equation (2.15):

38

____________________________Chapter 2: Variable Frequency Asymmetrical Pulse Width Modulation

I L in ( ave

)k

=

V m sin ω l t

(2.15)

Re

The current ripple around the average in this case is given by: Δi Lin =

Vm sin ω l t DTs

(2.16)

2 Lin

And thus, the peak input current can be expressed as: i Lin

peak

= I Lin ( ave) k + Δi Lin =

Vm sin ω l t Re

+

v s k Dk Ts

k

2 Lin

(2.17)

which is much less than that in discontinuous conduction mode due to the larger value of input inductance needed to maintain continuous conduction. It is seen here that for ideal operation the input current should follow the sinusoidal input waveform better than the case of discontinuous conduction, but some design considerations, which will be discussed later in this section, lead to deviations from this ideal case. Referring to figure 2.5, this mode of operation requires an additional measurement of the input current in order to be able to operate with a current mode control. This additional feedback signal can be eliminated if a current estimation technique is used. This will consequently lead to a smaller size and more reliable converter. The duty ratio in this case ranges between a minimum value of Dmin =

Vbus − Vm and a maximum value of 1 occurring at the zero crossings of the Vbus

sinusoidal input voltage. As mentioned in section 2.3, the duty ratio should be limited to a certain value below 1 such that the power flow to the output remains sufficient to supply the load. Therefore, based on the selection of the dc-bus voltage, the range of variation of the duty ratio over the line frequency period is determined.

39

____________________________Chapter 2: Variable Frequency Asymmetrical Pulse Width Modulation

2.4.2 Analysis of the Resonant Circuit (from dc-bus to output)

Frequency analysis techniques are used to model the circuit in order to study the performance of the resonant circuit stage. For a series-parallel LCC resonant circuit the equivalent ac load is given by [56]:

π 2 ⎛ N1 ⎞

2

⎜ ⎟ RL 8 ⎜⎝ N 2 ⎟⎠

Rac =

(2.18)

where, N1 and N2 are the primary and secondary turns, respectively, of the isolating transformer. The input voltage to the resonant circuit is shown in figure 2.2. The Fourier series expansion of this waveform is given by:

v AB =

⎛ ∞ ⎛ sin α n 2Vbus (1 − 2 D ) 1 − cos α n sin ⎜⎜ 2πnf s t + tan −1 ⎜⎜ Vbus + ∑ n =1 nπ 2 ⎝ 1 − cos α n ⎝

where, α n = 2πn(1 − D)

⎞⎞ ⎟⎟ ⎟ ⎟ ⎠⎠

(2.19) (2.20)

fs is the switching frequency and,

n is the harmonic order.

The dc-component of vAB is blocked by the resonant circuit. Therefore, the transformer primary voltage can be given as: vP =

∞

∑

Vm Z P

n =1

Z tot

(n)

(n)

where, Z p ( n ) =

⎛ ⎞ ⎛ sin α n ⎞ ⎟⎟ + θ pn − θ n ⎟ sin ⎜⎜ 2πnf s t + tan −1 ⎜⎜ ⎟ ⎝ 1 − cos α n ⎠ ⎝ ⎠

Rac (1 − jnω s Rac C P )

(2.21)

(2.22)

(1 + n 2ω s Rac2 C P2 ) 2

⎛ Im(Z p ( n ) ) ⎞ ⎟ ⎟ Re( Z ) p ( n ) ⎝ ⎠

θ pn is the angle of Zp(n) such that θ pn = tan −1 ⎜⎜

40

(2.23)

____________________________Chapter 2: Variable Frequency Asymmetrical Pulse Width Modulation

and Z tot ( n ) =

⎛ Rac nω s Rac2 C P ⎜ nω s Ls − 1 − + j ⎜ nω s C s 1 + n 2ω s 2 Rac2 C P2 1 + n 2ω s2 Rac2 C P2 ⎝

⎞ ⎟ ⎟ ⎠

(2.24)

⎛ Im(Z tot ( n ) ) ⎞ ⎟ ⎟ Re( Z ) tot ( n ) ⎠ ⎝

θ n is the angle of Ztot (n) such that θ n = tan −1 ⎜⎜ The resonant circuit current is, therefore, given by: I r ( n) =

v AB

( n)

(2.25)

Z tot( n ) ∞

∴ ir = ∑ n =1

2Vbus nπ Z tot ( n )

⎛ ⎛ sin α n 1 − cos α n sin ⎜⎜ 2πnf s t + tan −1 ⎜⎜ ⎝ 1 − cos α n ⎝

⎞ ⎞ ⎟⎟ − θ n ⎟ ⎟ ⎠ ⎠

(2.26)

where θ n has a positive value as long as the circuit is operating in the above resonant mode. This leads to a resonant current (ir) lagging the input voltage to the resonant circuit (vAB), and that contributes to achieving zero voltage switching. The transformer primary current is given by: ⎛N i P = I o ⎜⎜ 2 ⎝ N1

⎞ ⎟⎟ sgn(v P ) ⎠

(2.27)

where, Io is the output load current. As mentioned earlier, the series-parallel resonant converter is found to be convenient for this application because of its ability to operate as a buck-boost converter according to the frequency variation. The transfer function of this circuit (transformer primary voltage Vp(s) to input voltage VAB(s)) in the Laplace domain can be given by:

Rac C s s VP ( s ) = 3 V AB ( s) Rac L s C s C P s + Ls C s s 2 + Rac (C s + C P ) s + 1

(2.28)

Therefore, for the cases where the duty ratio is farther away from 0.5 (either above or below this value), this may occur at the valleys of the input voltage waveform or in some

41

____________________________Chapter 2: Variable Frequency Asymmetrical Pulse Width Modulation

cases near its peak; the fundamental ac-component of the voltage input to the resonant circuit is reduced. Hence, a boosting action in the resonant circuit is required to maintain the output voltage within the required limits. Bases on (2.28) the frequency response of this circuit is shown in figure 2.10; and according to the derived steady state equations figures 2.11, 2.12 and 2.13 show the variation of the output voltage versus the switching frequency, load resistance, turns-ratio and duty ratio. 200 N1/N2=4 N1/N2=6 N1/N2=8 N1/N2=10

Magnitude (dB)

00 -200 -400 -600 -800

Phase (deg)

-1000 90

0

-90

-180 103

104

105 106 Frequency (rad/sec)

107

Figure 2.10 Frequency response of the series parallel resonant circuit with different transformer turns-ratios

42

108

____________________________Chapter 2: Variable Frequency Asymmetrical Pulse Width Modulation 60

90 f=190kHz f=200kHz f=210kHz f=220kHz f=230kHz f=240kHz

40

80 70 Output Voltage--Vo (V)

Output Voltage--Vo (V)

50

30

20

Vbus=650V

f=190kHz f=200kHz f=210kHz f=220kHz f=230kHz f=240kHz

Vbus=400V

60 50 40 30 20

10 10 0

0

0.1

0.2

0.3 0.4 Duty Cycle -- D

0.5

0.6

0

0.7

0

0.1

0.2

0.3 0.4 Duty Cycle -- D

0.5

0.6

0.7

Figure 2.11 Output Voltage Vo vs. duty ratio D for different values of switching frequency fs 100

70 D=0.05 D=0.15 D=0.25 D=0.5

80

50

Output Voltage-- Vo (V)

Output Voltage-- Vo (V)

60

D=0.05 D=0.15 D=0.25 D=0.5

90

Vbus=400V f=200kHz 40

30

70 60

Vbus=650V f=200kHz

50 40 30

20

20 10 10 0

1

2

3

4 5 6 7 Transformer Turns Ratio N1/N2

8

9

0

10

1

2

3

4 5 6 7 Transformer Turns Ratio N1/N2

8

9

10

Figure 2.12 Output Voltage Vo vs. turns-ratio for different values of duty ratio D 400

450

f=190kHz

f=190kHz f=200kHz

400

f=200kHz

350

f=210kHz

f=210kHz 300

f=230kHz Output Voltage-- Vo (V)

Output Voltage-- Vo (V)

f=220kHz

f=220kHz

350

f=240kHz

300

Vbus=400V D=0.5

250

200

f=230kHz f=240kHz

250 Vbus=650V D=0.2 200

150

150 100 100 50

50

0 10

20

30

40

50

60

70

80

90

0 10

100

20

30

40

50

60

70

80

90

% Load Current

% Load Current

Figure 2.13 Output Voltage Vo vs. load resistance for different values of switching frequency fs 43

100

____________________________Chapter 2: Variable Frequency Asymmetrical Pulse Width Modulation

2.5 Simulation Results A 2.3kW three-level half-bridge converter prototype is designed to investigate the effectiveness of the proposed methods. The converter parameters are given in Table 2.1. The resonant frequency is 170 kHz and the converter is always operated above resonance frequency to guarantee ZVS. These parameters are used for simulating the real circuit using PSIM6 software [105]. The simulation schematic is shown in appendix B. It is observed that, the harmonic content of the input current is higher in the case of continuous conduction mode at low input voltage due to the limitations placed on the duty ratio as mentioned in section 2.3. The values of simulated input power factor confirm this fact and are shown in figure 2.14. The minimum value obtained for the input power factor is 0.97 and the maximum value is 0.993. Figures 2.15 to 2.18 show the input voltage and input current, and the harmonic content of the input current for different operating conditions. The input current harmonics are compliant with the IEC1000-3-2 and IEC1000-3-4 harmonic standards for high and low input voltages respectively. Zero voltage switching is achieved for all switches. Figures 2.19 and 2.20 illustrate the current and voltage polarities of one of the upper and one of the lower switches, which guarantee ZVS. The high current peak for the upper switch is due to the energy discharge from the boost inductor Lin. This current peak is not present in the case of continuous conduction mode. The dc-bus voltage is maintained constant over the range of operation of the converter according to the ranges specified by equation (2.11) for DCM operation. For CCM the dc-bus voltage range is changed to 400-650 V for a 90-265 V RMS input range

44

____________________________Chapter 2: Variable Frequency Asymmetrical Pulse Width Modulation

in order to reduce the required gain of the resonant circuit to guarantee the desired output voltage level. Therefore the voltage range is given by:

V bus = 1 . 03V m + 269 . 3

(2.34)

Table 2.1: Converter parameters for VFAPWM operation

Parameter

Value

Input voltage Vs

90-265V RMS

Output voltage Vo

48V ± 2.5%

Output current Io

48A

Input filter

Inductor: 2 µH, capacitor: 4.4 µF

Input rectifier

MP506W-BPMS-ND

Switches S1, S2, S3, S4

IRFPS43N50K

Boost inductor Lin

5µH (DCM), 25 µH (CCM)

Dc-bus capacitors Cb1, Cb2

4700 µF

Clamping diodes Dc1, Dc2

RHRP1560

Series resonant inductor Ls

22 µH

Series resonant capacitor Cs

47 nF

Parallel resonant capacitor Cp

47 nF

Transformer turns-ratio N1/N2

2/1

Output rectifier

80CPQ150PbF

Output inductor Lo

20 µH

Output capacitor Co

470 µF

45

____________________________Chapter 2: Variable Frequency Asymmetrical Pulse Width Modulation

1

Vs=90V RMS

Input Power Factor

0.99

0.98

Vs=265V RMS

0.97

0.96

0

10

20

30

40

50

Load Current Io (A) (a) 1

Input Power Factor

Vs=265V RMS

0.99

0.98

0.97

Vs=90V RMS

0

10

20

30

40

Load Current Io (A) (b) Figure 2.14 Input Power Factor at different values of load current (a) for DCM (b) for CCM

46

50

____________________________Chapter 2: Variable Frequency Asymmetrical Pulse Width Modulation

150 vs (50V/div)

10 ms/div

50 is(50A/div) 0 -50

-100 -150

Time (msec) (a) 50

40

Is- n (peak) (A)

Input Voltage vs (V)& Input current is (A)

100

30 IEC1000-3-4 Limits 20

10

3rd 5th

0

0

250

250Hz/div th

7

500

750

1000

1250

Frequency (Hz) (b) Figure 2.15 For Vs=90V (a)Input Voltage (vs) and input line current (is) and (b) peak harmonic current content

47

____________________________Chapter 2: Variable Frequency Asymmetrical Pulse Width Modulation

400

Input voltage vs (V) & Input line current is (A)

vs(200V/div) 10ms/div

200

0

-200 10*is(200A/div) -400

Time (ms) (a)

17.5 15

Is- n (peak) (A)

12.5 IEC1000-3-2 Limits 10 7.5

5

3rd 5th

2.5 0

0

200Hz/div th

7

200

th

9 400

600

800

Frequency (Hz) (b) Figure 2.16 For Vs=265Vrms (a) Input Voltage (vs) and input line current (is) and (b) peak harmonic current content for operation under DCM 48

____________________________Chapter 2: Variable Frequency Asymmetrical Pulse Width Modulation

150

vs (50V/div) 100

Input voltage vs (V) & Input line current is (A)

is (50A.div) 50

10 ms/div

0 -50

-100 -150 Time (ms)

(a) 50

Is- n (peak) (A)

40

30 IEC1000-3-4 Limits

20

10

5th 0

0

200Hz/div

(b)

3rd 7th

200

9th 400

600

800

Frequency (Hz) (b) Figure 2.17 For Vs=90V (a) Input Voltage (vs) and input line current (is), (b) peak harmonic current content

49

____________________________Chapter 2: Variable Frequency Asymmetrical Pulse Width Modulation

Input voltage vs (V) & Input line current is (A)

400 10 ms/div

vs (200V/div) 200

10*is (200A/div)

0

-200

-400

Time (ms) (a) 14 12

Is- n (peak) (A)

10 8 6 IEC1000-3-2 Limits

4 2 0

3rd 5th

250

7th

250Hz/div

9th

500

750

1000

1250

Frequency (Hz) (b) Figure 2.18 For Vs= 265V RMS (a) Input Voltage (vs) and input line current (is), (b) peak harmonic current content for operation under CCM

50

____________________________Chapter 2: Variable Frequency Asymmetrical Pulse Width Modulation

400 vds1 (100V/div)

Switch voltage vds1 (V) & switch drain current id1 (A)

300

200

5.33µs/div id1 (100A/div)

100

0

-100 -200

Time (µs) (a) 400

Switch voltage vds4 (V) & switch drain current id4 (A)

300

vds4 (100V/div)

200 id4 (100A/div)

100

0 5.33µs/div

-100

Time (µs) (b) Figure 2.19 Switch voltage vds and switch current id to illustrate the Zero Voltage Switching: (a) for switch S1, (b) for switch S4 in DCM

51

____________________________Chapter 2: Variable Frequency Asymmetrical Pulse Width Modulation

400 vds1 (100V/dv)

Switch voltage vds1 (V) & switch drain current id1 (A)

300

200

100

id1 (100A/div)

0 5µs/div

-100

Time (μs) (a)

400

Switch voltage vds4 (V) & switch drain current id4 (A)

vds4 (100 V/div) 300

200

100 id4 (100A/div) 0 2.33µs/div -100

Time (μs) (b) Figure 2.20 Switch voltage vds and switch current id to illustrate the Zero Voltage Switching: (a) for switch S1 (b) for switch S4 in CCM

52

____________________________Chapter 2: Variable Frequency Asymmetrical Pulse Width Modulation

Figures 2.21 and 2.23 show the dc-bus voltage at different values of output load current for DCM and CCM, respectively. It illustrates that the voltage Vbus remains constant throughout the converter operation at the level determined by the input voltage. Finally, figure 2.22 the estimated conversion efficiency for the simulation model is given over the loading range of the circuit. A maximum estimated efficiency of 95% is obtained in the case of maximum input voltage in DCM operation. The CCM operation is a little less efficient than the DCM operation, with maximum estimated value of approximately 92.3%, due to the limitations placed on the duty ratio. This leads to the need for higher converter gain and thus higher circulating current in the resonant circuit and a higher range of switching frequency variation, which, consequently, forces the converter to operate further away from the optimum efficiency point.

700

DC-bus Voltage Vbus (V)

600

Vs=265 V RMS

500

Vs=90 V RMS

400

300

0

10

20

30

40

Load Current Io (A) Figure 2.21 DC bus Voltage at different values of load current for DCM

53

50

____________________________Chapter 2: Variable Frequency Asymmetrical Pulse Width Modulation

100

% Efficiency

Vs= 265 V RMS

90

Vs= 90 V RMS 80

70

0

10

20

30

40

50

40

50

Load Current Io (A) (a) 100 Vs=265 V RMS

% Efficiency

90

80 Vs= 90 V RMS 70

60

50

0

10

20

30

Load Current Io (A) (b) Figure 2.22 Converter efficiency at different values of load current (a) for DCM (b) for CCM

54

____________________________Chapter 2: Variable Frequency Asymmetrical Pulse Width Modulation

DC-bus Voltage Vbus (V)

700

600

Vs= 265 V RMS

500 Vs= 90 V RMS 400

300

0

10

20

30

40

50

Load Current Io (A) Figure 2.23 Dc-bus voltage at different values of load current for CCM

2.6 Experimental Results An experimental prototype of the converter, described in section 2.5, is built to demonstrate proof-of-concept and verify the analysis. The power circuit components and the input and output values are the same as those given in table 2.1. The circuit layout and a list of components with part numbers are given in appendix C. The control circuit is implemented by integrating the UC2823 PWM controller with some other external components including operational amplifiers, logic gates and a voltage controlled oscillator. A diagram of the controller implementation is shown in appendix C. The high

55

____________________________Chapter 2: Variable Frequency Asymmetrical Pulse Width Modulation

frequency isolation transformer has turns-ratio of 2:1:1 and its parameters are also given in appendix C. Near unity input power factor is achieved with harmonic content of the input current being compliant with the IEC limits and input current being in phase with the input voltage. Figures 2.24 and 2.25 show the input voltage and filtered current as well as the harmonic content of the input current for discontinuous and continuous conduction modes, respectively. In CCM at low input voltage with high input current it is seen that there exists more current distortion. This is due to the limitation on the duty ratio as explained in section 2.3 and similar to what appeared in the simulation results. However, the input current harmonics are still compliant with the IEC standards. The input power factor for different output current and input voltage is illustrated in figure 2.26 with a maximum input power factor of 0.99 being obtained. Zero voltage switching is achieved for all switches as illustrated in figure 2.27. As was previously mentioned, the circuit is operating above the resonant frequency to maintain a lagging resonant circuit current. The lagging resonant current, required to achieve ZVS is shown in figure 2.28 for different operating points. The dc-bus voltage is regulated as shown in figure 2.29. It is regulated to approximately 300V for an input voltage of 110V RMS and 200V for an input of 55V RMS. Conversion efficiency is illustrated in figure 2.30. A maximum efficiency of 93.7% is achieved for the case of 110V RMS input voltage. Figure 2.31 shows the narrow range of frequency variation for different values of output load current. A switching frequency of approximately twice the resonant frequency is required at the worst operating conditions of light-load and high input voltage. Finally, table 2.2 shows a brief summary of the obtained theoretical and experimental results, 56

____________________________Chapter 2: Variable Frequency Asymmetrical Pulse Width Modulation

indicating good correlation between them. The mismatch in the efficiency results can be attributed to the fact that the testing is done on a scaled value for voltages and currents (voltages and currents used in testing are 50% of the actual design values), which makes the circuit losses a more significant ratio of the output. Another reason is that the switches that are used for testing have a slightly higher ON resistance as compared to the optimum choice that is used in the analysis. The effect of these losses becomes more significant when the voltage is reduced and more current is being drawn by the converter. It should also be noted that the difference in efficiency between high and low input voltages is consistent with that obtained in the analysis. vs (50V/div)

is (5A/div)

2.5A/div 200Hz/div

Input current harmonics 10ms/div

(a) vs (50V/div)

is (1A/div)

0.5A/div 100Hz/div

Input current harmonics 10ms/div

(b) Figure 2.24 Experimental input voltage vs and filtered input current is current harmonics, input voltage 110 V (DCM) (a) high output current, (b) low output current 57

____________________________Chapter 2: Variable Frequency Asymmetrical Pulse Width Modulation

2A/div 100Hz/div

is (5A/div)

5ms/div

Input current harmonics

Figure 2.25 Experimental (a) input current is and (b) current harmonics, input voltage 55 V (CCM)

1

Vs=55V RMS

Input power factor

0.99

0.98

Vs=110V RMS 0.97

0.96 0

5

10

15

20

Load current Io (A) Figure 2.26 Experimental results: input power factor for different values of load current

58

25

____________________________Chapter 2: Variable Frequency Asymmetrical Pulse Width Modulation

vds1 (50V/div)

vds2 (50V/div)

vgs1 (20V/div)

vgs2(10V/div)

1μs/div

0.5μs/div (b)

(a) vds3 (50V/div)

vgs3 (10V/div)

vds4 (50V/div)

1μs/div

vgs4 (10V/div)

0.5μs/div (d)

(c)

Figure 2.27 vds and vgs to show zero voltage switching for the different switches (a) S1, (b) S2, (c) S3 and (d) S4

59

____________________________Chapter 2: Variable Frequency Asymmetrical Pulse Width Modulation

vab (60Vdiv)

vab (60Vdiv)

ir (2A/div)

ir (2A/div)

1μs/div

1μs/div

(a)

(b)

vab (60Vdiv)

vab (60Vdiv)

ir (5A/div)

ir (5A/div)

1.5μs/div

1.5μs/div

(c)

(d)

Figure 2.28 Resonant circuit voltage (vab) and current (ir) to illustrate lagging resonant current at different conditions figures from (a) to (d) are for increased effective loading (Higher D and lower fs)

DC-bus Voltage Vbus (V)

350

300

Vs = 110 V RMS 250

Vs = 55 V RMS 200

150

0

5

10

15

20

Output Current Io (A) Figure 2.29 Experimental results: dc-bus voltage for different values of load current 60

____________________________Chapter 2: Variable Frequency Asymmetrical Pulse Width Modulation

100

Vs=110 V RMS

% Efficiency

90

Vs=55 V RMS

80

70

60

0

5

10

15

20

25

Load Current Io (A) Figure 2.30 Experimental results: Conversion efficiency for different values of load current 380

Switching frequency fs (kHz)

340 Vs = 110 V RMS

300

260 Vs = 55 V RMS 220

180

0

5

10

15

20

Load Current Io (A) Figure 2.31 Switching frequency variation for different values of load current 61

25

____________________________Chapter 2: Variable Frequency Asymmetrical Pulse Width Modulation

Table 2.2 Comparison between theoretical and experimental results 55V

110V

Theoretical

Experimental

Theoretical Experimental

Output voltage

24 V

24 V

24 V

24 V

Input Power factor

0.992

0.99

0.987

0.982

Dc-bus Voltage

200 V

195 V

300 V

293 V

Conversion Efficiency

92.3%

90.2%

95%

93.7%

2.7 Derivation of Other Converter Topologies The proposed converter configuration can be applied to different resonant circuit topologies. The analysis in previous sections was performed based on an LCC resonant circuit. There are two main considerations to be taken into account when viewing other resonant topologies for SSPFC application: i.

Because of the asymmetrical nature of the voltage input to the resonant circuit, the resonant circuit has to contain a series capacitor to block the dc-component in the voltage vAB. Therefore, the LC parallel resonant converter is not suitable for this type of application.

ii.

The converter also has to provide both step up and step down capabilities. This is due to the fact that the fundamental high frequency ac-component of the voltage vAB is highly affected by the duty ratio D. Therefore, at both very low and very high values of D, vAB will have a higher dc-component and its fundamental component will be reduced and thus a step up operation will be required, whereas when D takes values around 0.5, a step down operation will 62

____________________________Chapter 2: Variable Frequency Asymmetrical Pulse Width Modulation

likely be required. Consequently, the LC-series resonant converter is unsuitable for this application because it only has step down characteristics. The series resonant converter also has the drawback of higher output voltage ripples due to the absence of an inductor in the output filter, which makes it less desirable when a fixed output voltage level is required. Therefore, a single-stage three-level half-bridge resonant LLC resonant converter can be considered for this application of SSPFC. The LLC resonant converter has the advantage of reduced part count as the parallel inductor can be included in the design of the high frequency transformer. In addition, that no output inductor filter is required due to the absence of a parallel capacitor. Another advantage of the LLC circuit is its fast transient response. The main problem with this circuit is the design complexity of the magnetizing inductance of the transformer to include the value of the parallel inductor. On the other hand, LCC circuit is easier to design but the part count increases. It also has an advantage over the LLC converter in terms of efficiency and lower circulating currents especially at lighter loads. It should be noted that the same restrictions of continuous conduction mode operation apply to any variation of the resonant topology. Equations (2.22), (2.24) and (2.28) can be modified to be: Z p(n) =

Z tot ( n ) =

nω s Rac L p (nω s L p + jRac )

(2.29)

( Rac2 + n 2ω s L2P ) 2

⎛ n 2ω s2 Rac L2P nω s Rac2 LP ⎜ nω s Ls − 1 + + j ⎜ nω s C s Rac2 + n 2ω s 2 L2P Rac2 + n 2ω s2 L2P ⎝

Rac L p C s s 2 VP ( s) = V AB ( s ) L s L p C s s 3 + Rac C s (Ls + L p )s 2 + L p s + Rac

63

⎞ ⎟ ⎟ ⎠

(2.30)

(2.31)

____________________________Chapter 2: Variable Frequency Asymmetrical Pulse Width Modulation

The frequency response of equation (2.31) is shown in figure 2.33. This response illustrates the step up/down capability of the LLC converter.

Figure 2.32 Three-level resonant LLC converter configuration used with VFAPWM control

64

____________________________Chapter 2: Variable Frequency Asymmetrical Pulse Width Modulation

20

N=4 N=5 N=6 N=7 N=8 N=9 N=10

Magnitude (dB)

0 -20 -40

Phase (deg)

-60 180

90

0

-90 5 10

6

10

7

10

9

8

10

10

Frequency (rad/sec) Figure 2.33 Frequency response of the LLC circuit for a 300 kHz design with different transformer turns ratios

2.8 Summary

In this chapter a new single-stage power factor corrected converter suitable for high power and universal input voltage range has been proposed. The converter is based on a three-level half-bridge resonant topology with an input inductor connected directly to the lower pair of the switches. This converter can operate with either continuous or discontinuous input current. A new variable frequency asymmetrical pulse width modulation controller is also proposed. Variable frequency control is used to regulate the

65

____________________________Chapter 2: Variable Frequency Asymmetrical Pulse Width Modulation

output voltage, whereas, asymmetrical pulse width modulation is used to regulate the dcbus voltage and to shape the input current. This method of control along with the converter topology lead to reduced circulating current and voltage stress resulting in a high input power factor and high efficiency for a wide range of input voltage and output load. Steady-state analysis and possible topological variations are also presented. Finally, simulation and experimental results prove the features of the proposed converter.

66

Chapter 3: Variable Frequency Phase Shift Modulation

Chapter 3 Three-Level Converters with Variable Frequency Phase Shift Modulation Control

3.1 Introduction The use of variable frequency APWM control for the proposed single stage PFC converter achieves the objective of regulating the three variables of interest: input current, output voltage and dc-bus voltage. One drawback of this method is the asymmetrical switching. Since the duty ratio decides the percentage of the switching period in which the lower pair of switches operates, therefore, the two legs of the converter operate for different time periods leading to an asymmetrical voltage being applied at the input of the resonant circuit. This consequently makes it necessary to have a series blocking capacitor in the resonant circuit in order to avoid core saturation of the high frequency isolation transformer. This series capacitor is, thus, exposed to a high negative dc-voltage level especially at high load current and at low input ac voltage (when a high value of duty ratio is needed), Similarly, during periods of low load current and high input ac voltage (when a very low duty ratio is required), a high positive dc-voltage appears across the series capacitor. Therefore, in this chapter a variable frequency phase shift modulation (VFPSM) controller is proposed in an effort to alleviate the problem of asymmetry while using the three-level resonant half-bridge converter topology. The objective is to obtain the 67

Chapter 3: Variable Frequency Phase Shift Modulation

required duty ratio that controls the dc-bus voltage and shapes the input current by means of phase shifting the gating signals of the switches, while maintaining the variable frequency operation as the output voltage regulation method. For this method of operation, the converter topology presented in chapter 2 has to be modified by adding an auxiliary circuit in order to maintain equal voltages across the two dc-bus capacitors. This chapter is organized as follows. In section 2 the modified SSPFC converter topology is presented, its principle of operation is described and a variable frequency phase shift modulation (VFPSM) control method is proposed. Section 3 describes the limitations posed on the operation of the proposed converter. In section 4 the steady state analysis, as well as the key design curves for the proposed converter are illustrated. Sections 5 and 6 demonstrate the validity of the proposed methods through simulation and experimental results respectively. In section 7 different variations of the proposed topology are presented. Section 8 gives a brief comparative study of the different singlestage three-level PFC topologies. Finally, section 9 presents some concluding remarks.

3.2 Converter Topology and Principle of Operation 3.2.1 The Modified Converter Topology The basic converter topology is based on the three-level half-bridge LCC resonant circuit with an input inductor (Lin) connected directly to the lower pair of switches, as was described in chapter 2. The resonant circuit is also set to operate above its resonance frequency to maintain zero voltage switching. The modification that is made to fit the VFPSM control is the addition of an auxiliary circuit as shown in Figure 3.1. The purpose of the auxiliary circuit is to maintain the voltage balance between the two capacitors forming the dc-bus. The auxiliary circuit consists of an auxiliary transformer with turns-

68

Chapter 3: Variable Frequency Phase Shift Modulation

ratio Naux1/Naux2= 1, in addition to diodes Daux1 and Daux2 connected to the dc-bus capacitors. As will be detailed in the following sub-section, the auxiliary circuit is designed to operate briefly at the beginning of every half-cycle to balance any difference in the dc-bus voltage. This circuit has to be designed to withstand the dc-bus voltage but it only processes fractional power, and therefore it carries low current. A flying capacitor (Cf) is also used to provide zero voltage switching for switches S1 and S4. The clamping diodes operate in a similar way to that described for variable frequency APWM control, therefore, switches S1 and S4 must be turned on and off before S2 and S3, respectively. The possibility of using other resonant circuits is also discussed in a subsequent section. 3.2.2 Principle of Operation The operation of this converter is similar in its concept to the one operating with VFAPWM control, but with some differences in both the input and resonant circuit sections. In VFPSM operation each switch is operated for 50% of the switching period. The duty ratio (D) is determined by the operational overlap of switches S3 and S4. In order to maintain voltage balance between switches, switches S1 and S4 should start and end operation before switches S2 and S3, respectively. The different stages of operation of this converter can be described using the timing diagram shown in figure 3.2 and the equivalent circuits shown in figure 3.3. Since phase shift is used to regulate the dc-bus voltage the duty ratio must satisfy the condition: D ≤ 0.5

(3.1)

The stages of operation are given as follows: Stage 1 (t0
69

Chapter 3: Variable Frequency Phase Shift Modulation

capacitor of S3 before S3 is turned on at zero voltage. In this case, the current in the boost inductor (Lin) increases. The voltage across the resonant circuit terminals vAB becomes (– Vbus/2). If there exists any unbalance between the voltages of the two dc-bus capacitors, such that VCb2> VCb1, the auxiliary circuit starts conducting through diode Daux1 to balance the voltage difference across the Cb1 and Cb2. Stage 2 (t1
70

Figure 3.1 The proposed topology of the three- level resonant SSPFC converter with auxiliary circuit

Input Rectifier

Auxiliary Circuit

Output Rectifier

Chapter 3: Variable Frequency Phase Shift Modulation

71

Chapter 3: Variable Frequency Phase Shift Modulation

vgs1 t vgs2

γ t

vgs3

t 180-γ

vgs4

t vAB

Vbus/2

t

-Vbus/2 iaux

DTs

DTs t

t0 t1

t2 t3

Ts/2

t4 t5 t6

t7 t8

t9

Ts/2

Figure 3.2 Switching sequence for frequency + Phase shift control for the proposed circuit shown in figure 3.1

72

Chapter 3: Variable Frequency Phase Shift Modulation

Stage 5 (t4VCb2 through the conduction of the auxiliary diode Daux2. For the boost inductor, if the current flowing through it has not decayed to zero, the inductor continues its discharge through the series connection of Cb1 and Cb2. Stage 6 (t5
Chapter 3: Variable Frequency Phase Shift Modulation

the resonant circuit thus, rises gradually in the negative direction until it reaches (–Vbus/2). Switch S3 can therefore, be turned ON with zero voltage switching and the converter operation returns to stage 1. These stages ensure high input power factor, zero-voltage switching for all switches, voltage stress across the switches limited to half dc-bus voltage, and voltage balance between the two dc-bus capacitors. There is also no dc-component in the resonant circuit voltage vAB, which leads to the reduction of voltage stress across the series capacitor and also allows the use of different topologies that do not include series blocking capacitor without saturating the isolation transformer. It is also worth noting that the discharge mode of the input inductor depends on both the duty ratio and the load current. There are three different cases that occur during the discharge of the input inductor as described below and shown in figure 3.4: •

Case 1: (Duty ratio <0.5 and full discharge happens through S3 only): In this case, the current decays to zero during the dead time of vAB and energy is transferred to Cb2. In this case the balancing circuit balances the voltage across Cb2 and that across Cb1.

•

Case 2: (Duty ratio <0.5 and discharge begins through S3, then continues through S1 &S2): In this case the inductor energy is discharged through Cb2 but it does not reach zero by the end of stage 4. Instead it reaches an intermediate value (i*Lin). Consequently, the remaining energy is discharged through the series combination of Cb1 and Cb2 forcing the current to decay to zero.

74

Chapter 3: Variable Frequency Phase Shift Modulation

(a) Stage 1

(b) Stage 2

(c) Stage 3 Figure 3.3 Equivalent circuits for each operation stage for the converter shown in figure 3.1: (a)-(c) illustrate stage (1) - stage (3) 75

Chapter 3: Variable Frequency Phase Shift Modulation

(d) Stage 4

(e) Stage 5

(f) Stage 6 Figure 3.3 (continued) Equivalent circuits for each operation stage for the converter shown in figure 3.1: (d)-(f) illustrate stage (4) - stage (6) 76

Chapter 3: Variable Frequency Phase Shift Modulation

(g) Stage 7

(h) Stage 8

(i) Stage 9 Figure 3.3 (continued) Equivalent circuits for each operation stage for the converter shown in figure 3.1: (g) - (i) illustrate stage (7) - stage (9) 77

Chapter 3: Variable Frequency Phase Shift Modulation iLin

iLin

iLin iLin(max)

iLin(max)

iLin(max)

i*Lin

t

t DTs d1Ts

DTs Ts/2

d1Ts d2Ts

Ts

Ts/2

(a)

(b)

t DTs

Ts

d2Ts Ts/2

Ts

(c)

Figure 3.4 Discharge modes of the input inductor (a) Case 1, (b) Case 2, (c) Case (3) •

Case 3: (D ≈ 0.5, and therefore all discharge occurs through S1 & S2): in this case all the boost inductor current is discharged through the series combination of Cb1 and Cb2 leading to no voltage imbalance between the two capacitors. Some other notes on the operation of this converter include: (1) the lower switches

are required to carry both input and resonant currents, whereas the upper switches only carry their difference; (2) the voltage across the resonant circuit is now symmetrical, thus eliminating the dc-voltage component across the series resonant capacitor; and (3) the clamping diodes Dc1 and Dc2 must be chosen such that they can carry the input current and resonant current during the freewheeling modes, since they operate for more significant periods of the switching cycle compared to VFAPWM converters that were presented in chapter 2. 3.2.3 Control Method In this control method, the switching frequency fs is used for output voltage regulation and the duty ratio (D) for dc-bus voltage regulation and input current shaping. The difference here lies in the method used to obtain (D). In this case, it is determined by

78

Chapter 3: Variable Frequency Phase Shift Modulation

the phase shift angle (γ) between the switching signals. The method used to obtain such signal is shown in figure 3.5. The output voltage controller is used to generate the switching frequency (fs) for the next switching cycle; this is then used to generate the saw tooth carrier signal. The dc-bus voltage control loop then produces the phase shift needed to produce the required duty ratio. The generated pulses are then isolated and conditioned to get the final gating signals. This operation is only designed for voltage mode control, so the input inductor is only operated in discontinuous conduction mode. Therefore, only two feedback signals are required: the output voltage and the dc-bus voltage. This makes the control circuit easy to implement. The drawback of this method is the existence of high current pulses, which require sufficient EMI filtering to prevent interference with other circuitry.

3.3 Restrictions on the Converter Operation Based on the converter topology and modes of operation presented in the previous section some restrictions apply to the operation of the converter. These restrictions are:

•

The converter must operate in discontinuous conduction mode because of the limitation on the duty ratio range. In order to achieve phase shift modulation, a maximum duty ratio of 50% is allowed.

•

Due to the reduction of the maximum allowable value of (D) as compared to VFAPWM operation, the gain of the resonant circuit must be increased so that the required output voltage level can be obtained at the lower end of the input voltage range. Therefore, the isolation transformer turns-ratio is increased and the ratio of parallel to series resonant capacitors (Cp/Cs) is also increased. These values have

79

Chapter 3: Variable Frequency Phase Shift Modulation

to be appropriately chosen so as not to have high a circulating current in the resonant circuit.

•

There are two design restrictions placed on the value of the dc-bus voltage: (i) The dc-bus voltage must be chosen in such a way that the input inductor is guaranteed to start discharging its energy as soon as switch S4 is turned OFF. Referring to figure 3.4, the discharge can start or occur completely through the lower capacitor. Therefore, the voltage across this capacitor has to be chosen such that it is higher than the maximum possible peak of the input sinusoidal supply voltage. Consequently, the total dc-bus voltage must satisfy the condition: Vbus > 2v s (max)

(3.2)

(ii) The choice of voltage should also be made to reduce the gain required by the resonant circuit by having a sufficiently high voltage to be transferred to the output.

3.4 Steady State Analysis Similar to the approach used for VFAPWM converters, the steady state analysis of the VFPSM converter can also be divided into two sections: the first from the input to the dc-bus and the second from the dc-bus to the output. The dead times between switching transitions are neglected here for clarity since they are much shorter than the switching period. The control variables are still referred to as switching frequency (fs) and the duty ratio (D). The duty ratio is related to the phase shift angle γ as follows:

γ = (1 − 2 D)π or D =

(3.3a)

1⎛ γ ⎞ ⎜1 − ⎟ 2⎝ π ⎠

(3.3b)

80

Chapter 3: Variable Frequency Phase Shift Modulation

The following two subsections show the steady state analysis of the converter in addition to some key design curves. 3.4.1 Analysis of the Boost Operation (from ac input to dc-bus)

The boost inductor is operated in DCM. Therefore, the maximum current at the end of the charging phase of the boost inductor is given by: i Lin ( ch arg ing ) (t = Dk Ts k ) = i Lin

peak

=

v s k Dk Ts

(3.4)

k

Lin

The shape of the boost inductor current during the discharging (freewheeling) mode depends on which discharge case takes place: Case 1: the full discharge takes place through capacitor Cb2 as shown in figure 3.4 (a).

Therefore, 0 = i

Lin

peak

⎛ V bus − vs ⎜ 2 ⎝ − L in

k

⎞d T ⎟ 1 k sk ⎠

(3.5)

where, d1kTs is the time required for the current to decay to zero, such that d 1k =

vs V bus

2

k

− vs

D

(3.6)

k

k

Therefore, the average value of the input current over the switching period is given by:

I L in ( ave

)k

⎡ ⎛ 2 ⎜ ⎢ V m sin ω l t V m sin ω l t = ⎢ + ⎜ L in f sk ⎜ ⎛ V bus ⎢ − V m sin ω l t ⎞⎟ L in f sk ⎜ ⎜ 2 ⎢⎣ ⎝ ⎠ ⎝

⎞⎤ ⎟⎥ D 2 k ⎟⎥ ⎟⎥ 2 ⎟ ⎠ ⎥⎦

(3.7)

Case 2: the discharge occurs first through Cb2 and continues through Cb1 and Cb2 as shown in figure 3.4 (b). In this case, the inductor is charged according to (3.4) for the period 0 ≤ t ≤ Dk Tsk then is discharged through Cb2 for a time period Dk Tsk ≤ t ≤ 0.5Tsk until it reaches a current level i*Lin given by:

81

Figure 3.5 A Simplified block diagram of the proposed VFPSM control closed loop system

Chapter 3: Variable Frequency Phase Shift Modulation

82

Chapter 3: Variable Frequency Phase Shift Modulation

i

* L in

= i Lin

peak

⎛ V bus − v ⎜ s 2 −⎝

⎞ ( 0 . 5 − D )T ⎟ k sk ⎠ L in

k

(3.8)

and thus d1k = 0.5 − Dk

(3.9)

The discharge process is then continued through the series connected Cb1 and Cb2 and the current decays to zero according to the relation:

0 = i L*in −

(V

− vs

bus

k

)d

2k

T sk

(3.10)

L in

where, d2kTs is the time required for the current to decay to zero, such that

(v

d 2k =

s k

− (0 . 5 − D k )V bus

(

2 V bus − v s

)

k

)

(3.11)

The average input current over the switching cycle is thus given as: ⎡Dk vs k Vbus − vs k + ⎤ 1 ⎢ ⎥ I Lin (ave)k = 1 ⎢ 4Lin f sk Vbus − vs k v −V (0.5 − Dk ) Vbus (0.5 − Dk ) + vs k (2Dk − 0.5) ⎥ ⎢⎣ 2 s k bus ⎥⎦

(

(

)

) (

)(

)

(3.12)

Case 3: D ≈ 0.5, therefore all discharge occurs through the series connected Cb1 and Cb2, in this case d1k ≈ 0 and there will only be d2k and the current will decay to zero as follows:

0 = i Lin

peak

and d 2 k =

−

(V bus − v s

vs

k

) d 2 k T sk

(3.13)

L in Dk ≈

k

V bus − v s

k

(

vs

k

2 V bus − v s

k

)

(3.14)

Finally the average input current per switching cycle takes a form similar to that obtained in case 1 and also to the VFAPWM control method:

I L in ( ave

)k

2 ⎡ v ⎛ vs s ⎜ = ⎢ + ⎜ (V bus − v s )L in f sk ⎢⎣ L in f sk ⎝

83

⎞⎤ D 2 k ⎟⎥ ⎟⎥ 2 ⎠⎦

(3.15)

Chapter 3: Variable Frequency Phase Shift Modulation

The value of the input inductor must still satisfy the condition given in equation (2.10) to guarantee discontinuous conduction and, consequently, automatic current shaping. In order to guarantee inductor energy discharge as soon as switch S4 is turned off, the voltage across each capacitor has to be above 375V, which is the peak voltage for the case of maximum input. Therefore, the dc-bus voltage reference is set to range from 400800V corresponding to an input voltage of 90-265Vrms i.e.

Vbus ( ref .) = 1.62vin (max .) + 194.3

(3.16)

Figures 3.6 and 3.7 show the harmonic content of the input current versus the dcbus voltage for the different discharge modes. It should be noted that in the case of discharge mode 1 the highest distortion of the input current occurs due to the discharge being forced by only half the dc-bus voltage and conversely, the distortion is at a minimum during the case of discharge mode 3 because of the higher potential discharging the inductor. Equations (3.7), (3.11) and (3.15) also prove that no dc-bus voltage less than twice the peak sinusoidal input can be used as it would generate singular points with extremely high currents. 3.4.2 Analysis of the Resonant Circuit

The steady state analysis of the resonant circuit to output can again be made using the frequency domain analysis. Since the circuit analyzed is also an LCC resonant circuit with an LC output filter, only the operational differences are presented here to avoid repetition. The ac equivalent resistance Rac is represented in the same form given in equation (2.18). The circuit voltage vAB according to figure 3.2 is expanded to its harmonic components in the form:

84

Chapter 3: Variable Frequency Phase Shift Modulation

v AB =

∑

( − 1)

n −1 2

n , odd

V bus sin (n π D ) sin (2π nf s t ) 2 nπ

(3.17)

As mentioned earlier, equation (3.17) does not contain a dc-component due to the symmetry of the VFPSM operation. The resonant current is, therefore, given by:

ir =

∑

( − 1)

n −1 2

n , odd

V bus sin (n π D ) sin (2π nf s t − θ n ) 2 n π Z tot ( n )

(3.18)

and the primary transformer voltage would therefore be:

vp =

∑

n , odd

( − 1)

n −1 2

V bus sin (n π D ) Z P ( n ) 2 n π Z tot ( n )

sin (2π nf s t + θ pn − θ n )

(3.19)

Figures 3.8 and 3.9 show the resonant circuit gain for different values of transformer turn ratios as well as for different ratios of parallel to series capacitance values (Cp/Cs). Figures 3.10 and 3.11 show the variation of the output voltage with different circuit variables. It is noted that a higher turns-ratio and higher capacitor ratio is needed to generate the required output voltage as compared to the case of VFAPWM.

85

Chapter 3: Variable Frequency Phase Shift Modulation

Harmonic Current/Fundamental

0.35 0.3

3rd Harmonic

0.25 IEC 1000-3-4 (3rd Harmonic)

0.2 0.15 0.1 0.05 0300

IEC 1000-3-4 (5th Harmonic)

5th Harmonic

IEC 1000-3-4 (7th Harmonic)

7th Harmonic

350

400

450

500

550

DC bus Voltage (V) (a) 2.5

IEC 1000-3-2 (3rd Harmonic)

Harmonic Current(A)

2 3rd Harmonic

1.5

IEC 1000-3-2 (5th Harmonic)

1

IEC 1000-3-2 (7th Harmonic)

9th Harmonic 5th Harmonic

0.5

7th Harmonic

0 300

350

400

IEC 1000-3-2 (9th Harmonic)

450

DC bus Voltage (V) (b)

500

550

Harmonic Current/Fundamental

0.35 0.3

3rd Harmonic

0.25

IEC 1000-3-4 (3rd Harmonic)

0.2

0.15 IEC 1000-3-4 (5th Harmonic)

0.1

IEC 1000-3-4 (7th Harmonic) 5th Harmonic 7th Harmonic

0.05 0

300

350

400 450 DC bus Voltage (V)

500

550

(c) Figure 3.6 Effect of dc-bus voltage selection on the harmonic content of the input current for the case of Vs= 90V RMS, fs=180 kHz: (a) Discharge case 1, (b) Discharge case 2, (c) Discharge case 3 86

Chapter 3: Variable Frequency Phase Shift Modulation

2.5

IEC 1000-3-2(3rd Harmonic) 3rd Harmonic

Harmonic Current(A)

2 1.5

IEC 1000-3-2(5th Harmonic)

1

IEC 1000-3-2(7th Harmonic) 5th Harmonic

0.5

7th Harmonic

0

800

850

DC-bus Voltage (V) (a)

2.5

950

IEC 1000-3-2(3rd Harmonic) 3rd Harmonic

2

Harmonic Current(A)

900

1.5 IEC 1000-3-2(5th Harmonic)

1 IEC 1000-3-2(7th Harmonic) 5th Harmonic 7th Harmonic

0.5 0

800

850

900

950

DC-bus Voltage (V) (b) 2.5

IEC 1000-3-2(3rd Harmonic)

Harmonic Current(A)

2 1.5 IEC 1000-3-2(5th Harmonic)

1

IEC 1000-3-2(7th Harmonic) 3rd Harmonic

0.5 5th Harmonic

0

800

850

7th Harmonic

900

950

DC-bus Voltage (V) (c) Figure 3.7 Effect of dc-bus voltage selection on the harmonic content of the input current for the case of Vs= 265V RMS, fs= 180 kHz: (a) Discharge case 1, (b) Discharge case 2, (c) Discharge case 3 87

Chapter 3: Variable Frequency Phase Shift Modulation

0

Cp/Cs=2

-20 -40 -60 -80 -100 90 N1/N2=2 N1/N2=3 N1/N2=4 N1/N2=5 N1/N2=6 N1/N2=7 N1/N2=8

0

Phase (deg)

Magnitude (dB)

20

-90 -180 3 10

4

10

5

10

6

7

10

Frequency (rad/sec)

8

10

10

Figure 3.8 Gain and phase plots for the resonant circuit for different transformer turn ratios

Magnitude (dB)

50 Cp/Cs=1 Cp/Cs=2 Cp/Cs=3 Cp/Cs=4 Cp/Cs=5

N1/N2=6

0

-50

Phase (deg)

-100 90 0 -90

-180 3 10

10

4

10

5

10

6

Frequency (rad/sec)

10

7

Figure 3.9 Gain and phase plots for the resonant circuit for different values for the ratio Cp/Cs 88

10

8

Chapter 3: Variable Frequency Phase Shift Modulation

Output Voltage Vo (V)

100

fs=170kHz N1/N2=6 Cp/Cs=2

80

Vbus=800V fs=188kHz

60

40

fs=205kHz fs=222kHz fs=240kHz

20

0 0

0.1

0.2

0.3

0.4

0.5

Duty ratio (D) (a) 50

fs=170kHz

Cp/Cs=2 N1/N2=6

Output Voltage Vo(V)

40

Vbus=400V fs=188kHz

30

fs=205kHz

20

fs=222kHz

10

0

0

fs=240kHz

0.1

0.2

0.3

0.4

Duty ratio (D) (b)

Figure 3.10 Variation of the output voltage (a) with duty ratio and frequency for Vbus=800V, (b) with duty ratio and frequency for Vbus=400V,

89

0.5

Chapter 3: Variable Frequency Phase Shift Modulation

120 N1/N2=6

Output Voltage Vo (V)

Vbus=800V

80

fs=170 kHz

40

0

1

2

3

Cp/Cs

4

5

4

5

(a) 70 N1/N2=6 Vbus=400V

Output Voltage Vo (V)

fs=170 kHz

50

30

10 0 1

2

3

Cp/Cs (b) Figure 3.11 Variation of the output voltage (a) with capacitor ratio with Vbus=800V, (b) with capacitor ratio with vbus=400V

90

Chapter 3: Variable Frequency Phase Shift Modulation

3.5 Simulation Results A 2.3 kW, 48V three-level half-bridge converter with an input voltage range of 90-265V RMS is designed to verify the effectiveness of the proposed methods. The resonant frequency of the converter is chosen to be 170 kHz and it is operated above the resonance frequency to maintain ZVS. The converter parameters, which are also used for experimentation listed in table 3.1. The PSIM6 [105] simulation schematic is given in appendix B. A transformer turns-ratio of 6:1:1 and parallel to series capacitor ratio of 2 are chosen. The dc-bus voltage is regulated according to equation (3.16) The input current and its harmonic components indicate compliance with the IEC 1000-3-2 and the IEC 1000-3-4 standards. Nevertheless, the harmonic content and input power factor, shown in figure 3.12 are slightly lower than the VFAPWM control in discontinuous mode. This is due to limitations on the duty ratio and the different current pulse shape depending on the discharge mode, which contains higher harmonic components. Minimum harmonic content occurs in the case of input voltage of 90V RMS and maximum load current, where the duty ratio approaches 0.5 leading to discharge mode 3 as discussed in section 3.3. The input current and voltage for minimum and maximum input voltages are presented in figures 3.13 and 3.14. Table 3.1: Converter parameters for VFPSM operation

Parameter

Value

Input voltage Vs

90-265V RMS

Output voltage Vo

48V ± 2.5%

Output current Io

48A

Input filter

Inductor : 2 µH, capacitor: 4.4 µF

Input rectifier

MP506W-BPMS-ND

91

Chapter 3: Variable Frequency Phase Shift Modulation

Table 3.1 (Continued): Converter parameters for VFPSM operation

Parameter

Value

Switches S1, S2, S3, S4

IRFPS43N50K

Boost inductor Lin

5µH (DCM)

Dc-bus capacitors Cb1, Cb2

4700 µF

Clamping & auxiliary diodes Dc1, Dc2,

RHRP1560

Daux1, Daux2 Series resonant inductor Ls

18µH

Series resonant capacitor Cs

47nF

Parallel resonant capacitor Cp

94nF

Flying capacitor Cf

22nF

Main transformer turns-ratio N1/N2

6/1

Auxiliary transformer turns-ratio

1/1

Naux1/Naux2 Output rectifier

80CPQ150PbF

Output inductor Lo

25µH

Output capacitor Co

470 µF

1

Input power factor

0.99

Vs= 90V RMS

0.98

0.97

Vs= 265V RMS

0.96

0.95

0

10

20

30

40

50

Load current Io (A) Figure 3.12 Simulation results: input Power Factor at different values of output load current 92

Chapter 3: Variable Frequency Phase Shift Modulation

150

Input voltage vs (V) & input current is (A)

vs (50V/div)

100 10ms/div

50 is (50A/div.)

0

-50

-100

-150

Time (ms) 50

Peak harmonic input currents (A)

40

30 IEC 1000-3-4 Limits 20 200 Hz/div

3rd

10

5th

7th

Figure 3.13 Simulation results: (a) Input Voltage (vs) and filtered input 0 current (is) at Vsrms=90Vrms (b) harmonic content of the input current 0

200

400

Frequency (Hz)

600

800

Figure 3.13 Simulation results: (a) Input Voltage (vs) and filtered input current (is) at Vs=90V RMS (b) harmonic content of the input current 93

Chapter 3: Variable Frequency Phase Shift Modulation

400

Input voltage vs (V) & input current is (A)

10ms/div vs (200V/div)

200

10 × is (200A/div.)

0

-200

-400

Time (ms) (a) 14

Peak harmonic input currents (A)

12

10 IEC 1000-3-2 Limits

8

6

100Hz/div 3

4

rd

5th

2 0

0

100

200

7th

300

400

500

Frequency (Hz) (b) Figure 3.14 Simulation results: (a) Input Voltage (vs) and filtered input current (is) at Vs=265V RMS, (b) Harmonic content of input current 94

600

Chapter 3: Variable Frequency Phase Shift Modulation

Zero voltage switching is achieved for all switches. Figure 3.15 shows the switch voltage and current for one of the upper and one of the lower switches to illustrate ZVS, and figure 3.16 shows the resonant circuit voltage and current at maximum load current (small phase shift angle) and in case of small load current (large phase shift angle) to illustrate the lagging resonant current and its zero crossing for a wide range of operation. 600

Drain source voltage vds (V)& Drain current id (A)

vds1(200V/div)

1.5μs/div

400

id1(200A/div)

200

0 Charge transfer through Cf

-200

Drain source voltage vds (V)& Drain current id (A)

Time (μs) 400

(a)

300

vds3(100V/div)

200

100 id3(100A/div)

0 1.5μs/div -100

Time (μs) (b) Figure 3.15 Simulation results: switch drain source voltage and drain current to illustrate zero voltage switching in (a) S1 & (b) S3 95

Chapter 3: Variable Frequency Phase Shift Modulation

Resonant circuit voltage vAB (V) & resonant current ir (A)

400 vAB (200V/div) 200

0

-200 ir (200A/div) 4 μs/div

-400

Time (μs) (a)

Resonant circuit voltage vAB (V) & resonant current ir (A)

600 400

vAB (200V/div)

200

ir (200A/div)

0

-200 3 μs/div -400

Time (μs) (b)

Figure 3.16 Simulation results: Resonant circuit voltage (vAB) and resonant current (ir) to illustrate ZVS for: (a) full load, (b) 20% of full load

96

Chapter 3: Variable Frequency Phase Shift Modulation

The dc-bus voltage is maintained at the required regulation level regardless of the output load current as shown in figure 3.17. Finally, figure 3.18 gives the estimate converter efficiency for different loading conditions. It should be noted that the maximum efficiency in this case is lower than that obtained using VFAPWM (92% compared to 95%). This is attributed to the increased conduction losses resulting from the higher circulating current caused by the higher circuit gain, which causes the converter to operate further away from the resonant frequency and thus, the higher circulating current. The efficiency is further penalized at low output load current.

850

DC-bus Voltage Vbus (V)

750 Vs=265 V RMS 650

550 Vs=90 V RMS 450

350

0

10

20

30

40

Load Current Io (A) Figure 3.17 Simulation results: dc-bus Voltage (Vbus) at different values of output load current

97

50

Chapter 3: Variable Frequency Phase Shift Modulation

95 Vs=265 V RMS

% Efficiency

85

Vs=90 V RMS

75

65

55

0

10

20

30

40

50

Load Current Io (A) Figure 3.18 Simulation results: Estimated converter efficiency at different values of output load current

3.6 Experimental Results An experimental prototype of the converter described in section 3.4 is implemented to demonstrate proof-of-concept and to verify the proposed methods. The power circuit components and the input and output values are the same as those given in table 3.1. The circuit layout and a list of components with part numbers is given in appendix C. The control circuit is implemented by integrating the UC3875 phase shift controller with some other external components, including operational amplifiers, logic gates and a voltage controlled oscillator. The controller implementation is shown in appendix B. The high frequency isolation transformer is made of a 3 winding transformer with turns-ratio 6:1:1. The parameters of the transformer are also given in appendix B.

98

Chapter 3: Variable Frequency Phase Shift Modulation

High input power factor is achieved with harmonic content of the input current being compliant with the IEC standards and input current being in phase with the input voltage. Figure 3.19 and 3.20 show the input voltage and filtered current as well as the harmonic content of the input current for the maximum and 20% output load current respectively. The obtained values for input power factor and harmonic distortion show good agreement with the simulation results and theoretical analysis. The input power factor for different output current and input voltage is illustrated in figure 3.21 with a maximum input power factor of 0.988 being obtained. Zero voltage switching is achieved for all switches as illustrated in figure 3.22. As was previously mentioned, the circuit is operating above the resonant frequency to maintain a lagging resonant circuit current. The lagging resonant current, required to achieve ZVS is shown in figure 3.23 for two different operating points. The dc-bus voltage is regulated as shown in figure 3.24. It is regulated to approximately 400V for an input voltage of 110V RMS and 200V for an input of 55V RMS. Conversion efficiency is illustrated in figure 3.25. A maximum efficiency of 91.2% is achieved for 110V RMS input voltage. A narrow range of frequency variation for different values of output load current. A switching frequency of approximately 3.5 times the resonant frequency is required at the worst operating conditions of light-load and high input voltage. Finally, table 3.2 shows a brief summary of theoretical and experimental results, indicating good correlation between them. Similar to the results obtained in chapter 2, the mismatch in the efficiency results can be attributed to the fact that the testing is done on a scaled value for voltages and currents and that the switches that are used for testing have a slightly higher ON resistance as compared to the optimum choice that is used in the analysis. The effect 99

Chapter 3: Variable Frequency Phase Shift Modulation

of these losses becomes more significant when the voltage is reduced and more current is being drawn by the converter.

vs (50V/div)

is (5 A/div)

2.5A/div 200Hz/di v

Input current harmonics 10ms/div

Figure 3.19 Experimental input voltage vs and filtered input current is current harmonics, input voltage 110 V RMS at high output current

vs (50V/div)

is (1A/div)

0.5A/div 100Hz/div

Input current harmonics 10ms/div

Figure 3.20 Experimental input voltage vs and filtered input current is current harmonics, input voltage 110 V RMS at 20% full load condition

100

Chapter 3: Variable Frequency Phase Shift Modulation

1

Input power factor

Vs=55V RMS

0.99 0.98 Vs=110V RMS

0.97 0.96 0.95 10

20

30

40

50

60

70

80

90

100

% Load Current Figure 3.21 Experimental results: input power factor versus output load current vds2 50V/div

vds1 50V/div

vgs2 10V/div

vgs1 10V/div

1 μs/div

1μs/div (b)

(a) vds3 50V/div

vds4 60V/div

vgs3 10V/div

vgs4 10V/div

1μs/div

1 μs/div

(c)

(d) Figure 3.22 vds and vgs to show ZVS for (a) S1, (b) S2, (c) S3 and (d) S4 (Higher trace in all figures is vds) 101

Chapter 3: Variable Frequency Phase Shift Modulation

vAB (50 V/div)

vAB (50 V/div) ir (1 A/div)

ir (5 A/div)

2 μs/div

1 μs/div

(b) (a) Figure 3.23 Resonant circuit voltage (vab) and current (ir) to illustrate lagging resonant current at different conditions (a) high output load current, (b) low output load current

550

DC-bus Voltage --Vbus (V)

450 Vs=110V RMS

350

250

150 10

Vs=55V RMS

20

30

40

50

60

70

80

90

100

% Load current Figure 3.24 Experimental results: dc-bus voltage versus output load current

102

Chapter 3: Variable Frequency Phase Shift Modulation

90

Vs=110V RMS

80

% Efficiency

Vs=55V RMS

70

60

50 10

20

30

40

50

60

70

80

90

100

% Load Current Figure 3.25 Experimental results: Conversion efficiency versus output load current

Table 3.2 Comparison between theoretical and experimental results 55V

110V

Theoretical

Experimental

Output voltage

24 V

24 V

24 V

24 V

Input Power factor

0.99

0.988

0.983

0.98

Dc-bus Voltage

200 V

193 V

400 V

402 V

Conversion Efficiency

90.3%

88.7%

92%

91.2%

103

Theoretical Experimental

Chapter 3: Variable Frequency Phase Shift Modulation

3.7 Derivation of Other Converter Topologies As was the case for VFAPWM control, different resonant topologies can be used according to the required application as shown in figure 3.26. Due to the symmetry of the voltage vAB increased number of resonant circuits can be used without core saturation of the transformer and with reduced voltage stress on the series elements of the circuit. Resonant LCC and LC are preferred from the standpoint of the output voltage ripple, since the use of an LC output filter minimizes these ripples. The LC circuit provides higher gain at the expense of increased circulating current compared to the LCC topology. LLC circuits can also be used where a magnetically integrated transformer and shunt inductor can provide higher power density, at the expense of a higher output ripple.

3.8 A Comparative View of the Different proposed SSPFC Topologies In this section, a comparative summary of the proposed three-level single-stage power factor correction topologies is presented. Two control methods previously presented are compared. Table 3.3 summarizes the differences between the performance of these two control methods. The values of input power factor obtained by each of these methods for an LCC three-level resonant converter are shown in figure 3.27. The best input power factor is obtained using VFAPWM in CCM with high input voltage where there is very little restriction on the duty ratio, but in all case the power factor is above 0.97 and harmonic content is compliant with the IEC standards.

104

Chapter 3: Variable Frequency Phase Shift Modulation

Used with LC and removed if LLC circuit is used

Figure 3.26 Three-level resonant converter configurations used with VFPSM control Table 3.3 Comparison between the two controllers

Input Current Resonant circuits

VFAPWM CCM or DCM LCC, LLC

VFPSM DCM LC, LCC, LLC

Auxiliary Circuit Maximum Efficiency

No 95%

Yes 92%

Vbus Switch Voltage Stress

400-650Vdc 200-325V

400-800Vdc 200-400V

Dmaximum

~ 0.92 (CCM)

0.5

105

Chapter 3: Variable Frequency Phase Shift Modulation

The dc-bus voltage is well regulated using the proposed control methods. The level of the input voltage is chosen depending on the required gains and range of operation of the converter. Figure 3.28 shows the dc-bus voltages for the different control methods. Finally, the application of different resonant circuits is studied and the different efficiencies are illustrated in figure 3.31. The LCC converter operating with VFAPWMDCM is the most efficient. 1

Power Factor

0.99

0.98

0.97 0.96

10

20

30 40 50 60 % Load Current (a)

70

80

90

100

1

Power Factor

0.99

0.98

0.97

0.96

10

20 30 40 50 60 70 80 90 100 % Load Current (b) Figure 3.27 Input power factor versus output current for (a) Vs=265V RMS, (b) Vs=90V RMS 106

Chapter 3: Variable Frequency Phase Shift Modulation

900

VFPS Vin=265Vrms

800 700 VFPWM Vin=265Vrms

600 500

VFPWM-CCMor VFPS Vin=90Vrms

400

VFPWM-DCM Vin=90Vrms

300 200 100 0 0

10

20

30

40

50

60

70

80

90

100

Figure 3.28 Dc-bus voltage of different configurations under different input voltage versus output current

100 95 90 85 80 75 LCC-VFPWM-DCM 70

LCC-VFPWM-CCM LCC-VFPS-DCM

65

LLC-VFPS-DCM LLC-VFPWM-DCM

60

LLC-VFPWM-CCM LC-VFPS-DCM

55 10

20

30

40

50

60

70

80

90

100

Figure 3.29 Efficiency of different converter configurations versus output current

107

Chapter 3: Variable Frequency Phase Shift Modulation

3.9 Summary In this chapter a variable frequency phase shift modulation control method for single-stage three-level resonant PFC converters is proposed. In this method, the power circuit is modified by the adding an auxiliary voltage balancing circuit to equalize the voltage across the two dc-bus capacitors. The VFPSM control reduces the stress across the series capacitor and allows the use of different topologies without a series blocking capacitor. It also makes it possible to use a self-driven synchronous rectifier at the output. Due to the limitation on the duty ratio the converter can only be operated in DCM. Simulation and experimental results are presented to prove the validity of the proposed method. The proposed converter and controller are suitable for multiple kilowatt applications, because of the reduced component stresses and high efficiency.

108

___________________________________Chapter 4: Multiple Frequency Average Modelling

Chapter 4 Multiple Frequency Average Modelling of Three-Level Resonant Single-Stage PFC Converters

4.1 Introduction This chapter presents modelling approach for single-stage three-level PFC converters. A state-space approach based on combined averaging and multiple frequency modelling is used. This method allows the separation of both the duty ratio and the switching frequency as two explicit control variables. The model can describe the operation of the converter, including the effect of non-linear and parasitic component. It can also be simplified to a decoupled linearized model for small-signal analysis, and provides good prediction of the steady state behaviour. This model is applied to converters operating with either variable frequency APWM or variable frequency PSM control.

4.2 Modelling Issues of SSPFC Converters As discussed in the previous chapters, the operation of the SSPFC converters must cope with two sets of dynamic behaviours. The first is the slow dynamic of the input current and dc-bus voltage (if it exists in the converter), and the second is the fast dynamic response required at the output side. Modelling approaches for this type of converter have been primarily based on averaging and/or small-signal analysis

109

___________________________________Chapter 4: Multiple Frequency Average Modelling techniques. The resulting performance equations, therefore, do not express both input and output dynamics adequately in the same model [77, 80, 81 and 82]. Another modelling issue is that many of the models are developed for certain applications or modes of operation. That is, the model is able to express the performance of discontinuous conduction mode only or continuous conduction mode only; in other cases the model can only represent either constant or variable frequency operation. A multi-frequency modelling approach of dc-dc converters was presented in [83], but this modelling approach ends up using time varying circuit parameters to solve for the different frequency components. An added difficulty for the single-stage power factor corrected converter proposed in chapters 2 and 3 arises because of the use of two control variables in the two separate control loops: the switching frequency and duty ratio (or phase-shift angle). Thus, the objective of the analysis presented in this chapter is to develop a systematic state-space modelling procedure that is suitable for expressing the different system dynamics in the converter as well as separating the two control variables explicitly in order to facilitate better understanding of system performance and better controller design. This model is also able to express the non-linearities as well as parasitic component effects in the converter such that it can be used at a high complexity level if needed and can also be simplified to an approximate decoupled model if only an approximation of the system performance is needed. In this chapter a state space model based on combined averaging [13] and multiple frequency (AMF) modelling [84, 85] is proposed. In section 4.3, a description of the modelling procedure is presented. This is followed by the application of this

110

___________________________________Chapter 4: Multiple Frequency Average Modelling procedure to SSPFC converters operating with variable frequency APWM and variable frequency PSM control in sections 4.4 and 4.5 respectively. Small signal approximation is presented in section 4.6 and a description of a decoupled model in section 4.7. Finally, A controller design example using the decoupled model is presented in section 4.8. Finally, section 4.9 gives a concluding summary.

4.3 The Proposed Averaging Multiple Frequency Model In order to develop the AMF state space model the following procedure is followed: 1. The modes of operation of the converter, through a switching cycle, are determined along with their respective equivalent circuits. 2. The state-space model for each mode of operation is derived and they are combined using weighted averaging to get the average system model. 3. The state-space variables are broken down into their harmonic components. This gives an infinite series for each variable, but based on the knowledge of the system the significant harmonics can be chosen to reduce the computational effort. 4. These harmonic components are differentiated to obtain a new set of state variables. 5. The magnitudes of the harmonic components thus become the new state variables and are substituted in the original average model by equating harmonic components for each state variable. These steps lead to the derivation of a full order detailed large signal model that, in most cases, will be a non-linear model. Both the fast and slow transients are expressed in

111

___________________________________Chapter 4: Multiple Frequency Average Modelling the same model. Some of the important characteristics of this method can be noted as follows: •

A significant feature of this method is that it does not include state variables that change at different rates at steady state when using standard averaging. Instead, using the magnitudes of the harmonic components as the new state variables means that the state variables end up at a dc steady-state value for all system variables. These components can then be added up to reconstruct the original signal.

•

Although this model can be highly non-linear and complex depending on the circuit structure, it can then be linearized around a specific operating point or even simplified to a decoupled model with the fast and slow dynamics separated.

•

This procedure is also indifferent to whether the converter is operating in continuous or discontinuous conduction mode.

•

The use of the harmonic series for the state variables leads to a straightforward means of extracting the switching frequency as an explicit variable in the model in addition to the duty ratio (or phase shift angle) for any mode of operation.

Throughout the following analysis these assumptions are made to simplify the analysis: •

The dead times between switching transitions are ignored since they are much smaller than the switching period.

•

Initially, the ac equivalent resistance of the output of the resonant circuit is used for the purpose of clarity, then the effects of transformer, output rectifier and parasitic elements is introduced.

112

___________________________________Chapter 4: Multiple Frequency Average Modelling •

The main switching modes of operation are considered in the average model for the VFAPWM-CCM, VFAPWM-DCM or VFPSM control methods.

4.4 Modelling VFAPWM Converters Depending on the chosen mode of operation the modelling of the converters with VFPWM control is performed for the cases of: 1. Continuous input current conduction mode. 2. Discontinuous input current conduction mode. 4.4.1 Case 1: Continuous Conduction Mode For the case of CCM the operation of the converter can be divided into two main periods that are illustrated in figure 4.1: (i)

when lower switches (S3 & S4) are on, 0 ≤ t ≤ DTs and

(ii) when upper switches (S1 & S2) are on, DTs ≤ t ≤ Ts . Therefore, the state space model is given by equations (5.1) & (5.3) for cases (a) and (b) of figure 4.1 respectively.

(a) Input inductor charging:

⎫ v di Lin = s ⎪ dt L in ⎪ dV 1 ⎪ = 0 ⎪ dt dV 2 ir ⎪ = ⎪⎪ dt Cb2 ⎬ −1 di r = (V 2 + v cs + v P )⎪ dt Ls ⎪ dv cs ir ⎪ = ⎪ dt Cs ⎪ vp dv P i ⎪ = r − ⎪⎭ dt CP R ac C P

All state variable notations are defined on the circuit diagram in figure 4.1 and

113

(4.1)

___________________________________Chapter 4: Multiple Frequency Average Modelling

R ac =

π 2 ⎛ N1 ⎞

2

⎜ ⎟ RL 8 ⎜⎝ N 2 ⎟⎠

(4.2)

is the ac equivalent resistance of the output of the resonant circuit [56].

⎫ ⎪ ⎪ ⎪ dV 1 i Lin − i s = ⎪ dt C b1 ⎪ ⎪ i dV 2 = Lin ⎪ dt Cb2 ⎪ (b) Input inductor discharging: ⎬ di r 1 (V1 − v cs − v P )⎪⎪ = dt Ls ⎪ dv cs ir ⎪ = ⎪ dt Cs ⎪ vp dv P ir ⎪ = − ⎪ dt CP R ac C P ⎭ v − V1 − V 2 di Lin = s dt L in

(4.3)

Combining equations (4.1) and (4.3) the overall average model of the converter over the switching period is given by:

114

___________________________________Chapter 4: Multiple Frequency Average Modelling

Figure 4.1 Equivalent Circuits for the two stages of operation (CCM) (a) input inductor charging, (b) input inductor discharging

115

___________________________________Chapter 4: Multiple Frequency Average Modelling

(1 − D) (1 − D) ⎤ ⎡ 0 0 0 0 − − ⎥ ⎢ Lin Lin ⎥ ⎢ (1 − D) (1 − D) ⎢ 0 0 0 0 ⎥ ⎡iLin ⎤ ⎡ 1 ⎤ − ⎡iLin ⎤ ⎢ C ⎥ ⎢ ⎥ C b1 ⎢ V ⎥ ⎢ Lin ⎥ ⎢ V ⎥ ⎢ b1 ⎥ D 1 ⎢ 1 ⎥ ⎢ (1 − D) 0 0 0 0 ⎥⎢ ⎥ ⎢ 0 ⎥ d ⎢V2 ⎥ ⎢ Cb2 Cb2 ⎥ ⎢V2 ⎥ + ⎢ 0 ⎥ v = ⎢ ⎥ 1− D −D −1 − 1 ⎥ ⎢ ir ⎥ ⎢ ⎥ s dt ⎢ ir ⎥ ⎢ 0 ⎢ ⎥ 0 0 ⎢ Ls Ls Ls Ls ⎥⎥ ⎢v ⎥ ⎢⎢ ⎥⎥ ⎢ vcs ⎥ ⎢ cs ⎢ ⎥ ⎢0⎥ ⎢ ⎥ ⎢ 1 ⎥ 0 0 0 0 0 ⎢⎣ vP ⎥⎦ ⎢⎣ vP ⎥⎦ ⎥ ⎢ ⎣⎢ 0 ⎦⎥ Cs ⎥ ⎢ 1 −1 ⎥ ⎢ 0 0 0 0 CP CP Rac ⎥⎦ ⎢⎣ ……... (4.4) The next step is to decompose each of the state variables into their dominant harmonic components. Note that ωs indicates the angular switching frequency and ωl indicates the angular power line frequency. This decomposition is found to be adequate due to the fact that higher harmonic orders are blocked by the resonant circuit. The rectified input voltage can thus be given as:

vs =

2V m

π

+

∑

n = 2 , 4 , 6 ,...

4V m

π

n cos( n ω l t ) n2 −1

(4.5),

where n is the harmonic order.

v sgn(vP ) = v p = Similarly, P

2v p (max)

π

+ ∑

n = 2 , 4 , 6 ,...

4vP (max)

π

n cos(nωs t ) n2 − 1

(4.6)

on the output rectifier side. The input voltage to the resonant circuit (vAB) in terms of V1 and V2 and referring to figure 2.2 can be given as:

116

___________________________________Chapter 4: Multiple Frequency Average Modelling

v AB ≈ V 1 (1 − D ) − V 2 D +

V1 + V 2

π +

sin( 2 π (1 − D )) cos ω s t

V1 + V 2

π

[1 − cos(

2 π (1 − D )) ]sin ω s t + ... ..…… (4.7)

The effect of higher harmonics is very small and can be neglected here. Finally the state variables are expressed in terms of their dominant harmonics as follows:

ir = ir ( dc) + irq cos ωst + ird sin ωst + irql cos 2ωl t + irdl sin 2ωl t vcs = vcs ( dc) + vcsq cos ωst + vcsd sin ωst + vcsql cos 2ωl t + vcsdl sin 2ωl t vP = vP ( dc) + vPq cos ωst + vPd sin ωst + vPql cos 2ωl t + vPdl sin 2ωl t V1 = V1( dc) + V1ql cos 2ωl t + V1dl sin 2ωl t + V1q cos ωst + V1d sin ωst V2 = V2( dc) + V2 ql cos 2ωl t + V2dl sin 2ωl t + V2q cos ωst + V2 d sin ωst iLin = iLin( dc) + iLinql cos 2ωl t + iLindl sin 2ωl t + iLinq cos ωst + iLind sin ωst

⎫ ⎪ ⎪⎪ ⎬ ⎪ ⎪ ⎪⎭

…… (4.8) Only even harmonic components appear in the expansion of the low frequency variables since they are all on the dc side of the rectifier and thus have waveforms symmetrical about the vertical axis. The following step is to differentiate the variables in equation (4.8). The resulting expansion is as shown in equation (4.9). By substituting (4.5) to (4.9) into (4.4) and equating harmonic components taking into consideration the average power balance between input and output we can reformulate the model in (4.4) as shown in (4.10)- (4.18):

117

___________________________________Chapter 4: Multiple Frequency Average Modelling

i&r = i&r ( dc ) + i&rq cos ω s t − i rq ω s sin ω s t + i&rd sin ω s t + i rd ω s cos ω s t

⎫ ⎪ ⎪ ⎪ v&cs = v&cs ( dc ) + v&csq cos ω s t − v csq ω s sin ω s t + v&csd sin ω s t + v csd ω s cos ω s t ⎪ ⎪ ⎪ v& P = v& P ( dc ) + v& Pq cos ω s t − v Pq ω s sin ω s t + v& Pd sin ω s t + v Pd ω s cos ω s t ⎪ ⎪ ⎪ V&1 = V&1( dc ) + V&1ql cos 2ω l t − 2ω lV1ql sin 2ω l t + V&1dl sin 2ω l t + 2ω lV1dl cos 2ω l t ⎪ ⎪ ⎬ & & + V1q cos ω s t − V1q ω s sin ω s t + V1d sin ω s t + V1d ω s cos ω s t ⎪ ⎪ ⎪ V&2 = V&2 ( dc ) + V&2 ql cos 2ω l t − 2ω lV2 ql sin 2ω l t + V&2 dl sin 2ω l t + 2ω lV2 dl cos 2ω l t ⎪ ⎪ + V&2 q cos ω s t − ω sV2 q sin ω s t + V&2 d sin ω s t + ω sV2 d cos ω s t ⎪ ⎪ ⎪ i&Lin = i&Lin ( dc ) + i&Linql cos 2ω l t − 2ω l i Linql sin 2ω l t + i&Lindl sin 2ω l t + 2ω l i Lindl cos 2ω l t ⎪ ⎪ + i&Linq cos ω s t − i Linq ω s sin ω s t + i&Lind sin ω s t + i Lind ω s cos ω s t ⎪⎭ …... (4.9)

(i) High frequency state variables

dir ( dc ) dt

=

[

1 (1 − D)V1( dc ) − DV2 ( dc ) − vcs ( dc ) − v P ( dc ) Ls

]

⎡V1d + V2 d ⎤ sin(2π (1 − D)) − vcsq − v Pq ⎥ ⎢ dt ⎣ π ⎦ ⎤ dird 1 ⎡V1q + V2 q = ω s irq + (1 − cos(2π (1 − D))) − vcsd − v Pd ⎥ ⎢ dt Ls ⎣ π ⎦ dirql 1 = −2ω l irdl + (1 − D)V1ql − DV2 ql − vcsql − v Pql dt Ls dirq

= −ω s ird +

1 Ls

[

]

dirdl 1 = 2ω l irql + [(1 − D)V1dl − DV2 dl − vcsdl − v Pdl ] dt Ls

118

⎫ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎬ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪⎭

(4.10)

___________________________________Chapter 4: Multiple Frequency Average Modelling

dv cs ( dc )

=

dt dv csq dt

i r ( dc ) Cs

= −ω s v csd +

i rq Cs

i dv csd = ω s v csq + rd Cs dt dv csql dt

= − 2ω l v csdl +

i rql Cs

dv csdl i = 2ω l v csql + rdl dt Cs dv p ( dc ) dt dv pq

=

ir ( dc ) Cp

−

⎫ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪⎪ ⎬ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎭⎪

v p ( dc )

C p Rac irq v p(q) = −ω s v pd + − dt C p C p Rac dv pd v p(d ) i = ω s v pq + rd − dt C p C p Rac dv pql irql v pql = −2ωl v pdl + − dt C p C p Rac dv pdl v pdl i = 2ωl v pql + rdl − dt C p C p Rac

(4.11)

⎫ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎬ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎭

(4.12)

(ii)Low frequency state variables

2Vm 1 − D V1( dc ) + V2( dc ) − dt πLin Lin diLinql 8Vm 1− D V1ql + V2 ql = − 2ωl iLindl − dt Lin 3πLin diLindl 1− D (V1dl + V2dl ) = 2ωl iLinql − dt Lin diLinq 1− D 1− D V1q − V2 q = −ωs iLind − dt Lin Lin diLind 1− D 1− D V1d − V2 d = ωs iLinq − dt Lin Lin diLin( dc )

=

(

)

(

Therefore

⎫ ⎪ ⎪ ⎪ ⎪ ⎪⎪ ⎬ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪⎭

)

2 2 2 2 2 i Lin = i Lin ( dc ) + i Linql + i Lindl + i Linq + i Lind

119

(4.13)

(4.14)

___________________________________Chapter 4: Multiple Frequency Average Modelling dV 1( dc )

=

dt dV 1ql dt

[

1− D i Lin ( dc ) − i r ( dc ) C b1

= − 2ω l V1dl +

]

[

1− D i Linql − i rql C b1

dV 1dl 1− D [i Lindl − i rdl ] = 2ω l V1ql + dt C b1 dV 1q dt

= − ω s V1 d +

[

1− D i Linq − i rq C b1

dV 1d 1− D [i Lind − i rd ] = ω s V1 q + dt C b1

Therefore , V1 =

]

]

⎫ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪⎪ ⎬ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎭⎪

(4.15)

V12( dc ) + V12ql + V12dl + V12q + V12d

(4.16)

Similarly for the second capacitor dV

2 ( dc )

dt dV

2 ql

dt

=

D 1− D i Lin ( dc ) + i r ( dc ) C b2 C b2

= − 2 ω l V 2 dl +

D 1− D i Linql + i rql C b2 C b2

dV 2 dl D 1− D i Lindl + i rdl = 2 ω l V 2 ql + dt Cb2 C b2 dV

2q

dt

= − ω sV 2 d +

D 1− D i Linq + i rq C b2 C b2

dV 2 d D 1− D i Linq + i rq = ω sV 2 q + dt C b2 C b2

⎫ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪⎪ ⎬ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪⎭

(4.17)

and thus, V2 = V22( dc ) + V22ql + V22dl + V22q + V22d

(4.18)

It should be noted that the all newly derived state variables are now dc variables whose values represent the peak values of the sinusoidal components to which the original variables were decomposed, instead of having variables that are at different harmonic frequencies as was the case in equation (4.4).

120

___________________________________Chapter 4: Multiple Frequency Average Modelling

Equations (4.10) to (4.18) show that both control variables: (D) and (ωs) now appear explicitly in the system model. It is worth noting that the value (ωl), which is the angular frequency of the line voltage, is dealt with as a constant (either 314 rad/sec or 377 rad/sec depending on the operating line frequency.) The effects of the low frequency dynamics on the high frequency variables can also be modeled and vice versa, as it is apparent the model in this case is non-linear due to the multiplication of the control variables and the state variables. If the effect of any parasitic component needs to be accounted for, it is simply inserted in the state equations. Steady state operation of the converter can be predicted by setting the derivatives of the state variables to zero and calculating the values of these variables for the different operating points. Figure 4.2 shows the system steady state response for different values of frequency and duty ratio for a 2.3kW, 48V, 170 kHz converter. These values agree with those obtained from the steady state analysis in chapter 2.

Output Voltage Vo (V)

100 80 60 40 20 0 1 2 0.5

1.5

Duty ratio D

1

0 0.5

Switching frequency ωs (rad/s)

Figure 4.2 Open loop steady state output voltage at different values of control inputs

121

× 10 6

___________________________________Chapter 4: Multiple Frequency Average Modelling 4.4.2 Case 2: Discontinuous Conduction Mode

For the case of DCM the three main modes of operation are as follows: (i)

Switches S3 and S4 are ON; this occurs in the interval 0 ≤ t ≤ DTs

(ii)

The second set of dynamic equations occurs when switches S1 and S2 are ON with the input inductor discharging its energy. This occurs during the time period DTs ≤ t ≤ (D + d )Ts

(iii) At the end of this period the value of the input inductor current iLin should reach zero. Following this period the third stage takes place with switches S1 and S2 still in the ON state. The duration of this period is d2Ts. taking into consideration that:

d2 = 1 − D − d

(4.19)

The three modes of operation are shown in figure 4.3. The first two modes of operation are similar to equations (4.1) and (4.3) for the case of CCM with (D) in (4.1) retaining the same definition and (1-D) in (4.3) replaced by (d). Therefore, the modified equations are given in equations (4.20) and (4.21). Mode (iii) that is shown in figure 4.3(c) is given by equation (4.22).

122

___________________________________Chapter 4: Multiple Frequency Average Modelling ⎫ ⎪ L in ⎪ ⎪ dV 1 = 0 ⎪ dt ⎪ dV 2 ir ⎪ = ⎪ dt C b2 ⎪ ⎬ di r −1 (V 2 + v cs + v P )⎪ = dt Ls ⎪ ⎪ dv cs i ⎪ = r ⎪ dt Cs ⎪ vp dv P i ⎪ = r − ⎪⎭ dt CP R ac C P di Lin dt

=

vs

(4.20)

v − V1 − V 2 ⎫ di Lin = in ⎪ dt L in ⎪ dV 1 i − ir ⎪ = Lin ⎪ dt C b1 ⎪ dV 2 i = Lin ⎪⎪ dt Cb2 ⎬ 1 di r (V1 − v cs − v P )⎪ = dt Ls ⎪ dv cs ir ⎪ = ⎪ dt Cs ⎪ vp dv P i ⎪ = r − ⎪⎭ dt CP R ac C P

(4.21)

⎫ ⎪ ⎪ ⎪ ⎪ ⎪ dV 2 ⎪ = 0 ⎪ dt ⎪ ⎬ di r 1 (V 1 − v cs − v P )⎪ = dt Ls ⎪ ⎪ dv cs i ⎪ = r dt Cs ⎪ ⎪ v dv P ir p ⎪ = − ⎪⎭ dt CP R ac C P di Lin = 0 dt dV 1 − ir = dt C b1

(4.22)

Equations (4.20), (4.21) and (4.22) can be combined to obtain an average model in the form:

123

___________________________________Chapter 4: Multiple Frequency Average Modelling

[x& ] = A [x] + B eq

vin

eq

(4.23)

Such that,

[x] = [iLin V1 V2 ir vcs v p ]t

(4.24)

is the state vector. ⎡ ⎢ 0 ⎢ ⎢ d ⎢C ⎢ b1 ⎢ d ⎢C Aeq = ⎢ b 2 ⎢ 0 ⎢ ⎢ ⎢ 0 ⎢ ⎢ ⎢ 0 ⎣

−

d Lin

−

d Lin

0

0

0

0

(1 − D ) Ls

−

D Ls

0

0

0

0

0 −

0

(1 − D ) C b1 D Cb2

0 0 −

0 1 Cs 1 Cp

⎤ ⎥ ⎥ ⎥ 0 ⎥ ⎥ ⎥ 0 ⎥ 1 ⎥ ⎥ − Ls ⎥ ⎥ 0 ⎥ ⎥ 1 ⎥ − R ac C p ⎥⎦ 0

1 Ls 0 0

(4.25)

is the plant matrix, ⎡ (D + d ) Beq = ⎢ ⎣ Lin

⎤ 0 0 0 0 0⎥ ⎦

t

(4.26)

is the input matrix. This is followed by substituting the state variables with their harmonic components. The resulting model is thus formulated as follows: The input voltage to the resonant circuit (vAB) in terms of V1 and V2 and referring to Figure 3.2 is expanded to:

+

V1 + V 2

π

V1 + V 2

sin( 2 π (1 − D )) cos ω s t π [1 − cos( 2 π (1 − D )) ]sin ω s t + ...

v AB ≈ V 1 ( 1 − D ) − V 2 D +

124

(4.27)

___________________________________Chapter 4: Multiple Frequency Average Modelling

S1

D

1

C D

+

b1

V

1

-

c1

L S2 L

D

2

C

s

+

ir

vs +

in

i L in

s

C

p

R

ac

vp S3

D

-

3

|v s |

D S4

c2

C D

+

b2

V

4

2

-

(a ) S1

D

1

C D

b1

+

V

-

c1

1

L S2 L

i L in

D

2

is

C

s

+

s

vs +

in

C

p

R

ac

vp S3

D

-

3

|v s |

D S4

c2

C D

+

b2

V

4

2

-

(b )

(c) Figure 4.3 Equivalent Circuits for the three stages of operation (DCM) (a) input inductor charging, (b) input inductor discharging, (c) Energy transfer to output

125

___________________________________Chapter 4: Multiple Frequency Average Modelling

(i) High frequency state variables di r ( dc ) dt

=

[

1 (1 − D )V 1 ( dc ) − DV Ls

2 ( dc )

− v cs ( dc ) − v P ( dc )

]

⎡ V1d + V 2 d ⎤ sin( 2 π (1 − D )) − v csq − v Pq ⎥ ⎢ π dt ⎣ ⎦ di rd 1 ⎡ V1q + V 2 q (1 − cos( 2 π (1 − D ))) − v csd − v Pd = ω s i rq + ⎢ dt Ls ⎣ π di rql 1 (1 − D )V 1 ql − DV 2 ql − v csql − v Pql = − 2 ω l i rdl + dt Ls di rq

= − ω s i rd +

1 Ls

[

]

di rdl 1 [(1 − D )V 1 dl − DV = 2 ω l i rql + dt Ls

dv cs ( dc ) dt dv csq dt

=

i r ( dc ) Cs

= − ω s v csd +

i rq Cs

dv csd i = ω s v csq + rd dt Cs dv csql dt

= − 2 ω l v csdl +

i rql Cs

dv csdl i = 2 ω l v csql + rdl dt Cs

2 dl

− v csdl − v Pdl

⎫ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪⎪ ⎬ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪⎭

=

ir ( dc)

−

(4.28)

(4.29)

⎫ ⎪ dt Cp Rac ⎪ dv pq irq v p(q) ⎪ ⎪ = −ω s v pd + − dt C p C p Rac ⎪ ⎪ dv pd v p(d ) ird ⎪ = ω s v pq + − ⎬ dt C p C p Rac ⎪ dv pql irql v pql ⎪ ⎪ = −2ωl v pdl + − dt C p C p Rac ⎪ ⎪ dv pdl v pdl ⎪ irdl = 2ωl v pql + − dt C p C p Rac ⎪⎭ dv p ( dc)

]

⎫ ⎪ ⎪ ⎪ ⎪ ⎪ ⎤ ⎪⎪ ⎥ ⎬ ⎦ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪⎭

v p( dc)

(4.30)

126

___________________________________Chapter 4: Multiple Frequency Average Modelling

Thus, equations (4.28) to (4.30) describe the operation of the output resonant stage of the converter. (ii)Low frequency state variables Similar to the CCM operation, equations (4.31) to (4.35) describe the operation from the input to the dc-bus capacitors of the converter. They also include the effects of the high frequency components reflected from the output side.

(

)

2Vm d (D + d ) − V1( dc) + V2( dc ) πLin Lin dt diLinql 8Vm d = ( D + d ) − 2ωl iLindl − V1ql + V2 ql 3πLin Lin dt diLindl d (V1dl + V2dl ) = 2ωl iLinql − dt Lin diLinq d d = −ωs iLind − V1q − V2 q Lin Lin dt diLind d d = ωs iLinq − V1d − V2d Lin Lin dt diLin( dc )

=

(

dV1( dc ) dt dV1ql dt

=

(1 − D ) i d i Lin ( dc ) − r ( dc ) C b1 C b1

= −2ω lV1dl +

(1 − D ) i d i Linql − rql C b1 C b1

dV1dl (1 − D ) i d = 2ω lV1ql + i Lindl − rdl C b1 C b1 dt dV1q dt

= −ω sV1d +

(1 − D ) i d i Linq − rq C b1 C b1

dV1d (1 − D ) i d i Lind − = ω sV1q + rd C b1 C b1 dt

⎫ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪⎪ ⎬ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪⎭

⎫ ⎪ ⎪ ⎪ ⎪ ⎪⎪ ⎬ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪⎭

)

(4.31)

(4.32)

and thus,

V1 = V12( dc ) + V12ql + V12dl + V12q + V12d

(4.33)

127

___________________________________Chapter 4: Multiple Frequency Average Modelling

Similarly for the second capacitor

⎫ ⎪ dt ⎪ dV2ql d D ⎪ = −2ωlV2dl + iLinql + irql ⎪ Cb2 Cb2 ⎪ dt ⎪⎪ dV2dl d D = 2ωlV2ql + iLindl + irdl ⎬ dt Cb2 Cb2 ⎪ ⎪ dV2q d D = −ωsV2d + iLinq + irq ⎪ dt Cb2 Cb2 ⎪ ⎪ dV2d d D = ωsV2q + iLinq + ird ⎪ ⎪⎭ dt Cb2 Cb2 dV2(dc)

=

d D iLin(dc) + ir(dc) Cb2 Cb2

(4.34)

and thus,

V2 = V22( dc ) + V22ql + V22dl + V22q + V22d

(4.35)

The two ratios d1 and d2 must be replaced by a single value or at least one of them must be expressed in terms of the other. Figure 4.4 shows the input inductor current over one switching period. iLin iLin(peak)

t

DTs

dTs

Ts

Figure 4.4 Input inductor current in discontinuous conduction mode

128

___________________________________Chapter 4: Multiple Frequency Average Modelling

The peak input inductor current is given by:

i Lin ( peak ) =

vs 2π D v s DT s = Lin ω s Lin

(4.36)

One way of obtaining a relation between D and d is by means of averaging the input current over one switching cycle [17].

i Lin ( dc ) =

1 i Lin ( peak ) ( D + d ) 2

(4.37)

Therefore, the relationship between the two variables D and d can be obtained by substituting from equation (4.36) into (4.37):

d =

2ω s Lin iLin ( dc ) 2πD vs

−D

(4.38)

Therefore, D can be expressed in terms of d or vice-versa. In order to simplify the obtained model, d is substituted for in terms of D.

4.5 Modelling of VFPSM Converters As presented in chapter 3, SSPFC converters with this type of operation have a discontinuous input inductor current. The operation of the converter can be divided into four main periods: (i) S3, S4 ON: duration= DTs, (ii) S3, S1 ON: duration= (0.5-D)Ts, (iii) S2, S1 ON: duration= DTs, the two intervals (ii) and (iii) can be expressed as two or expanded to three or four according to the discharge mode of the input inductor, which will determine the values of d2 and d3. (iv) S2, S4 ON: duration= (0.5-D)Ts. Two additional cases may also occur depending on the mode of discharge of the input

129

___________________________________Chapter 4: Multiple Frequency Average Modelling

inductor. Figure 3.4 is repeated again here in figure 4.5 to re-illustrate these modes of discharge discussed in chapter 3. Therefore, the model for each of these cases over one switching cycle can be given by the set of equations (4.39)-(4.44). iLin

iLin

iLin iLin(max)

iLin(max)

iLin(max)

i*Lin

t

t Ts/2 DTs d1Ts

Ts

Ts/2 DTs

t Ts/2

Ts

d1Ts d2Ts

(a)

Ts

d2Ts

DTs

(c)

(b)

Figure 4.5 Discharge modes of the input inductor (a) Case 1, (b) Case 2, (c) Case (3) Interval 2: DT s ≤ t ≤ (D + d 1 )Ts

Interval 1: 0 ≤ t ≤ DT s v di Lin = s dt L in dV 1 = 0 dt dV 2 i = r dt C b2 di r 1 (− V 2 − v cs = dt Ls dv cs i = r dt Cs dv dt

p

=

vp ir − Cp C p R ac

⎫ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎬ − v p )⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎭

di Lin dt dV dt dV dt

(4.39)

1

2

vs − V

=

2

L in

= 0 =

i Lin C b2

1 di r = dt Ls

(−

v cs − v

dv cs ir = dt C s dv dt

130

p

=

vp ir − C p C pR

ac

p

⎫ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ (4.40) ⎬ )⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎭

___________________________________Chapter 4: Multiple Frequency Average Modelling

Interval 4: (0.5)Ts ≤ t ≤ (0.5 + d 2 )Ts

Interval 3: (D + d 1 )Ts ≤ t ≤ (0.5)Ts

di Lin = 0 dt dV 1 = 0 dt dV 2 = 0 dt di r 1 = dt Ls

(−

v cs − v

p

dv cs ir = dt C s dv

p

dt

=

vp ir − C p C pR

ac

⎫ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪⎪ )⎬⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪⎭

di Lin dt dV dt dV dt

(4.41)

dV 2 = 0 dt 1 di r (V 1 − v cs − v = dt Ls dv cs i = r dt Cs dv dt

p

=

vp ir − C p C p R ac

p

v s − V1 − V 2 L in

1

=

i Lin − i r C b1

2

=

i Lin C b2

1 di r (V 1 − v cs − v = dt Ls

p

dv cs i = r dt Cs dv

p

dt

=

vp ir − C p C p R ac

⎫ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ (4.42) ⎬ )⎪⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎭

Interval 6: (D + 0.5 )Ts ≤ t ≤ Ts

Interval 5: (0 . 5 + d 2 )T s ≤ t ≤ (D + 0 . 5 )T s

di Lin = 0 dt − ir dV 1 = dt C b1

=

⎫ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪⎪ ⎬ (4.43) )⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪⎭

131

di Lin = 0 dt dV 1 = 0 dt dV 2 = 0 dt di r 1 (− v cs − v = dt Ls

p

dv cs i = r dt Cs dv dt

p

=

vp ir − C p C p R ac

⎫ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪⎪ )⎬⎪ (4.44) ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪⎭

___________________________________Chapter 4: Multiple Frequency Average Modelling

The occurrence of intervals 2, 3 and/or 4 depends on how the energy in the input inductor is discharged. The averaged model for iLin , V1 and V2 can have different forms

di Lin dt

⎧ vs (D + d 1 ) − V 2 d 1 ⎪ L in ⎪ L in ⎪v V V = ⎨ in (0 . 5 + d 2 ) − 1 d 2 − 2 ( 0 . 5 − D + d 2 ) L in L in ⎪ L in ⎪ v in (D ) − V 1 d 2 − V 2 d 2 ⎪ L in L in ⎩ L in

case 1

(4.45)

case 2 case 3

The equation used for the input current dynamics is determined according to the values of D and d1. In order to have case 1, D<0.5, d2=0 and

d2 =

vs V2 − vs

≤ 0 .5 − D

(4.46)

For case 2, D<0.5 and d1=0.5-D. Finally for case 3, D=0.5 and therefore, d1=0. The average dynamics of the dc-bus voltages are given by: ⎛ 1 − sgn( V 1 − V 2 ) 1 + sgn( V 1 − V 2 ) i dV 1 i V1 D ⎜⎜ = Lin d 2 − r D − + 2 N aux r aux C b1 C b2 dt C b1 C b1 ⎝ ⎛ 1 − sgn( V 1 − V 2 ) 1 + sgn( V 1 − V 2 ) ⎞ V2 ⎟⎟ D ⎜⎜ + + 2 N aux r aux C b1 C b2 ⎝ ⎠

⎞ ⎟⎟ ⎠

⎛ 1 − sgn( V 1 − V 2 ) 1 + sgn( V 1 − V 2 ) ⎞ i dV 2 i V1 ⎟⎟ = Lin (d 1 + d 2 ) + r D + + D ⎜⎜ dt C b2 C b2 C b1 C b2 2 N aux r aux ⎝ ⎠ ⎛ 1 − sgn( V 1 − V 2 ) 1 + sgn( V 1 − V 2 ) ⎞ V2 ⎟⎟ − + D ⎜⎜ C b1 C b2 2 N aux r aux ⎝ ⎠

(4.47)

(4.48)

where raux is the equivalent resistance of the auxiliary circuit path determined by the resistance of the transformer winding, the equivalent resistance presented by the diode and any additional current limiting resistors added. The two non-linear terms at the end of both equation (4.47) and (4.48) represent the operation of the auxiliary circuit. Finally, for the last three state variables representing the resonant circuit and output:

132

___________________________________Chapter 4: Multiple Frequency Average Modelling

vp V v dir V1 = D − 2 D − cs − dt Ls Ls Ls Ls

(4.49)

dv cs i = r dt Cs

(4.50)

dv p

=

dt

vp ir − C p C p Rac

(4.51)

This is followed by substituting the state variables with their harmonic components. The input voltage to the resonant circuit (vAB) in terms of V1 and V2 is expanded to: ∞

(V + (−1)

n +1

V2 )

∞

1

n =1

sin nDπ cos nωs t + ∑

(V + (−1)

n +1

V2 )

(1 − cos nDπ ) sin nωs t n =1 n n = D(V1 − V2 ) + (V1 + V2 ) sin Dπ cos nωs t + (V1 + V2 )(1 − cos Dπ ) sin ωs t + ....

v AB = D(V1 − V2 ) + ∑

1

……... (4.52) By substituting equations (4.5),(4.6), (4.8), (4.9) and (4.52) in (4.45)-(4.51) and equating harmonic components, taking into consideration the average power balance between input and output we can reformulate the model as follows: i) High frequency variables dir ( dc) dt dirq dt

=

[

1 DV1( dc) − DV2( dc) − vcs ( dc) − vP ( dc ) Ls

= −ωsird +

]

[

1 (V1d + V2 d ) sin Dπ − vcsq − vPq Ls

[

]

dird 1 = ωsirq + (V1q + V2 q )(1 − cos Dπ ) − vcsd − vPd dt Ls dirql dt

= −2ωl irdl +

[

1 DV1ql − DV2 ql − vcsql − vPql Ls

dirdl 1 = 2ωl irql + [DV1dl − DV2 dl − vcsdl − vPdl ] dt Ls

]

]

⎫ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪⎪ ⎬ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪⎭

133

(4.53)

___________________________________Chapter 4: Multiple Frequency Average Modelling dv cs ( dc )

=

dt dv csq

i r ( dc ) Cs

= − ω s v csd +

dt

i rq Cs

dv csd i = ω s v csq + rd dt Cs dv csql

= − 2 ω l v csdl +

dt

i rql Cs

dv csdl i = 2 ω l v csql + rdl dt Cs

dv pq dt dv pd dt dv pql dt dv pdl dt

(4.54)

⎫ ⎪ Cp C p R ac ⎪ irq v p(q) ⎪ = −ω s v pd + − ⎪ C p C p R ac ⎪ v p(d ) i ⎪ = ω s v pq + rd − ⎬ C p C p R ac ⎪ irql v pql ⎪ = − 2ω l v pdl + − C p C p R ac ⎪ ⎪ v pdl ⎪ irdl = 2ω l v pql + − C p C p R ac ⎪⎭

dv p ( dc ) dt

⎫ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪⎪ ⎬ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪⎭

=

ir ( dc )

−

v p ( dc )

(4.55)

where V1 & V2 are the total instantaneous values of the dc-bus capacitor voltages. ii) Low frequency variables ⎫ 2V m (D + d 1 ) − V 2 dc d 2 ⎪ πLin dt Lin ⎪ V 2 ql ⎪ di Linql 8V m (D + d 1 ) − 2ω l iindl − d 1 ⎪ = 3πLin Lin dt ⎪ di Lindl V 2 dl ⎪ = 2ω l iinql − d1 ⎬ dt Lin ⎪ di Linq V2q ⎪ = − ω s iind − d1 ⎪ dt Lin ⎪ di Lind V ⎪ = ω s iinq − 2 d d 1 ⎪⎭ dt Lin di Lin ( dc )

=

134

(4.56-a)

___________________________________Chapter 4: Multiple Frequency Average Modelling 2Vm (0.5 + d 2 ) − V1dc d 2 − V2dc (0.5 − D + d 2 ) πLin Lin Lin V V1ql 8Vm (0.5 + d 2 ) − 2ωl iindl − d 2 − 2ql (0.5 − D + d 2 ) = 3πLin Lin Lin V1dl V2dl (0.5 − D + d 2 ) d2 − = 2ωl iinql − Lin Lin V1q V2q (0.5 − D + d 2 ) d2 − = − ωs iind − Lin Lin V V = ωs iinq − 1d d 2 − 2d (0.5 − D + d 2 ) Lin Lin

diLin( dc) dt diLinql dt diLindl dt diLinq dt diLind dt

=

dt di Linql dt di Lindl dt di Linq dt di Lind dt

⎫ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎬ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪⎭

2Vm V V D − 1dc d 2 − 2 dc d 2 πLin Lin Lin V2 ql V1ql 8Vm = d2 d2 − D − 2ω l iindl − 3πLin Lin Lin V V = 2ω l iinql − 1dl d 3 − 2 dl d 2 Lin Lin V1q V2 q = − ω s iind − d2 − d2 Lin Lin V V = ω s iinq − 1d d 2 − 2 d d 2 Lin Lin

di Lin ( dc )

=

⎫ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎬ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪⎭

(4.56-b)

(4.56-c)

where each set of equations in (4.56) represents the decomposition of one average model equation from(4.45). dV 1 ( dc ) dt dV 1 ql dt

=

=

i Lin

( dc )

C b1

i Linql C b1

d2 −

i r ( dc ) C b1

D − M

d 2 − 2 ω lV 1 dl −

i rql C b1

1

D − M

dV 1 dl i i = Lindl d 2 + 2 ω lV 1 ql − rdl D − M dt C b1 C b1 dV 1 q dt

=

i Linq C b1

d 2 − ω sV 1 d −

i rq C b1

D − M

1

dV 1 d i i = Lind d 2 + ω sV 1 q − rd D − M dt C b1 C b1

1

1

1

⎫ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪⎪ ⎬ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪⎭

135

(4.57)

___________________________________Chapter 4: Multiple Frequency Average Modelling ⎫ ⎪ Cb 2 Cb 2 ⎪ ⎪ iLinql irql = ( d1 + d 2 ) − 2ω lV2 dl − D − M2⎪ Cb 2 Cb 2 ⎪ ⎪⎪ iLindl irdl = ( d1 + d 2 ) + 2ω lV2 ql − D − M2⎬ Cb 2 Cb 2 ⎪ ⎪ i i = Linq ( d1 + d 2 ) − ω sV2 d − rq D − M 2 ⎪ Cb 2 Cb 2 ⎪ ⎪ iLind ird = ( d1 + d 2 ) + ω sV2 q − D − M2 ⎪ ⎪⎭ Cb 2 Cb 2

dV 2 ( dc ) dt dV 2 ql dt dV 2 dl dt dV 2 q dt dV 2 d dt

=

iLin ( dc )

( d1 + d 2 ) −

ir ( dc )

D − M2

(4.58)

where M1 and M2 represent the two non-linear terms due to the operation of the auxiliary circuit. The closer the converter operation is to steady state the less effect the two nonlinear terms M1 and M2 have on the dynamic performance. The values of d1 and d2 are determined according to the discharge mode; these values are then substituted in the state equations such that the only control variables expressed are (D) and (ωs). It is also worth noting that the duty ratio (D) is used as a control variable here just to maintain a consistent analysis, but it can be readily replaced by the phase shift angle (γ) since it is related to (D) by a linear function as was shown in equation (3.3). The effect of parasitic elements such as ESR can also be easily represented in this model. Equation (4.59) shows an example of the required modification to add the effect of ESR, output rectifier and transformer at the output stage. The variables affected are the parallel capacitor voltage and the output filter components, which are represented by two new state variables, the output inductor current (iLo) and the output capacitor voltage (vo). Since all three variables are operating in CCM the state equations are given by:

136

___________________________________Chapter 4: Multiple Frequency Average Modelling dvP i i N sgn(vP ) = r − Lo 2 dt CP CP N1 diLo v N v sgn(vP ) RL rco ⎡ v ⎤ iLo − o ⎥ =− o + 2 P − ⎢ dt Lo N1Lo ( RL + rco ) ⎣ RL ⎦ ⎡ dvo Ro v ⎤ iLo − o ⎥ = ⎢ dt Co ( RL + rco ) ⎣ RL ⎦

⎫ ⎪ ⎪ ⎪ ⎪ ⎬ ⎪ ⎪ ⎪ ⎪⎭

(4.59)

This is followed by the harmonic expansion of the state variables to their harmonic components as was shown in the previous analysis. Since (D) and (ωs) are the input control variables, the non-linear state space system in (4.23) can thus be expressed as:

x& = f ( x, D, ω s )

(4.60)

where the input voltage magnitude and frequency are regarded as system constants. The obtained model can also be easily linearized, which then facilitates the design of the controller using conventional design methods. In this case direct transfer functions relating both control variables and the outputs can be derived as illustrated in the next section.

4.6 Small Signal Approximation In the previous sections, a large signal model was derived for the different converters and their operating conditions. This model can then be linearized by applying small signal perturbations to the state variables around a desired operating point. The state vector and control inputs in (5.60) can therefore be rewritten as:

⎫ x = x + xˆ ⎪ D = D + Dˆ ⎬ ω s = ω s + ωˆ s ⎪ ⎭

(4.61)

137

___________________________________Chapter 4: Multiple Frequency Average Modelling

where x , D and ωs are the operating points for state variables, duty ratio and switching frequency respectively, and xˆ , Dˆ and ωˆ s represent their small signal perturbations. By substituting this form of the variables in the MFA models developed previously a small signal approximation suitable for classical linear controller design can be obtained. Only first order perturbations are calculated since the higher order perturbations have small magnitudes that can be neglected. The resulting model, therefore takes the form:

x&ˆ = Aˆ xˆ + Bˆ uˆ

(4.62)

where, in this case Aˆ and Bˆ represent the small signal plant and input matrices. They are given in terms of the converter parameters, input voltage and the operating point. The

ˆ ωˆ vector uˆ = [ D s

Vˆm ]t represents the perturbed input vector. The outputs in this case

would be the output voltage, dc-bus voltage and/or the input current. Substituting the perturbed parameters in the system model we get: For the case of CCM (i) High frequency state variables d iˆr ( dc ) dt d iˆrq dt d iˆrd dt d iˆrql dt d iˆrdl

=

[

1 (1 − D )Vˆ1( dc ) − V1( dc ) Dˆ − V 2 ( dc ) Dˆ − D Vˆ2 ( dc ) − vˆ cs ( dc ) − vˆ p ( dc ) Ls

= −ω s iˆrd − i rd ωˆ s + = ω s iˆrq + i rq ωˆ s + = − 2ω l iˆrdl +

[(

]

)

1 ˆ V1q + Vˆ2 q sin( 2π (1 − D ) − 2π (V1q + V 2 q ) cos( 2π (1 − D )) Dˆ − vˆ csq − vˆ pq Ls

[(

)

]

1 ˆ V1d + Vˆ2 d (1 − cos( 2π (1 − D ) ) − 2π (V1d + V 2 d )sin( 2π (1 − D ) Dˆ − vˆ csd − vˆ pd Ls

[

1 (1 − D )Vˆ1ql − V1ql Dˆ − V 2 ql Dˆ − D Vˆ2 ql − vˆ csql − vˆ pql Ls

[

1 (1 − D )Vˆ1dl − V1dl Dˆ − V 2 dl Dˆ − D Vˆ2 dl − vˆ csdl − vˆ pdl = 2ω l iˆrql + dt Ls

]

]

] ……. (4.63)

138

⎫ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎬ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎭

___________________________________Chapter 4: Multiple Frequency Average Modelling d vˆ cs ( dc

)

dt d vˆ csq d vˆ csd dt

d vˆ csdl dt

dt

d vˆ pql dt d vˆ pdl dt

iˆrq

C ˆi rd + Cs

=

iˆr ( dc ) C

−

p

s

iˆrql C

s

iˆ + rdl Cs

= 2 ω l vˆ sql

d vˆ p ( dc )

dt

s

= − 2 ω l vˆ sdl +

dt

d vˆ pd

C

⎫ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎬ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎭

)

= ω s vˆ sq + ωˆ s v csq

d vˆ csql

dt

iˆr ( dc

= − ω s vˆ sd − ωˆ s v csd +

dt

d vˆ pq

=

vˆ p ( dc ) C p R ac

= − ω s vˆ pd − ωˆ s v pd +

= 2 ω l vˆ pql +

iˆrql C

C

−

p

vˆ p ( q ) C p R ac

vˆ p ( d ) iˆ + rd − Cp C p R ac

= ω s vˆ pq + ωˆ s vˆ pq = − 2 ω l vˆ pdl +

iˆrq

−

p

vˆ pql C p R ac

vˆ pdl iˆrdl − Cp C p R ac

(4.64)

⎫ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎬ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎭

(4.65)

(ii) Low frequency state variables d Vˆ1 ( dc )

⎫ ⎪ dt ⎪ ⎪ ˆ d V 1 ql 1− D ˆ Dˆ (i Linql − i rql ) ⎪⎪ = − 2 ω l Vˆ1 dl + i Linql − iˆrql + C b1 C b1 dt ⎪ ˆ d Vˆ1 dl ⎪ − 1 D D (i Lindl − i rdl ) = 2 ω l Vˆ1 ql + iˆLindl − iˆrdl + ⎬ C b1 C b1 dt ⎪ ⎪ ˆ ˆ d V1q 1− D ˆ D (i Linq − i rq )⎪⎪ = − ω s Vˆ1 d − V 1 d ωˆ s + i Linq − iˆrq + C b1 C b1 dt ⎪ d Vˆ1 d 1− D ˆ Dˆ ˆ ˆ (i Lind − i rd ) ⎪⎪ = ω s V 1 q + V 1 q ωˆ s + i Lind − i rd + C b1 C b1 dt ⎭ =

1− D ˆ Dˆ (i Lin ( dc ) − i r ( dc ) ) i Lin ( dc ) − iˆs ( dc ) + C b1 C b1

(

)

(

)

(

)

(

(

)

)

139

(4.66)

___________________________________Chapter 4: Multiple Frequency Average Modelling d Vˆ2 ( dc )

⎫ ⎪ dt ⎪ ⎪ ˆ ˆ d V 2 ql 1− D ˆ D D ˆ ⎪ ˆ (i Linql − i sql ) = − 2ω l V 2 dl + i sql − i Linql + ⎪ Cb2 C b2 C b2 dt ⎪ ⎪ d Vˆ2 dl 1− D ˆ Dˆ D ˆ ˆ (i Lindl − i sdl ) = 2ω l V 2 ql + i sdl − i Lindl + ⎬ C b2 C b2 Cb2 dt ⎪ ⎪ ˆ ˆ dV 2 q 1− D ˆ D D ˆ (i Linq − i sq ) ⎪⎪ = −ω s Vˆ2 d − ωˆ s V 2 d + i sq − i Linq + C b2 C b2 Cb2 dt ⎪ d Vˆ2 d 1− D ˆ Dˆ D ˆ ˆ (i Lin ( dc ) − i sd ) ⎪⎪ i sd − = ω s V 2 q + ωˆ s V 2 q + i Lind + C b2 Cb2 Cb2 dt ⎭ =

1− D ˆ Dˆ D ˆ (i Lin ( dc ) − i s ( dc ) ) i s ( dc ) − i Lin ( dc ) + C b2 Cb2 Cb2

2Vˆm 1 − D ˆ Dˆ (V1( dc ) + V 2 ( dc ) ) − V 1 ( dc ) + Vˆ2 ( dc ) + π L in dt L in L in di Linql 8Vˆm 1− D ˆ Dˆ (V1 ql + V 2 ql ) = − 2 ω l iˆindl − V 1 ql + Vˆ2 ql + 3π L in L in L in dt di Lindl 1− D ˆ Dˆ (V1 dl + V 2 dl ) = 2 ω l iˆinql − V 1 dl + Vˆ2 dl + dt L in L in di Linq 1− D ˆ Dˆ (V 1 q + V 2 q ) = − ω s iˆLind − ωˆ s i Lind − V 1 q + Vˆ2 q + dt L in L in di Lind 1− D ˆ Dˆ (V1 d + V 2 d ) = ω s iˆLinq + ωˆ s i Linq − V 1 d + Vˆ2 d + dt L in L in di Lin ( dc )

=

(

)

(

)

(

)

(

(

)

)

(4.67)

⎫ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎬ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎭

(4.68)

Equations (4.63) to (4.68) thus represent a linear small signal model for the converter operation. Closed loop controller design for this system, with a zero reference for perturbation values, can be performed. Since the model is now linear, superposition can be used to study the system response to each of the control inputs. These equations can be rewritten in matrix form as three separate sets of matrices as follows: x&ˆ dc = Aˆ dc xˆ dc + Bˆ dc uˆ

(4.69)

x&ˆ dq = Aˆ dq xˆ dq + Bˆ dq uˆ

(4.70)

x&ˆ dql = Aˆ dql xˆ dql + Bˆ dql uˆ

(4.71)

140

___________________________________Chapter 4: Multiple Frequency Average Modelling t where, xˆ = [ xˆ dc

t xˆ dq

t xˆ dql ]t , such that:

xˆ dc = [iˆLin ( dc ) Vˆ1( dc ) Vˆ2( dc )

iˆr ( dc )

vˆs ( dc )

vˆ p ( dc ) ]t

(4.72)

Similarly, xˆ dq is a vector of the states representing the high frequency components and xˆ dql is the state vector of those representing the low frequency components.

⎤ ⎡ 0 0 0 (D −1) / Lin (D −1) / Lin 0 ⎢(D −1) / C 0 0 0 0 (1− D) / Cb1 ⎥ b1 ⎥ ⎢ 0 0 0 0 (1− D) / Cb2 ⎥ ˆA = ⎢ D / Cb2 dc 0 −1/ Ls −1/ Ls (1− D) / Ls − D / Ls 0 ⎥ ⎢ ⎥ ⎢ 1/ Cs 0 0 0 0 0 ⎥ ⎢ 1/ C −1/(Cp Rac ) 0 0 0 0 p ⎦ ⎣

(4.73)

represents the plant sub-matrix for variables in xˆ dc the other sub-matrices are constructed in a similar fashion such that:

⎡ Aˆ dc ⎢ Aˆ = ⎢ 0 ⎢ 0 ⎣

0 ˆA dq 0

⎤ ⎥ ⎥ ⎥ dq ⎦

0 0 Aˆ

(4.74)

Matrices Aˆ dq and Aˆ dql are listed in appendix D. The input sub-matrix Bˆ dc is given by:

Bˆ dc

⎡V1( dc ) + V2( dc ) ⎢ Lin ⎢ 0 =⎢ 2 ⎢ ⎢ πLin ⎢⎣

iLin ( dc ) − ir ( dc ) Cb1 0 0

−

iLin ( dc ) − ir ( dc ) Cb 2 0 0

−

V1( dc ) + V2( dc ) Ls 0 0

⎤ 0 0⎥ ⎥ 0 0⎥ 0 0⎥⎥ ⎥⎦

t

(4.75)

Sub-matrices Bˆ dq and Bˆ dql are constructed in a similar way and are listed in appendix C, such that:

141

___________________________________Chapter 4: Multiple Frequency Average Modelling

⎡ Bˆ dc ⎤ ⎢ ⎥ Bˆ = ⎢ Bˆ dq ⎥ ⎢ Bˆ ⎥ ⎣ dql ⎦

(4.76)

Consequently, the transfer function of any state variable with respect to any of the inputs can be obtained using the classical form: G ( s ) = Cˆ ( sI − Aˆ ) −1 Bˆ

(4.77)

where Cˆ represents the small signal output matrix and s is the Laplace domain variable. The full expressions of the state space system matrices for the different modes of operation can be obtained using the same procedure. This small signal model can be used to study the system open loop response and can be used for feedback control loop design. Since the system is linearized, the superposition theory can be applied for the control loop design for each of the control inputs. Using this analysis for the converter operating with VFAPWM control, the output voltage control loop has a gain of 5 and time constant of 15µsec. For the dc-bus voltage loop controller gain is 0.5 and time constant 670µsec for DCM operation, whereas for CCM current mode control the current loop controller has a gain of 4.2 and a bandwidth of 15 kHz. Similarly, for the VFPSM controlled converter the output voltage control loop has a gain of 0.7 and time constant 715µsec. These values were used for the control of the converters in chapters 2 and 3. Figure 4.6 shows the compensated closed loop frequency response of the dc-bus voltage to duty ratio and output voltage to switching frequency at an operating point of: minimum input voltage, 48V output, V1 + V2 = 400V with the converter at different operating conditions.

142

___________________________________Chapter 4: Multiple Frequency Average Modelling

Figures 4.7 to 4.10 show the input current and output voltage dynamic performance at start up and during a 50% step load change in simulation and experimental results. These figures show good correlation between simulation and experimental waveforms. Magnitude (dB)

500 0

VFAPWM-CCM

0

0

VFPSM

-50 0

VFAPWM-DCM Phase (deg)

-100 0 0 -45

VFAPWM-DCM VFAPWM-CCM

-90 -135

VFPSM

-180 10

0

10

1

10

2

10

3

10

4

10

5

Frequency (rad/sec) (a)

Phase (deg)

Magnitude (dB)

10 -1

Frequency (rad/sec) (b) Figure 4.6 Compensated response (a) dc-bus voltage to duty cycle, (b) output voltage to switching frequency 143

10

6

___________________________________Chapter 4: Multiple Frequency Average Modelling 20

Input current is (A)

15 10 5 0 -5 -10 -15 -20

0

0.1

0.2

0.3

Time (s)

0.4

0.5

0.6

Figure 4.7 Simulation results: Input current with 50% step load change at t=0.3s

Io 5A/div

500ms/div

is 2A/div

Figure 4.8 Experimental results: Input current with 50% step load change

144

___________________________________Chapter 4: Multiple Frequency Average Modelling 50

Output Voltage Vo (V)

40

30 20

10 0

-10 0

0.05

0.1

0.15

0.2

0.25

0.3

Time (s) Figure 4.9 Simulation results: Output voltage with 50% step load variation at t=0.1 sec.

0.35 Vo 10V/div

500ms/div

(a) Vo 10V/div

5ms/div ΔVo=0.5 V

ΔVo1V/div

1ms/div

(b) Figure 4.10 Experimental results: Output voltage: (a) during start time and (b) with a 50% step load change

145

___________________________________Chapter 4: Multiple Frequency Average Modelling

4.7 Decoupled Model A further approximation is also possible for the derived model, since it is also possible to decouple the high and low frequency variables. This approximation can be used owing to the significant difference in the dynamic performance of the input to bus portion of the converter as compared to the bus to output portion. The former is much slower in dynamic response as compared to the latter. This is achieved by considering the input to the high frequency resonant stage as a rectangular wave voltage source whose magnitude is determined by the value of the dc-bus voltage. In case of fundamental analysis, this would be a sinusoidal voltage source whose magnitude depends on Vbus, whereas, the low frequency current shaping boost operation can be separated as having a dc load at the output determined by the output of the converter. A simplified schematic diagram of this separation is shown in figure 4.11

Figure 4.11 Simplified block diagram of the decoupled circuit This approximation gives a useful estimate of the steady state values of voltages and currents across and through all components of the converter, when non-exact values are needed. 146

___________________________________Chapter 4: Multiple Frequency Average Modelling

4.8 Example Controller Design Based on the Decoupled Model Since the converter model can be decoupled into two subsystems one for output and one for input current shaping, the output voltage is regulated by variable frequency determined through the output voltage error control loop. Based on the small signal analysis of section 4.7 and the closed loop frequency response in figure 4.6, the compensator in this loop has a transfer function:

G vo =

fs s + 2 . 1524 × 10 3 = e vo s s + 1 . 4692 × 10 5

(

)

(4.78)

where fs is the switching frequency, evo is the output voltage error and s is the Laplace domain variable. As for the input to dc-bus stage, a sliding mode controller is designed to integrate both voltage and current loops. For this purpose, and since in a decoupled model the high frequency components have a much lower effect, the model of the low frequency variables can be given as:

⎡ ⎢ 0 ⎢ i d ⎡⎢ Lin ⎤⎥ ⎢ u − 1 V1 = dt ⎢ V ⎥ ⎢⎢ Cb1 ⎣ 2⎦ ⎢1 − u ⎢C ⎣ b2

u −1 Lin −1 Req1Cb1 0

u −1 ⎤ ⎥ ⎡ 1 ⎤ Lin ⎥ ⎢L ⎥ i ⎥ ⎡ Lin ⎤ ⎢ in ⎥ 0 ⎥ ⎢ V1 ⎥ + ⎢ 0 ⎥ vs ⎥ ⎢⎣ V2 ⎥⎦ ⎢ 0 ⎥ −1 ⎥ ⎢ ⎥ ⎣ ⎦ ⎥ Req 2Cb 2 ⎦

(4.79)

where (u) is a variable that depends on the state of the switches (S3 and S4), such that: ⎧1 u = ⎨ ⎩0

when S 3 and S 4 are ON when S 3 and S 4 are OFF

147

(4.80)

___________________________________Chapter 4: Multiple Frequency Average Modelling

Req1 and Req2 are the equivalent resistances that ensure power flow balance through the dc-bus capacitors Cb1 and Cb2, respectively. These resistance values can be updated on a cycle to cycle basis. Therefore the switching surface can be given by:

σ = g i ei + g v evbus

(4.81)

σ <0 σ >0

1 u = ⎧⎨ ⎩0

(4.82)

where gi and gv are switching function gains, ei and evbus are the errors of the input current and the dc-bus voltage respectively such that: ei = iref − iLin , evbus = Vref − (V1 + V2 )

(4.83)

The reference output voltage is a constant dc value, whereas the reference current i1ref takes the waveform of a rectified sinusoid in phase with the rectified input voltage. The amplitude of this sinusoid is determined such that power flow is balanced [13]. Since the line frequency is much lower than the switching frequency, the reference values can be considered at steady state during each switching cycle. The next step is to determine the stability of the controller. A sufficient condition for stability can be given by:

σσ& < 0

(4.84)

Applying this condition using (4.79) and (4.83) we get When σ > 0 ⇒ u = 0 ⇒ σ& < 0

therefore

,

gi gv

⎛ V 1 + i Lin R eq 1 V 2 + i Lin R eq 2 ⎜ + R eq 1 C b 1 R eq 2 C b 2 ⎜ > L in ⎜ v s − V1 − V 2 ⎜ ⎜ ⎝

148

⎞ ⎟ ⎟ ⎟ ⎟ ⎟ ⎠

(4.85)

___________________________________Chapter 4: Multiple Frequency Average Modelling

When σ < 0 ⇒ u = 1 ⇒ σ& > 0

therefore ,

gi L ⎛ V1 R eq 2 C b 2 + V 2 R eq 1C b 1 < in ⎜ gv v s ⎜⎝ R eq 1C b1 R eq 2 C b 2

⎞ ⎟ ⎟ ⎠

(4.86)

As long as (4.85) and (4.86) are satisfied, the sliding condition is satisfied and the system trajectory moves along the designed sliding surface. Consequently the equivalent duty ratio needed during each duty ratio can be calculated. A state observer can also be designed to estimate the input inductor current, in order to reduce the number of measurements and consequently increase system reliability. The observer dynamics can be given by:

z& = Ad z + Bd u + F + K ( y − Cz)

(4.87)

where z represents the vector of estimated states, z = [iLine

V1e

V2e ]t , Ad, Bd and F are

obtained by the separation of the plant matrix in (4.79), K is the observer parameter vector, y is the output and Cz is the output due to estimated states. In this case the only output is V1+V2. Therefore, C= [0 1 1]. Matrix B depends on both the converter parameters and the state values. Therefore, it can be separated into a parameter matrix Bd’ multiplied by the observed states vector z, and thus (4.87) can be rewritten as:

(

)

z& = Ad + Bd' u z + F + K ( y − Cz )

(4.87*)

such that,

149

___________________________________Chapter 4: Multiple Frequency Average Modelling

Ad

and

⎡ ⎢ 0 ⎢ ⎢ −1 = ⎢ ⎢ C b1 ⎢ −1 ⎢C ⎣ b2 K = [K 1

−1 L in −1 R eq 1 C b 1 0 K

2

⎤ ⎡ 1 ⎥ ⎢ 0 L in ⎥ ⎢ ⎥ ⎢ 1 0 0 ⎥, Bd = ⎢ C b1 ⎥ ⎢ 1 −1 ⎥ ⎢ 0 ⎢⎣ C b 2 R eq 1 C b 1 ⎥⎦ t ⎡ vs ⎤ t K3], F = ⎢ 0 0⎥ ⎣ L in ⎦ −1 L in

1 ⎤ ⎥ L in ⎥ 0 ⎥ ⎥ ⎥ 0 ⎥ ⎥⎦

Subtracting (4.87*) from (4.79) the error dynamics of the system would reduce to:

e& = [ Ad + Bd' u + KC ]e = Aobs e

(4.88)

[

ˆ ˆ ˆ where, e is the estimation error vector e = i Lin − i Lin V1 − V1 V 2 − V 2

] . Based on the t

equivalent continuous control signal of the variable structure controller (ueq), the system is observable; therefore, the observer gain vector K= [K1 K2 K3]t is designed by solving the characteristic equation:

sI − Aobs = 0

(4.89)

Combining the state observer with the previously designed controller, the conditions of existence of sliding mode are modified to be: For σ > 0 ⇒ u = 0 ⇒ σ& < 0 V 2 + i Lin R eq 2 ⎛ V1 + i Lin R eq1 ⎞ ⎜ − K 2 (V1 + V 2 ) + − K 3 (V1 + V 2 ) ⎟ R eq 2 C b 2 ⎜ R eq1C b1 ⎟ g therefore , i > Lin ⎜ ⎟ gv v s − V1 − V 2 + K 1 Lin (V1 + V 2 ) ⎜ ⎟ ⎜ ⎟ ⎝ ⎠

(4.90)

And for σ < 0 ⇒ u = 1 ⇒ σ& > 0

⎛ V1 Req 2 Cb 2 + V2 Req1Cb1 ⎞ Lin ⎜ − K 2 (V1 + V2 ) − K 3 (V1 + V2 ) ⎟ ⎜ ⎟ Req1Cb1 Req 2 Cb 2 g ⎝ ⎠ therefore, i < gv v s + K1 Lin (V1 + V2 )

150

(4.91)

___________________________________Chapter 4: Multiple Frequency Average Modelling

Therefore, the observer parameter vector should be designed to achieve the desired error dynamics as well as to satisfy the conditions in (4.90) and (4.91). Figure 4.12 shows simulation results of the actual and estimated input current with a 50% step load change at t= 0.1s. 20

Estimated

15

Actual

Input Current (A)

10 Loading point

5 0 -5 -10 -15 -20

0.04

0.06

0.08

0.1

0.12

0.14

0.16

Time (sec) Figure 4.12 Actual and estimated input current

4.9 Summary In this chapter a state-space model based on combined averaging and multiple frequency models has been presented. The model is suitable for prediction of the performance of a single-stage three-level resonant ac-dc converter operated with variable frequency asymmetrical pulse width modulation or variable frequency phase shift modulation control to regulate the output voltage and shape the input current, as well as to control the dc-bus voltage. Both approximate models and detailed models that contain effects of parasitic components can be derived from the proposed model. The proposed

151

___________________________________Chapter 4: Multiple Frequency Average Modelling

model gives very good performance prediction under transient and steady state conditions and facilitates a better controller design at any of its levels.

152

________________________________________________________Chapter 5: Discrete Time Controller

Chapter 5 Discrete Time Realization of the VFAPWM and VFPSM Controllers 5.1 Introduction With recent advances in microprocessors, digital control is increasingly being used in various applications of switch mode power supply systems. Digital control offers many advantages over analog control. These advantages include ease of implementation of computational functions, increased flexibility in modifying the code for different applications, applicability to sophisticated non-linear control techniques, the ability to add supervisory and protection functions to the existing control loop, less sensitivity to noise and environmental variations, and ease of implementation of the controller on a single dedicated integrated circuit (IC). However, the use of digital control may imply a higher development cost and it also has the disadvantage of limited resolution due to the finite number of bits of the processor and the analog to digital (A/D) converter. The first drawback can be alleviated if the controller is implemented by a dedicated chip that can be mass produced, thus reducing costs. There is more than one way to overcome the latter disadvantage. One option is to increase the number of bits representing the controller variables, but this requires higher and higher clock speed and memory capacity for storage. Another option is to develop control laws that reduce the effect of resolution error.

153

________________________________________________________Chapter 5: Discrete Time Controller

In this chapter the discrete time realization of the proposed controllers is investigated. A cycle by cycle control algorithm is derived for an SSPFC converter operating under variable frequency asymmetrical pulse width modulation or variable frequency phase shift modulation. This method can be easily implemented using digital signal processors, FPGAs, or dedicated control chips.

5.2 Discrete Model of the Converter Discrete time models can be derived from the small signal model obtained in chapter 4, with constant or variable sampling rates. To obtain the discrete time model, the continuous time model is quantized. The equivalent system model therefore becomes:

⎛T ⎞ Δxk +1 = e AT Δxk + ⎜⎜ ∫ e Aλ dλ ⎟⎟ BΔu k ⎝0 ⎠

(5.1)

where T is the sampling period and subscript k denotes the sample at which calculation is made. Since this model is used for a switching power supply, the sampling period should be chosen to satisfy Shannon’s theory, i.e. T ≥ 2Ts , where Ts is the switching ⎛ period ⎜⎜ T s = 2 π ωs ⎝

⎞ ⎟⎟ . In order to reduce the number of calculations and required memory ⎠

size, the sampling period can be made to change according to the switching frequency produced by the output voltage regulator. Therefore, the model expressed in (5.1) has to be modified to:

Δxk +1 = e

ATk

⎛ Tk Aλ ⎞ Δxk + ⎜ ∫ e dλ ⎟ BΔuk ⎜ ⎟ ⎝0 ⎠

(5.2)

154

________________________________________________________Chapter 5: Discrete Time Controller

Using this analysis, controllers can be designed in the z-domain to regulate the output voltage, dc-bus voltage and input current. In order to implement this control scheme the converter model and the controller transfer functions must be transformed to discrete time domain. Many methods can be used to transform from Laplace (s) domain to z-domain [89]. In this analysis, the bilinear transformation method is used due to its features of maintaining system stability, s=

2 z −1 Ts z + 1

(5.3)

This transformation is used to map the controllers derived in chapter 4. As an example, for the case of VFAPWM, the output voltage error compensator has a transfer function of the form: ⎛ 0.2 ⎞ ⎛ 0.4 ⎞ 199.8 ⎜⎜ + 80Tk +100⎟⎟z2 + ⎜⎜160Tk − ⎟⎟z − T Tk ⎠ Tk ⎠ ⎝ Gvo(z) = ⎝ k 2 z −1

(5.4)

The closed loop root locus for a varying switching frequency is shown in figure 5.1 indicating the system stability. Similarly, the controllers for dc-bus voltage regulation and current regulation can be given by: Gi ( z ) =

Gvbus =

[(

(10 6 + 1 / Tk ) z 2 + 2 z + (10 6 − 1 / Tk )

) (

(2 / Tk )( z − 1) 88.36 × 10 −6 / Tk + 470 z − 88.36 × 10 −6 / Tk − 470

(176 + 10 6 Tk ) z + (10 6 Tk − 176) 352( z − 1)

)]

(5.5)

(5.6)

The discrete time series of the state variables can thus be obtained and substituted in the control software program.

155

Imaginary axis

________________________________________________________Chapter 5: Discrete Time Controller

Real axis Figure 5.1 Root locus of the closed loop transfer function at the output stage in Z-domain

5.3 Cycle by Cycle Controller This control method is a type of discrete time control application. The converter requires a specific value for frequency and another for duty cycle for every switching period. Therefore, cycle by cycle control is sufficient to produce the required switching pattern in each cycle. The sampling frequency can be made to be equal to twice the switching frequency or any multiple as needed. This is sufficient for regulation of output voltage and input current (at power line frequency, which is much lower than switching frequency) as well as the dc-bus voltage. Figures 5.2 and 5.3 show simplified block diagrams of the proposed method for VFAPWM and VFPSM operation. In this case feedback signals are taken from the output voltage, input inductor current, dc-bus voltage and input voltage.

156

________________________________________________________Chapter 5: Discrete Time Controller

The output voltage control loop determines the switching frequency required to achieve the desired voltage regulation. This frequency (or time period) also controls the sampling time according to the current switching frequency via a resettable counter. The switching signal is used to generate the required switching pulses of 50% duty cycle. In order to generate the required pulse width or phase shift between the switching pulses, another resettable counter is initiated with its programmed target value set by the control loop of the dc-bus voltage. This is used to control the pulse duration or the delay time generated between the switches of each leg of the converter determining the duty cycle. Due to the combination of two control variables, their range of variation is reduced and accuracy is not severely penalized by the quantization of the input error signals and the output phase shifted switching signals. A flowchart of the control algorithm is shown in figure 5.4. The VHDL program code is given in appendix E.

Figure 5.2 Simplified block diagram of the proposed control scheme for the case of VFAPWM Control 157

________________________________________________________Chapter 5: Discrete Time Controller

Figure 5.3 Simplified block diagram of the proposed control scheme for the case of VFPSM control

5.4 Simulation Results The controller is applied to a 48V, 2.3kW VFAPWM SSPFC circuit that is designed with the following parameters: Vin=90-265Vrms, Ls=5µH, Cs=17.5nF, CP=30nF, N1/N2=12 and Lin=1.5µH. The input inductor is operating in discontinuous conduction mode. The switching frequency fs ≥ 250kHz. The dc-bus voltage reference is set to a range of 400 to 650 Volts corresponding to a 90-265Vrms input voltage. Figure 5.5 shows the dc-bus voltage, input current responses to a 50% step load change, and output voltage for minimum input voltage. Similarly, figure 5.6 shows the same quantities for maximum input voltage. Figures 5.7 and 5.8 show the frequency variation throughout the converter operation and the error in the output voltage for the maximum and minimum input voltages respectively.

158

________________________________________________________Chapter 5: Discrete Time Controller

Figure 5.4 Flow chart of the control algorithm

159

________________________________________________________Chapter 5: Discrete Time Controller

Using a combined variable frequency and PWM control reduces the frequency variation range required to regulate the output voltage under all loading conditions. Finally, figure 5.9 shows the output of the duty cycle counter at start up and steady state, whereas figure 5.10 shows the resultant switching pulses. Table 5.1 shows the equivalent FPGA circuitry to implement this controller. Two 12bit A/D and a 14 bit D/A converters are used. Table 5.1 Required FPGA design parameters Parameter

Value

Combinational circuits

523

Registers

35

Total pins

42

PLLs

2

Multiplexers

2

Required clock frequency

300 MHz

160

________________________________________________________Chapter 5: Discrete Time Controller

50

Loading point

Input current is (A)

30 10 -10 -30 -50

0

0.04

0.08

0.12

Time (s) (a)

0.16

450

DC-bus Voltage (V)

400 350 Loading point

300 250 200 150 100 50 0

0

0.02

0.04

0.06

0.08

0.1

0.12

0.14

0.16

0.14

0.16

(b) 50

Output Voltage (V)

40

Loading point

30

20

10

0

-10

0

0.02

0.04

0.06

0.08

0.1

0.12

(c) Figure 5.5 (a) Input current , (b) Dc-bus voltage and (c) Output voltage at minimum input voltage and 50% step load change at t=0.1s 161

________________________________________________________Chapter 5: Discrete Time Controller

20 Loading point

Input current is (A)

10 0 -10 -20 0

0.04

0.08

0.12

0.16

0.2

Time (s) (a)

700

DC-bus Voltage (V)

600 Loading Point

500

400

300

200

100

0

0

0.02

0.04

0.06

0.08

0.12

0.14

0.16

0.18

0.12

0.14

0.16

0.18

0.2

(b)

50

40

Output Voltage (V)

0.1

Loading point

30

20

10

0

-10

0

0.02

0.04

0.06

0.08

0.1

(c) Figure 5.6 (a) Input current (b) Dc-bus voltage and (c) Output voltage at maximum input voltage and 50% step load change at t=0.1s 162

0.2

________________________________________________________Chapter 5: Discrete Time Controller

Error in output voltage (V)

50

40

30

20

10 Loading Point 0

-10

0

0.05

0.1

0.15

0.2

0.25

0.3

0.2

0.25

0.3

0.35

(a) 5

11.5

x 10

Switching Frequency (Hz)

4.5 11 10.5

410 9.5

3.59 8.5

38 7.5

0

0.05

0.1

0.15

(b)

Figure 5.7 (a) Output voltage error and (b) frequency variation for the case of maximum input voltage

163

0.35

________________________________________________________Chapter 5: Discrete Time Controller

Error in output voltage (V)

50

40

30

20

10

0

-10

0

0.02

0.04

0.06

0.08

0.1

0.12

0.14

0.16

(a) 5

10 4

x 10

Switching Frequency (Hz)

9.5

3.59

8.5 Loading Point

3 8

7.5

0

0.02

0.04

0.06

0.08

0.1

0.12

0.14

(b) Figure 5.8 (a) Output voltage error and (b) frequency variation for the case of minimum input voltage

164

________________________________________________________Chapter 5: Discrete Time Controller

2μs/div

Time (μs) (a) 1.2μs/div

Time (μs) (b) Figure 5.9 Output of duty cycle counter (a) at start up and (b) at steady state 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0

0

1

2 -4

x 10

Figure 5.10 The resultant duty ratio during the converter start up

165

________________________________________________________Chapter 5: Discrete Time Controller

5.5 Summary In this chapter a discrete time controller has been proposed for a SSPFC converter operating under VFAPWM and VFPSM. This method can be easily implemented using digital signal processors, FPGAs, or dedicated control chips. The sampling frequency is governed by the switching frequency controller, where only a controlled number of samples is allowed per switching cycle to reduce memory requirements. The combination of two control variables provides less sensitivity to quantization accuracy. Simulation results have been shown to illustrate the performance of this method.

166

______________________________________________________Chapter 6: Summary and Conclusions

Chapter 6 Summary and Conclusions 6.1 Summary of Contributions Conventional single-stage power factor correction converters have limitations on their input voltage range and power handling capability due to the increased component voltage stress, high circulating current, and/or high value of low frequency voltage ripples in the output. These limitations result in reduced efficiency or inadequate output voltage waveforms, which make these converters useful only for low power applications. In this thesis the problem of extending the power handling capabilities of SSPFC converters with universal input voltage range has been investigated. Both converter topologies and control techniques have been proposed in order to provide SSPFC circuits capable of handling multiple kilowatts of power with high efficiency and reduced component stresses. A summary of how the proposed converters compare to the standard two-stage PFC methods that would typically be used at this power level is shown in appendix F.

The main contributions of this thesis can be summarized as follows: (i)

A single-stage three-level resonant converter topology has been proposed by integrating the three-level half-bridge resonant dc-dc converter with the boost power factor pre-regulator. This has been achieved by having an input inductor directly connected to the bottom pair of switches of the half-bridge resonant converter. The proposed topology gives reduced voltage stress across all switches, since each switch is supposed to carry only half the dc-bus voltage.

167

______________________________________________________Chapter 6: Summary and Conclusions

The use of three-level converters, as compared to two level circuits, also provides more flexibility in controlling the converter operations through the increased number of control variables. This makes the converter suitable for operation at wide ranges of input voltage and also capable of handling higher power levels with universal input voltage. (ii)

A variable frequency asymmetrical pulse width modulation (VFAPWM) control method has been proposed. Variable frequency control is used to regulate the output voltage to the required level, where the APWM control is used for input current shaping as well as dc-bus voltage regulation. The frequency control loop is responsible for providing the carrier frequency to the APWM controller. Having two control loops in this fashion also provides the advantage of not having the extremely high dc-bus voltage values at load conditions as in the conventional single-stage power factor correction circuits. This control is suitable for converter operation in both continuous and discontinuous conduction modes.

(iii) A variable frequency phase shift modulation controller (VFPSM) has been proposed. This method results in lower voltage stress across the resonant components, but it can only be used in discontinuous conduction mode. It also requires minor modification in the converter topology in which an auxiliary circuit is used to balance the dc-bus capacitor voltages. (iv)

A state space approach using combined averaging and multiple frequency techniques has been proposed for modelling the proposed converters. This modelling procedure can be used for either continuous or discontinuous conduction mode. This approach enables the separation of both frequency and 168

______________________________________________________Chapter 6: Summary and Conclusions

duty ratio (or phase shift) as two explicit control variables. The converter dynamics in this case can be obtained through the large signal model, including the effects of non-linearities and circuit parasitic components, or it can be simplified to obtain a small signal model or a decoupled model. (v)

A discrete time control algorithm for SSPFC converters has been presented. A variable sampling rate has been used to minimize storage and processing requirements for the controller.

(vi)

The proposed topology and control methods have been applied to different resonant topologies. Restrictions on circuit operation and performance comparisons for the different topologies and modes of operation have been also performed.

(vii) A variable structure controller based on the decoupled system model has been proposed. This controller provides system robustness to parameter, input voltage and output load variations.

6.2 Suggested Future Work A fully digitized implementation of the proposed control methods should be carried out through the development of FPGA. Further the development of application specific integrated circuit (ASIC) should be explored to provide a smaller, more reliable and cheaper controllers.

6.3 Conclusion In this thesis potential solutions for extending the power handling capabilities of the SSPFC converters have been presented. New three-level resonant circuits topologies have been proposed, along with new control techniques namely; variable frequency

169

______________________________________________________Chapter 6: Summary and Conclusions

control with APWM or PSM. The proposed converters can handle higher power levels at high efficiency with universal input voltage range. A detailed mathematical modelling has been presented to study converter performance, along with a digital solution for control implementation. Analytical, simulation and experimental results have been presented to validate the proposed techniques.

170

_______________________________________________________________References

References [1] R. Redl & A. Kislovski, “Telecom Power Supplies and Power Quality,” Proceedings of the Telecommunications and Energy Conference (INTELEC) 1996, pp. 13-21. [2] “Limits for Harmonic Current Emission (Equipment Input Current>16A per Phase),” IEC1000-3-2 International Standard, 1995. [3] “Limits for Harmonic Current Emission (Equipment Input Current>16A per Phase),” IEC1000-3-4 International Standard, 1998. [4] IEEE Std. 519-1992, “IEEE Recommended Practices and Requirements for Harmonic Control in Electric Power Systems,” April 1993. [5] N. Mohan, T. Undeland & W. Robbins, “Power Electronics: Converters, Applications and Design,” John Wiley & Sons, 1989. [6] V. Vorperian & R. Ridely, “A Simple Scheme for Unity Power Factor Rectification for High Frequency AC Buses.” IEEE Transactions on Power Electronics, Vol. 5, No. 1, January 1990, pp. 77- 87. [7] J. Vithayathil, “Power Electronics: Principles and Applications,” McGrawHill,1995. [8] E. Masset, E. Sanchis, J. Sebastian & E. Cruz, “Improved Passive Solutions to Meet IEC 100-3-2 Regulation in Low Cost Power Supplies,” Proceedings of the Telecommunications and Energy Conference (INTELEC) 1996, pp. 99-106. [9] M. Jovanovic & D. Crow, “Merits and Limitations of Full Bridge Rectifier with LC Filter in Meeting IEC 100-3-2 Harmonic Limit Specification,” IEEE Transactions on Industry Applications, Vol. 33, No. 2, March 1997, pp. 551-557.

171

_______________________________________________________________References [10] R. Redl, “An Economical Single Phase Passive Power Factor Corrected Rectifier: Topology, Operation, Extensions and Design for Compliance,” Proceedings of the Applied Power Electronics Conference 1998, pp. 454-460. [11] W. Lin, M. Hernando, A. Fernandez, J. Sebastian & P. Villegas, “A New Topology for Passive PFC Circuit Design to Allow AC to DC Converters to Comply with the New Version of IEC 1000-3-2 Regulations,” Proceedings of the Power Electronics Specialists Conference (PESC) 2002, pp. 2050-2055. [12] Z. Yang & P. Sen, “Recent Developments in High Power Factor Switch-Mode Converters,” Proceedings of the Canadian Conference on Electrical and Computer Engineering (CCECE) 1998, pp. 477-480. [13] R. Erickson, “Fundamentals of Power Electronics, “ Kluwer Press, 2nd edition, 2001. [14] O. Garcia, J. Cobos, R. Preito, P. Alou & J. Uceda, “Single Phase Power Factor Correction: A Survey,” IEEE Transactions on Power Electronics, Vol. 18, No. 3, May 2003, pp. 749-755. [15] “Modelling, Analysis and Compensation of the Current Mode Converter,” Unitrode Application Note U-97. [16] M. Ghanem, K. Al-Haddad & G. Roy, “A New Control Strategy to Achieve Sinusoidal Line Current in a Cascade Buck-Boost Converter,” IEEE Transactions on Industrial Electronics, Vol. 43, No. 3, June 1996, pp. 441-449. [17] G. Spiazzi & S. Buso, “Power Factor Pre-Regulators Based on Combined BuckFlyback Topologies,” IEEE Transactions on Power Electronics, Vol. 15, No. 2, March 2000, pp. 197-204.

172

_______________________________________________________________References [18] G. Spiazzi, “A High Quality Rectifier Based on the Forward Topology with Secondary Side Resonant Reset,” IEEE Transactions on Power Electronics, Vol. 18, No. 3, May 2003, pp. 725-732. [19] J. Sebastian, J. Uceda, J. Cobos, J. Arau & F. Aldana, “Improvinc Power Factor Correction in Distributed Power Supply Systems Using PWM and ZCS-QR SEPIC Topologies,” Proceedings of the Power Electronics Specialists Conference (PESC) 1991, pp. 780-791. [20] K. Matsui, I. Yamamoto, T. Kishi, M. Hasegawa, H. Mori & F. Ueda, “A Comparison of Various Buck-Boost Converters and Their Application to PFC,” Proceedings of the Annual Meeting of the Industrial Electronics Society (IECON) 2002, pp. 30-36. [21] W. Guo & P. Jain, “Comparison between Boost and Buck-Boost Implemented PFC Inverter with Built-in Soft Switching and a Unified Controller,” Proceedings of the Power Electronics Specialists Conference (PESC) 2001, pp. 472-477. [22] L. Petersen & R. Erickson, “Reduction of Voltage Stresses in Buck-Boost-Type Power Factor Correctors Operating in Boundary Conduction Mode,” Proceedings of the Applied Power Electronics Conference (APEC) 2003, pp. 664-670. [23] A. Pressman, “Switching Power Supply Design,” McGraw-Hill, 2nd Edition, 1998. [24] R. Redl & B. Erisman, “Reducing Distortion in Peak Current Controlled Boost Power Factor Correctors,” Proceedings of the Applied Power Electronics Conference (APEC) 1994, pp. 576-583. [25] D. Maksimovic, Y. Jang & R. Erickson, “Nonlinear-Carrier Control for High Power Factor Boost Rectifiers,” IEEE Transactions on Power Electronics, Vol. 11, No. 4, July 1996, pp. 578-584. 173

_______________________________________________________________References [26] R. Zane & D. Maksimovic, “Nonlinear Carrier Control for High Power Factor Rectifiers Based on Flyback, Cuk or SEPIC Converters,” Proceedings of the Applied Power Electronics Conference (APEC) 1996, pp. 814-820. [27] M. Rashid, “Power Electronics: Circuits, Devices and Applications,” Prentice Hall, 2nd Edition, 1994. [28] J. Genger, C. Hung & C. Lee, “High Power Factor AC to DC Converter Using a Reactive Shunt Regulator,” Proceedings of the Power Electronics Specialists Conference (PESC) 1994, pp. 349-355. [29] Y. Jiang, F. Lee, G. Hua & W. Tang, “A Novel Single Phase Power Factor Correction Scheme,” Proceedings of the Applied Power Electronics Conference (APEC) 1993, pp. 287-292. [30] J. Sebastian, P. Villegas, M. Hernando & S. Orello, “Improving Dynamic Response of Power Factor Correctors by Using Series Switching Post Regulators,” Proceedings of the Applied Power Electronics Conference (APEC) 1998, pp. 441446. [31] F. Pottker & I. Barbi, “Power Factor Correction of Non-Linear Loads Employing a Single Phase Active Power Filter: Control Strategy, Design Methodology and Experimentation,” Proceedings of the Power Electronics Specialists Conference (PESC) 1997, pp. 412-417. [32] O. Garcia, M. Avial, J. Cobos, J. Uceda, J. Gonzalez & J. Navas, “Harmonic Reducer Converter,” IEEE Transactions on Industrial Electronics, Vol. 50, No. 2, April 2003, pp. 322-327.

174

_______________________________________________________________References [33] M. El-Habrouk, M. Darwish & P. Mehta, “Active Power Filters: A Review,” Proceedings of IEE Electric Power Applications, Vol. 147, No. 5, September 2000, pp. 403-413. [34] M. El-Habrouk, M. Darwish & P. Mehta, “Analysis and Design of a Novel Active Power Filter Configuration,” Proceedings of IEE Electric Power Applications, Vol. 147, No. 4, July 2000, pp. 320-328. [35] M. Madigan, R. Erickson & E. Ismail, “Integrated High Quality Rectifier Regulators,” Proceedings of the Power Electronics Specialists Conference (PESC) 1992, pp. 1043-1051. [36] M. Daniele, P. Jain & G. Joos, „Single Stage Power Factor Corrected AC/DC Converter,” IEEE Transactions on Power Electronics, Vol. 14, No. 6, Nov. 1999, pp. 1046-1055. [37] O. Garcia, J. Cobos, R. Preito, P. Alou & J. Uceda, “Single Phase Power Factor Correction: A Survey,” IEEE Transactions on Power Electronics, Vol. 18, No. 3, May 2003, pp. 749-755. [38] C. Qiao & K. Smedly, “A Topology Survey of Single Stage Power Factor with a Boost Type Input Current Shaper,” IEEE Transactions on Power Electronics, Vol. 16, No. 3, May 2001, pp. 360-368. [39] L. Huber, J. Zhang, M. M. Jovanovic & F. C. Lee, “Generalized Topologies of Single Stage Input Current Shaping Circuits,” IEEE Transactions on Power Electronics, Vol. 16, No. 4, July 2001, pp. 508–513. [40] G. Moschopoulos, P. Jain, G. Joos & Y. Liu, “A single Stage Zero Voltage Switched PWM Full Bridge Converter with Power Factor Correction,” Proceedings of the Applied Power Electronics Conference (APEC) 1997, pp. 457-463. 175

_______________________________________________________________References [41] Q. Zhao, F. Lee & F. Tsai, “Voltage and Current Stress Reduction in Single Stage Power Factor Correction AC/DC Converters with Bulk Capacitor Feedback,” IEEE Transactions on Power Electronics, Vol. 17, No. 4, July 2002, pp. 477-484. [42] W. Wu, W. Qiu, K. Rustom S. Lou & I. Batarseh, “Universal Input Single Stage PFC AC/DC Converter with Reduced DC-bus Voltage Stress,” Proceedings of the Power Electronics Specialists Conference (PESC) 2002, pp. 1351-1356. [43] M. Madigan, R. Erickson & E. Ismail, “ Integrated High Quality Rectifier Regulators”, IEEE Transactions on Industrial Electronics, Vol. 46, No. 4, August 1999, pp. 749-758. [44] R. Redl, & L. Balogh, “A New Family of Single-Stage Isolated Power Factor Correctors with Fast Regulation of the Output Voltage,” Proceedings of the Power Electronics Specialists Conference (PESC) 1994, pp.1137-1144. [45] J. Qian, Q. Zhao & F. Lee, “Single Stage Single Switch Power Factor Correction AC/DC Converters with DC Bus Voltage Feedback for Universal Line Applications,” IEEE Transactions on Power Electronics, Vol. 13, No. 6, Nov. 1998, pp. 1079- 1088. [46] Y. Liu & G. Moschopoulos, “A DC bus voltage reduction technique for single-stage AC-DC forward converters,” Proceedings of the Applied Power Electronics Conference (APEC) 2004, pp. 744-749. [47] W. Choi, J. Kwon, H. Do & B. Kwon, “Single-stage half-bridge converter with high power factor,” IEE Proceedings on Electric Power Applications, Vol. 152, No. 3, May 2005,pp. 634-642.

176

_______________________________________________________________References [48] T. Wu, J. Hung, S. Tseng & Y. Chen, “A single-stage fast regulator with PFC based on an asymmetrical half-bridge topology,” IEEE Transactions on Industrial Electronics, Vol. 52, No. 1, February 2005, pp. 139- 150. [49] W. Guo & P. Jain, “Design Optimization for Steady State and Dynamic Performance of a Single-Stage Power Factor Corrected AC-DC Converter,” Proceedings of the Applied Power Electronics Conference (APEC) 2004, pp. 12061212. [50] M. Qiu, G. Moschopoulos, H. Pinheiro & P. Jain, “Analysis and Design of a Single Stage Power Factor Corrected Full Bridge Converter,” Proceedings of the Applied Power Electronics Conference (APEC) 1999, pp. 119-125. [51] G. Moschopoulos, “A Simple AC-DC PWM Full Bridge Converter with Integrated Power Factor Correction,” Proceedings of the International Telecommunications Energy Conference (INTELEC) 2001, pp. 376-383. [52] G. Moschopoulos & P. Jain, “Single Stage ZVS PWM Full-Bridge Converter,” IEEE Transactions on Aerospace and Electronic Systems, Vol. 39, No. 4, October 2003, pp. 1122-1133. [53] F. Hamdad & A. Bhat, “A Novel Soft Switching High Frequency Transformer Isolated Three Phase AC-to DC Converter with Low Harmonic Distortion,” IEEE Transactions on Power Electronics, Vol. 19, No. 1, January 2001, pp. 35-45. [54] M. Schutten, R. Steigerwald & M. Kheraluala, “Characteristics of Load Resonant Converters Operated in High Power Factor Mode,” IEEE Transactions on Power Electronics, Vol. 7, No. 2, April 1992, pp. 304-314.

177

_______________________________________________________________References [55] M. Kheraluala, R. Steigerwald & R. Gurumoorthy, “Fast Response High Power Factor Converter with Single Power Stage,” Proceedings of the Power Electronics Specialists Conference (PESC) 1991, pp. 769-779. [56] R. Steigerwald, “A Comparison of Half Bridge Resonant Converter Topologies,” IEEE Transactions on Power Electronics, Vol. 3, No. 2, April 1988, pp. 174-182. [57] V. Belaguli & A. Bhat, “Series Parallel Resonant Converter Operating in Discontinuous Current Mode. Analysis, Design, Simulation and Experimental Results,” IEEE Transactions on Circuits and Systems, Vol. 47, No. 4, April 2000, pp. 433-442. [58] V. Belaguli & A. Bhat, “A Hybrid Resonant Converter Operated as a Low Harmonic Rectifier with and without Active Control,” IEEE Transactions on Power Electronics, Vol. 14, No. 4, July 1999, pp. 730-742. [59] P. Jain & M. Tanju, “A Unity Power Factor Resonant AC/DC Converter for High Frequency Space Power Distribution System,” IEEE Transactions on Power Electronics, Vol. 12, No. 2, March 1997, pp. 325-331. [60] M. Youssef, P. Jain, H. Pinheiro & M. Orabi, “A Novel Single Stage AC-DC SelfOscillating Series Parallel Resonant Converter,” Proceedings of the Applied Power Electronics Conference (APEC) 2005, pp. 1635-1641. [61] H. Pinheiro, P. Jain & G. Joos, “Performance Characterization of Two SelfOscillating Controllers for Parallel Resonant Converters Operating with Unity Input Power Factor,” Proceedings of the Power Electronics Specialists Conference (PESC) 1997, pp. 692-698.

178

_______________________________________________________________References [62] H. Pinheiro, P. Jain & G. Joos, “Series-Parallel Resonant Converter in the SelfSustained Oscillating Mode For Unity Power Factor Applications,” Proceedings of the Applied Power Electronics Conference (APEC) 1997, pp. 477-483. [63] G. Moschopoulos & P. Jain, “Single-Phase Single-Stage Power-Factor-Corrected Converter Topologies,” IEEE Transactions on Industrial Electronics, Vol. 52, No.1, February 2005, pp. 23-35. [64] J. Pinheiro & I. Barbi, “The Three Level ZVS PWM Converter: A New Concept in High Voltage DC-to-DC Conversion,” Proceedings of the International Conference on Power Electronics and Motion Control (IPEMC) 1992, pp. 173-178. [65] J. Pinheiro & I. Barbi, “Wide Load Range Three-Level ZVS-PWM DC-to-DC Converter,” Proceedings of Power Electronics Specialists Conference (PESC) 1993, pp. 171-177. [66] J. Pinheiro & I. Barbi, “The Three Level ZVS PWM DC-to-DC Converter,” IEEE Transactions on Power Electronics, Vol. 8, No. 4, October 1993, pp. 486-492. [67] J. Pinheiro & I. Barbi, “An Improved TL-ZVS-PWM DC-DC Converter,” Proceedings of the Applied Power Electronics Conference (APEC) 1995, pp. 907912. [68] J. Pinheiro & I. Barbi, “Three-Level Zero-Voltage-Switching PWM DC-DC Converters- A Comparison,” Proceedings of Power Electronics Specialists Conference (PESC) 1995, pp. 914-919. [69] X. Ruan, L. Zhou & Y. Yan, “Soft Switching Three Level Converters,” IEEE Transactions on Power Electronics, Vol. 16, No. 5, September 2001, pp. 612-632. [70] F. Canales, P. Barbosa & F. Lee, “A Wide Input Voltage and Load Output Variations Fixed Frequency ZVS DC/DC LLC Resonant Converter for High Power 179

_______________________________________________________________References Application,” Proceedings of the Industry Applications Conference (IAS) 2002, pp. 2306-2313. [71] F. Canales, P. Barbosa & F. Lee, “A High Power Density DC/DC Converter for High Power Distributed Power System,” Proceedings of Power Electronics Specialists Conference (PESC) 2003, pp. 11-18. [72] F. Canales, P. Barbosa & F. Lee, “A Zero Current Zero Voltage Switching Three Level DC/DC Converter,” IEEE Transactions on Power Electronics, Vol. 17, No. 6, November 2002, pp. 898-904. [73] X. Ruan, B. Li and Q. Chen, “Three-Level Converters- A New Approach for High Voltage and High Power DC-to-DC Conversion,” Proceedings of Power Electronics Specialists Conference (PESC) 2002, pp. 663-668. [74] Y. Jang & M. Jovanovic, “A New Three-Level Soft-Switched Converter,” Proceedings of the Applied Power Electronics Conference (APEC) 2003, pp. 10591065. [75] Y. Gu, Z. Lu & Z. Qian, “Three Level LLC Series Resonant DC/DC Converter,” Proceedings of the Applied Power Electronics Conference (APEC) 2004, pp. 16471652. [76] J. Baggio, H. Hey, H. Grunding, H. Pinheiro & J. Pinheiro, “A PFC Rectifier for Telecommunications High Power Applications,” Proceedings of Power Electronics Specialists Conference (PESC) 2002, pp. 634-640. [77] B. Lin, H. Lu & Y. Hou, “Single-Phase Power Factor Correction Circuit with Three-Level Boost Converter,” Proceedings of the International Symposium on Industrial Electronics (ISIE) 1999, pp. 445-450.

180

_______________________________________________________________References [78] R. Gules, S. Martins & I. Barbi, “A Switched-Mode Three-Phase Three-Level Telecommunications

Rectifier,”

Proceedings

of

the

International

Telecommunications Energy Conference (INTELEC) 1999, paper 29-3. [79] P. Barbosa, F. Canales, J. Burdio & F. Lee, “A Three Level Converter and its Application to Power Factor Correction,” IEEE Transactions on Power Electronics, Vol. 20, No. 6, November 2005, pp. 1319-1327. [80] B. Lin & C. Huang, “Single-Phase Switching-Mode Rectifier with CapacitorClamped Topology,” IEE Proceeding on Electric Power Application, Vol. 152, No.1, January 2005, pp. 9-16. [81] T. Jingtao, C. Lin & Y. Jianping, “Integration of Three-Phase PFC and DC/DC Converter for UPS,” Proceedings of Power Electronics Specialists Conference (PESC) 2004, pp. 4062-4066. [82] J. Choi & B. Cho, “Small-Signal Modelling of Single-Phase Power-Factor Correcting AC/DC Converters: A Unified Approach,” Proceedings of Power Electronics Specialists Conference (PESC) 1998, pp. 1351-1357. [83] F. Huleihel, F. Lee & B. Cho, “Small-Signal Modelling of Single-Phase Boost High Power Factor Converter with Constant Frequency Control,” Proceedings of Power Electronics Specialists Conference (PESC) 1992, pp. 475- 482. [84] D. Weng & S. Yuvarajan, “Analysis of a Boost-Type Power Factor Corrector Using a Conductance Model,” Proceedings of the Applied Power Electronics Conference (APEC) 1995, pp. 835- 840. [85] V. Caliskan, G. Verghese & A. Stankovic, “Multifrequency Averaging of DC/DC Converters,” IEEE Transactions on Power Electronics, Vol. 14, No. 1 January 1999, pp. 124- 133. 181

_______________________________________________________________References [86] Z. Ye, P. Jain & P. Sen, “Multiple Frequency Modeling of High Frequency Inverter System,” Proceedings of Power Electronics Specialists Conference (PESC) 2004, pp. 4107-4113. [87] O. Ojo & I. Bhat, “The Dynamics of a Series Resonant Converter with Third-Order Commutation Network,” Proceedings of South eastern Symposium on Systems Theory (SSST) 1993, pp. 48-52. [88] Y. Liu & P. Sen, “Digital Control of Switching Power Converters,” Proceedings of IEEE Conference on Control Applications (CCA) 2005, pp. 635-640. [89] Y. Duan & H. Jin, “Digital Controller Design for Switch Mode Power Converters,” Proceedings of Applied Power Electronics Conference (APEC) 1999, pp. 967-973. [90] T. Martin & S. Ang, “Digital Control for Switching Converters,” Proceedings of International Symposium on Industrial Electronics (ISIE) 1995, pp. 480-484. [91] L. Hang, Y. Yang, B. Su, Z. LU & Z. Qian, “A Fully Digital Controlled 3KW, Single-Stage Power Factor Correction Converter Based on Full-Bridge Topology,” Proceedings of the International Power Electronics and Machines Conference (IPEMC) 2006. Papers Related to this Thesis [92] M. Agamy and P. Jain, “A New Zero Voltage Switching Single Stage Power Factor Corrected Three Level Resonant AC/DC Converter”, Proceedings of 31st IEEE Industrial Electronics Conference (IECON), November 2005, pp. 1178-1183. [93] M. Agamy and P. Jain “A New Single Stage Power Factor Corrected Three Level Resonant AC/DC Converter With and

Without Active Current Control”,

Proceedings of 40th IEEE Industry Applications Society Conference (IAS), October 2005, pp. 1992-1999. 182

_______________________________________________________________References [94] M. Agamy and P. Jain, “A Single Stage PFC Three Level Resonant AC/DC Converter Using Combined Phase Shift and Frequency Control”, Proceedings of 31st IEEE Industrial Electronics Conference (IECON) November 2005, pp. 1166-1171. [95] M. Agamy and P. Jain, “A Single Stage Three Level Resonant LLC AC/DC Converter Using a Variable- Frequency-Phase-Shift Controller and a Voltage Balancing Auxiliary Circuit”, Proceedings of 21st Applied Power Electronics Conference (APEC), March 2006, pp. 411-416. [96] M. Agamy and P. Jain, “ Modeling and Dynamics of a Single-Stage Three-level Resonant AC/DC Converter Operating with Combined Variable Frequency & PWM Control”, Proceedings of the 37th Power Electronics Specialists Conference, (PESC) , June 2006, pp. 1385-1390. [97] M. Agamy and P. Jain, “A State Space Modeling Approach of a Single-Stage Three Level Resonant AC/DC Converter Operating in Discontinuous Conduction Mode”, Proceedings

of

the

International

Telecommunication

Energy

Conference

(INTELEC), September 2006, pp. 560-566. [98] M. Agamy and P. Jain, “Modelling of Single Stage Three Level Resonant AC/DC Converters Operating with Variable Frequency Phase Shift Modulation,” Proceedings of the 38th Power Electronics Specialists Conference, (PESC), June 2007. [99] M. Agamy and P. Jain,” A New Cycle by Cycle Controller for a Three Level Resonant Single Stage Power Factor Correction Converter”, Proceedings of the 32nd IEEE Industrial Electronics Conference (IECON) November 2006, pp. 2318-2323. [100] M. Agamy and P. Jain, “A Discrete Time Controller for a Single Stage Three Level Resonant PFC Converter operated with Variable Frequency Phase Shift 183

_______________________________________________________________References Modulation,” Accepted for publication and to appear in the proceedings of the International Telecommunication Energy Conference (INTELEC), September 2007. [101] M. Agamy and P. Jain, “ Performance Evaluation of Single-Stage Three-level Resonant AC/DC Converter Topologies” Proceedings of the International Symposium on Industrial Electronics (ISIE), July 2006, pp. 1253-1258. [102] M. Agamy and P. Jain, “A Comparative Study of Two Controllers for Single Stage Three-Level Resonant AC/DC Converters”, Proceedings of the 19th Canadian Conference on Electrical and Computer Engineering, (CCECE), May 2006, pp., 1231-1234. [103] M. Agamy and P. Jain, “A Current Sensorless Sliding Mode Controller for a Three Level Resonant Single Stage PFC AC/DC Converter,” Proceedings of the 20th Canadian Conference on Electrical and Computer Engineering (CCECE), April 2007. [104] M. Agamy and P. Jain, “A Robust Controller for a Three-Level Single Stage Resonant AC/DC Converter,” The International Review of Electrical Engineering, Vol. 2, No. 5, October 2007, pp. 687-694. Publisher: Praise Worthy Prize. Software Manuals [105] PSIM 6, by PowerSim. [106] Matlab/ Simulink Release 14, by Mathworks.

184

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________Appendix A: Fundamentals

Appendix A Fundamentals A.1 Voltage Stress Reduction in SSPFC Converters The voltage stress on the bulk capacitor can also be reduced by introducing a feedback loop in the power circuit [42, 45]. This topology, shown in figure A.1a, is based on the BIFRED converter with a feedback winding. This feedback winding is used to detect the dc bus voltage as a feedback signal. In this case, as mentioned before, when the load becomes light, the duty ratio doesn’t change. As a result the PFC stage provides more power than the load needs. The unbalanced power between the input and the output will be stored in the bulk capacitor, which in turn increases the dc bus voltage. When the increased dc bus voltage is fed back it tends to reduce the duty ratio. Furthermore, the absorbed energy in the input inductor becomes small since the charging voltage across the inductor is the rectified input voltage minus the partial dc bus voltage. The key design parameters for the reduction of the dc bus voltage are the boost inductor (Lin), the transformer magnetizing inductance (Lm) the number of turns in the primary flyback transformer winding (N1) and the feedback winding (N2). The smaller the (Lm/Lin) ratio, the lower the bulk capacitor voltage stress. The boost inductor cannot be arbitrarily large in order to maintain discontinuous conduction mode operation. Therefore Lin should be designed at the maximum value that can maintain this mode. A smaller value for Lm leads to getting a limited effect on reducing the output current stress and the output ripple; hence a compromise between these values and the voltage stress must be made. It was

185

________________________________

________Appendix A: Fundamentals

found that an increase in the ratio (N2/N1) can dive a greater reduction in the voltage stress and make it less sensitive to the inductance ratio mentioned before. To obtain a desirable maximum bulk capacitor voltage, the larger (N2/N1), the larger the (Lm/Lin) that can be selected, which means a large output filter inductor can be used. However, the ratio (N2/N1) has a significant impact on the input current harmonics. The larger (N2/N1), the larger the dead angles in the input current waveform, and thus the power factor will be reduced. A converter operating on the same principle but with employing an additional flyback transformer and a snubber circuit to reduce the turn off spikes is shown in figure A.1b. This converter operates at higher efficiency because of the reduced losses and the power processing times are reduced due to the input feed forward features of this topology [43].

(b)

(a)

Figure A.1 Dc-bus voltage stress reduction techniques in SSPFC converters: (a) Using feedback winding [45], (b) Using auxiliary transformer [42]

A.2 Resonant Converters Characteristics i) Parallel resonant converter [56]: The converter can be thought of as being in steady state at each point as the DC link voltage varies at the power line frequency. Near

186

________________________________

________Appendix A: Fundamentals

the zero crossing of the input voltage, the loading of the converter is low resulting in a high value for quality factor (Q); because of this, the output voltage of the converter is stepped up. This boosting is what is needed to keep drawing current near the zero crossing. Conversely, at the peak of the input AC voltage, the maximum power is being delivered by the converter and (Q) is low. Because the DC link voltage is high near this point, the boosting action needed by the resonant circuit is either greatly reduced or not needed as the circuit response is more damped. i) Series/Parallel resonant converter [56]: This converter takes on the characteristics of a series resonant converter at high input voltage, and thus, it provides voltage step down in this case. Whereas, at the valleys of the rectified sinusoidal voltage, it acts as a parallel resonant converter providing the required boosting capabilities. Figure A.2 shows the required gain such that the resonant circuit can provide a constant output voltage for a sinusoidal input line voltage. The gain of the resonant circuits can be varied by changing the switching frequency at which they are operating. Both figures A.3 and A.4 show that parallel and series/parallel resonant circuits can operate in both buck and boost modes and therefore, they can achieve the required gain values for output voltage regulation.

187

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________Appendix A: Fundamentals

Figure A.2 An illustrative example of the required gain values for a resonant converter to produce a output dc voltage Vo =0.9Vm

Figure A.3 Variation of voltage gain versus the switching frequency for the parallel resonant converter

Figure A.4 Variation of voltage gain versus the switching frequency for the series parallel resonant converter 188

________________________________

________Appendix A: Fundamentals

A.3 Derivation of the Three-level Converter The derivation of the three-level converter is illustrated in figure A.5 for a half bridge three level converter. To clarify this idea, the voltage stress across the switches in the conventional half bridge converter in figure A.5a is equal to the whole input voltage Vin, whereas, the voltage across the switches in the converter of figure A.5c is limited to Vin/2, thus, switches with half the original rating can be used in this case. The presence of two clamping diodes and leaving proper blanking time between switch conduction periods ensures that the voltage stresses are balanced among all switches and limited to half the input voltage. In addition to the reduction of the voltage stress of the switches, some three level converters have the merit that the output filter can be significantly reduced, which improves the transient response of the converter. For these reasons, three level converters are quite suited for high input voltage and medium to high power dc/dc conversion.

189

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________Appendix A: Fundamentals

Figure A.5 The derivation of the three level half bridge converter

190

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_Appendix B: Simulation Schematics

Appendix B Simulation Schematics B.1 Three Level Resonant SSPFC Converter with VFAPWM Control B.1.1 Operation in DCM

Y

Z

X

Figure B.1 PSIM simulation schematic of the power circuit for the converter described in figure 3.1

191

________________________________

_Appendix B: Simulation Schematics

X Z

Y

Figure B.2 PSIM simulation schematic of the control circuit for the converter in figure A.1

192

________________________________

_Appendix B: Simulation Schematics

B.1.2 Operation in CCM

Figure B.3 PSIM simulation schematic of the three level resonant SSPFC converter operating in CCM

193

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_Appendix B: Simulation Schematics

B.2 Three Level Resonant SSPFC Converter with VFPSM Control

Figure B.4 PSIM simulation schematic of the three level resonant SSPFC converter operating with VFPSM control

194

PID Controller1

PID

|u|

400

195 Sine Wave2

Pulse Generator

Constant1

Sine Wave1 Abs1 Product

Subtract1

Subtract2

Product1

Abs

Saturation1

Sine Wave

|u|

Constant

0

Iin

I1

V1

I1

V2

Sign

PID

Subtract4

Product5

PID Controller

Scope6

Scope7

Subtract

Subsystem2

P

d

Iin

Subsystem1

P

d

Iin

Subsystem

P

d

Vo

Vin

Iind To Workspace4

Iin

Vbus

To Workspace2

Step

To Workspace1

Product3

Scope1

Product4

Compare To Constant

> 1000

Step1

Scope8

NOT Logical Operator

Clock

d

ws

V2

V1

Vpd

Vpq

Vpdc

Vsd

Vsq

Vsdc

Is

Isd

Isq

Isdc

To Workspace

t

Fcn

f(u)

ws

Isd

Isq

Isdc

ws

Isd

Isq

Isdc

Scope

Vp

Vs

Saturation

Vpd

Vpq

Vpdc

Vsd

Vsq

Vsdc

f(u)

Fcn4 f(u)

-K-

Scope29

Gain1

Fcn5

f(u)

Fcn1

f(u) Fcn2

2 Out2

PID

PID Controller2

Fcn3

abs(u[1]/12)

Vrec

Subtract3

48 Constant5

Subsystem3

Vo

i

Product2

1 Out1

Vo To Workspace3

________________________________ _Appendix B: Simulation Schematics

B.3 Mathematical Model of the Three Level SSPFC Converter

Figure B.5 Matlab / Simulink schematic of the mathematical model of the three level SSPFC converter

________________________________

_Appendix B: Simulation Schematics

ws 9 -1 Gain 1 Vsdc 4

1 s

-K-

Vpdc

1

Integrator

Gain2

Isdc

8 V2 Product 7 V1 Product1

1 s Product4

Integrator1

2 Isq

-KGain3

Product2

2 Vsq

5

1 s

Vpq Product5

Integrator2

-KProduct3

Gain4

3 Vsd 6 Vpd

f(u) Fcn

-1

Gain1

f(u) Fcn1

f(u) Fcn2

10 d

Figure B.6 Expansion of the equations expressing dynamics of the resonant current ws 4 -1 Gain3

1

1 s

-K-

Isdc

2 Isq

1

Integrator

Gain

1 s

-K-

2

Integrator1

Gain1

Vsdc

Vsq

Product

3 Isd

1 s

-K-

Integrator2

Gain2

3 Vsd

Product1

Figure B.7 Expansion of the equations expressing dynamics of the series resonant capacitor voltage 196

3 Isd

________________________________

_Appendix B: Simulation Schematics

ws 4 -1 Gain3

1

-K-

Isdc

1 s

Gain1

Subtract

1

Integrator

Vpdc

-KGain5

2

-K-

Isq

1 s

Gain2

Subtract1

2

Integrator1

Vpq

-KProduct

Gain6

3

-K-

Isd

Gain4

1 s Subtract2

Integrator2

3 Vpd

-KGain7 Product1

Figure B.8 Expansion of the equations expressing dynamics of the parallel resonant capacitor voltage 1 Iin

f(u)

2

1 s

d

Integrator

Fcn

1 V1

min Mi nMax

1-u[1] Fcn2

1

-K-

Gai n

Gain1

2 I1

f(u) Fcn1

3 P 4 Iin1

f(u)

5

1 s

d1

Integrator1

Fcn3

3 V2

f(u) Fcn4 6 P1

-KGai n2

4 I2

mi n 1-u[1]

MinMax1

Fcn5

Figure B.9 Expansion of the equations expressing dynamics of the DC-bus voltage

197

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_Appendix C: Layouts and Components

Appendix C Circuit Layouts and Selected Components Figures C.1 and C.2 show the power circuit for the VFAPWM converter, the first shows the circuit from input to DC-bus the latter shows the resonant tank to output. U4

U5

2

4

2

1 3

MP506W-BPMS-ND L6 L2

1

+

3

1

21

2

AC2

-

21 2uH

U8 heat_sink

U9 heat_sink

U10 heat_sink

U11 heat_sink

U12 heat_sink

2 2uH

4 2

AC1

2uH

C2 2.2u

U7 heat_sink

1

1 C1 2.2u

2

2uH L5

2

1uH

2uH L4

1

1uH

2uH L3

U1

2

2

1

21

4

2

L1 1

Current Sense L7 L8 21 21

1

-

1

2

AC2

U2

1

+

2

2

AC1

3

1

1

MP506W-BPMS-ND

U19 U21 U20 2 2 3 D 3 D S S G

G

MOSFET2

1

2

1

2

1

2

G

2 3 D S

1

U15 heat_sink

1

U14 heat_sink

1

U13 heat_sink

U23 2 3 D S

1

U22

2 3 D S

U24 2 3 D S G

U18 heat_sink

G

U17 heat_sink

G

U16 heat_sink

1

1

MOSFET2 MOSFET2

MOSFET2

MOSFET2

MOSFET2

MOSFET2

R1 10

R2 10

U27 2 3 D S

MOSFET2

MOSFET2

D3 D4 DIODEDIODE

U30

R3 10

MOSFET2 MOSFET2

1

1

2 3 D S

2 3 D S

R4 10

R6 10k C4 4700u

G

G

2 3 D S

U29

G

1

U3

U28

R5 680k

1

U26

2 3 D S

G

2 3 D S

D1 D2 DIODEDIODE

G

U25

1

1 5 2 6 3 7 4 8

1

G1 S1 G2 S2 G3 S3 G4 S4

G

1

2

1

2

1

2

gates

C3 4700u

MOSFET2

MOSFET: IRFPS43N50KPbF

Figure C.1 Power circuit for VFAPWM converter: Input to dc-bus 198

________________________________

_Appendix C: Layouts and Components

C21 C22 C23 C24 C25 L13

L14

1

L15

21 L9

21 L10

1 1

21 L1

1

21

C6

21 L3

C7

C8

C9

C10

C1 C2

C3

C4

C5

2 L4

21

C14 C15

2 L8

21 L2

C11 C12 C13

21 L7

C18 C19 C20

2 L12

21 L6

C16 C17

21 L11

21 L5

L16

21

L18 1

2 22uH

47nF 47nF

2 L17

D1

1

2

R1 100k

20uH

C26 C28 80CPQ150PbF

C30 47nF

C31

470uF

C27 C29

R2 10k

D2

U1 1 2 3 4 5 6

12 11 10 9 8 7

Transf ormer

Figure C.2 Power circuit of the VFAPWM converter: resonant tank to output Similarly, figures C.3 and C.4 represent the power circuit of the VFPSM converter. 1

U6

D1

U2

G

2 3

D S

MOSFET2

C1 1n

C2 1n

U7

1

U1 1

AC1

+

AC2

-

3

L3 2

4

2 3

Current Sense 1

L4

1uH

21 1uH

R5 1k U10

D S

L5

21

D3 D2 DIODEDIODE

G

2 1uH

2

MOSFET2

1uH

R1 1k

R2 1k

1

rectif ier

2 3

R7 1k

U4 1 2 3 4 5

G1 S1 G2 S2 G3 S3 G4 S4

10 9 8 7 6

4

U8

1

D6 DIODE gates

1 5 2 6 3 7 4 8

2 3

G

21 1uH

C3 1n

2

D S

MOSFET2

D5 D4 DIODEDIODE

R3 1k

R4 1k

U9

1

1

1

DIODE

L2

U3

2 3

R8 1k D7

Transf ormer

G

L1

D S

MOSFET2 DIODE

Figure C.3 Power circuit for VFPSM converter: Input to DC-bus 199

C4 1n

R6 v f b2 1k

________________________________ L6 1

L7 21

L8 1

C8

C9

C5

C6 C7

_Appendix C: Layouts and Components

C10

2 L9

21

U11

2 C14 C17

C20

R9 1 1k

L10

D8

1

2

2 R10 3 1k

C15 C18C21 C30 C16

4

C19 C22 U5 1 2 3 4 5 6

12 11 10 9 8 7

Transformer

Figure C.4 Power circuit of the VFPSM converter: resonant tank to output Figures C.5 and C.6 show the implementation of the control circuits for VFPSM and VFAPWM converters respectively.

C1

R2

C2 R3

PAD1

2

-

INPAD PAD2 +

V+

OUT 3

6

OP-176G/AD

5

555B

GND 7 6 DISCHARGE D1 5 THRESHOLD 4 CONTROL RESET OUTPUT 2D10D1 TRIGGER VCC

7

INPAD

R4 C3R5

V-

1n R1

U5

1

U1

4

GND

R10 U7

3

1 C12 R14

2 3

8 R13 C9

VCC

4 5

C10 6 C11 R12

7

Vbus 8 R17 R7

R18 R21 9 R 10

R8

VCC2 R22 R

Vg2

2

GND2

1

R6 ISO1 4

Vref GND E/Aout Ramp EA- Slope EA+SYNC CS+

F

SSDLYAB DLY CD OutA OutDOutB OutC Pwrgnd Vc

Vcc

20 C4 19 18 17 16

R9 C6 R11

15 14

C5

13

R16

12

R19 R

11

R15

UC3875

R20 R

Vg3

Vg2 Vg4

Figure C.5 Implementation of the VFPSM Controller 200

________________________________

GND2

C1

_Appendix C: Layouts and Components

R2

C2 R3

R4

2

-

C3R5

V-

1n R1

PAD1 INPAD PAD2

+

V+

OUT 3

U5

1

U1

4

GND

6

OP-176G/AD

R7 R8

GND 7 6 DISCHARGE THRESHOLD D1 5 4 CONTROL RESET OUTPUT 2D10D1 TRIGGER VCC

7

U7

C5 1 3 R13 2 1

INPAD

555B

Inv

Vref

N.I.

4OPTO ISOLATOR 3 E/A Out 5

8

VCC R11

2

R6

4 VCC2

5 6 C6

7

Vref

Vcc Out Vc

Clock PwrGnd Rt Ct

Ilimref

8 C4

15 14 R12 13 12 11 R10

Ramp Gnd

Vbus

16

SS

IlimS.D

10 9 C7 C12

UC2823

U14A 2

1

U13A 2

1

U12A

U15A

IN

DS1000/SO8

DS1000/SO8

7408

5 3 6 2 7

5 3 6 2 7

3

U9

5 3 6 2 7

3

TAP5 TAP4 TAP3 TAP2 TAP1

7408

7404 U10

TAP5 TAP4 TAP3 TAP2 TAP1

DS1000/SO8

IN

1

2 U11

TAP5 TAP4 TAP3 TAP2 TAP1

IN

1

2

1

1

1

7404

Vg3

Vg4

Vg2

Vg1

Figure C.6 Implementation of the VFAPWM Controller The implementation schematic of the gate signal isolation and gate drivers is shown in figure C.7. Figures C.8 and C.9 show the PCB layout for the VFAPWM converter and figures C.10 and C.11 show those of the VFPSM converter.

201

________________________________

S1

G1

S2

_Appendix C: Layouts and Components

G2

R10

S3

R9

U7

U6 1

1

Vcc

D3 2

LO

VB

COM

HO

Lin

Vs

Hin

D2 2 7

3

6

C2 4

4

5

G4

U8

R8 LO

Vcc

8

3 C3

G3

VB

COM

HO

Lin

Vs

Hin

8

1

7

D1 2

6

C1

3

5

4

ir2011

R7

Vcc

LO

VB

COM

HO

Lin

Vs

Hin

8 7 6 5

ir2011

ir2011 Vcc signal v gs1 v gs2 v gs3 v gs4 U2

gndo

2

4

3

in

out

gndi

gndo

2

4

3

v cci

OU T

7

V+

gnd1

V-

in

4

7

R4

v cc2

out

gndi

gndo

6

1

5

2

4

3

v cci in gndi

v cco out gndo

6 5 4

74OL6000

741

-

3 R3

U5 v cco

74OL6000

6

R2

v cc1

5

2

4

-

V-

2

+ R1

1

741

+

OU T

741

V+

6

74OL6000

6

74OL6000

7

U4 v cco

OU T

gndi

5

v cci

6

out

1

V+

V-

R5

gnd2

v cc34

4

-

in

3

3

signal gnd

6

2

2

U3 v cco

+

v cci

3

1

R6

gnd34

Figure C.7 Implementation of gate signal isolation and gate drive circuits

202

S4

________________________________

_Appendix C: Layouts and Components

Figure C.8 PCB layout of board 1 of the VFAPWM converter

Figure C.9 PCB layout of board 2 of the VFAPWM converter

203

________________________________

_Appendix C: Layouts and Components

Figure C.10 PCB layout of board 1 of the VFPSM converter

Figure C.11 PCB layout of board 2 of the VFPSM converter

204

________________________________

_Appendix C: Layouts and Components

The high frequency isolation transformer for the VFAPWM converter is made of a 3 winding transformer with turns ratio 2:1:1. The parameters of the transformer are obtained using the results of open circuit and short circuit analysis shown in figure C.12 are as follows, winding resistance: 785 mΩ, total leakage inductance: 1.83 µH, magnetizing inductance: 372.58 µH and core loss resistance 21.8028 kΩ:

These

parameters have been fully accounted for with a sufficient margin for tolerance in the simulation results.

(a)

(b) Figure C.12 Isolation transformer test results: (a) open circuit test, (b) short circuit test 205

________________________________

_Appendix C: Layouts and Components

The high frequency isolation transformer for the VFPSM converter is made of a 3 winding transformer with turns ratio 6:1:1. The parameters of the transformer are obtained using the results of open circuit and short circuit analysis shown in figure C.13 are as follows, winding resistance: 301.78 mΩ, total leakage inductance: 1.52 µH, magnetizing inductance: 810.4 µH and core loss resistance 48.4 kΩ.

(a)

(b) Figure C.13 Isolation transformer test results: (a) open circuit test, (b) short circuit test

206

________________________________

_Appendix C: Layouts and Components

Figure C.14 shows a sample of switching pulses for VFAPWM controlled converter.

(b)

(a)

Figure C.14 Experimental sample switching signals (a) at 190kHz, (b) at 240kHz Traces from top to bottom: vgs1, vgs2, vgs3 and vgs4 respectively Figure C.15 shows a sample of switching pulses VFPSM controlled converter.

(a)

(b)

Figure C.15 Experimental sample switching signals (a) at 180kHz, (b) at 290kHz Traces from top to bottom: vgs1, vgs2, vgs3 and vgs4 respectively

207

________________________________

_Appendix C: Layouts and Components

Finally, table C.1 lists the part numbers of the components used in the implementation. Table C.1 Component part numbers Description

Part #

Manufacturer/Distributor

MOSFETs

IRFPS43N50KPbF

International Rectifier / Newark

Driver

IR2011

International Rectifier/ Digikey

UF1006DICT-ND

Diodes Inc./ Digikey.

Rectifier

80CPQ150PbF

International Rectifier/ Digikey

DC Capacitors

DCMC472T450DE2B

Cornell Dublier/ Digikey

Input Inductor

SER2014-202ML

Coilcraft

Resonant

WIMA FKP1 Series 0.047uF

Capacitors

700VAC 2000VDC

WIMA/ R-theta

Input Rectifier

MP506W-BPMS-ND

Micro Commertial Components/ Digikey

NCT100B-T

Naional/ Newark

inductor

SER2014-202ML

Coilcraft

Input filter

WIMA MKS4 Series 6.8uF

capacitor

400VAC 630VDC

Panasonic-ECG/ Digikey

Capacitor

UVR1J471MHD

Nichicon/Digikey

Resonant

22uH, I_resonant=16Arms

Inductor

(200kHz)

Coil craft

Output filter

20uH, Io=48A

Coilcraft

Clamping diodes Output

Current Sensor Input filter

Output

Magnetics/ Dexter magnetics & New Transformer

center tap, Vs=48V, Io=48A

England Wires

Delay Lines

DS1100-250

Dallas/ Newark

Opto-couplers

74O6000

Fairchild/ Digikey

UC2823

Texas Instruments/ Digikey

UC3875

Texas Instruments/ Digikey

PWM Controller Phase shift Controller

207

________________________________

_Appendix C: Layouts and Components

Table C.2 Controller parameters VFAPWM-DCM

VFAPWM-CCM

VFPS

Input Resistor:400kΩ

Input Resistor:100kΩ

Input Resistor:200kΩ

Feedback Resistor:200 kΩ

Feedback Resistor:2kΩ

Feedback Resistor:150 kΩ

Feedback capacitor: 4.4nF

Feedback capacitor: 4.7nF

Feedback capacitor: 4.7nF

Pole capacitor: 47pF Output Loop: Input Resistor:100kΩ, Feedback Resistor:500kΩ,Feedback capacitor: 300pF

208

________________________________________________Appendix D: Converter Modelling

Appendix D Converter Modelling

[

xˆ dq = iˆsq

[

xˆ dql = Vˆ1ql

Bˆ dq

iˆsd Vˆ1dl

⎡ − 2π (V1q ⎢ ⎢ ⎢ − 2π (V1d ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ =⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢⎣

vˆ sq

vˆ sd

Vˆ2 ql

vˆ pq Vˆ2 dl

vˆ pd

Vˆ1q

iˆLinql

iˆLindl

+ V1q ) cos(2π (1 − D )) Ls + V1d ) sin(2π (1 − D )) Ls 0 0 0 0 (i Linq − i sq ) C b1 (i Lind − i sd ) C b1 (i Linq − i sq ) Cb 2 (i Lind − i sd ) Cb 2 (V1q + V2 q ) Lin (V1q + V2 q ) Lin

Vˆ1d

Vˆ2 q

]

t

Vˆ2 d

iˆLinq

iˆLinq

]

t

(D.1) (D.2)

− i sd i sq − v sd v sq − v pd v pq − V1d V1q − V2 d V2 q − i Lind i Linq

210

⎤ 0⎥ ⎥ ⎥ 0⎥ ⎥ 0⎥ 0⎥ ⎥ 0⎥ 0⎥ ⎥ ⎥ 0⎥ ⎥ 0⎥ ⎥ ⎥ 0⎥ ⎥ ⎥ 0⎥ ⎥ ⎥ 0⎥ ⎥ ⎥ 0⎥ ⎥⎦

(D.3)

________________________________________________Appendix D: Converter Modelling

Bˆ dql

⎡ i Linql ⎢ C b1 ⎢ ⎢ i Lindl ⎢ C b1 ⎢ ⎢ − i Linql ⎢ Cb 2 =⎢ i ⎢ − Lindl ⎢ Cb 2 ⎢ (V + V ) 2 ql ⎢ 1ql ⎢ Lin ⎢ (V + V ) 2 dl ⎢ 1dl L in ⎣⎢

⎡ Aˆ Let Aˆ dq = ⎢ 1 ˆ ⎣ A3

0 0 0 0 0 0

⎤ 0 ⎥ ⎥ ⎥ 0 ⎥ ⎥ 0 ⎥⎥ ⎥ 0 ⎥ ⎥ ⎥ 8 ⎥ 3πLin ⎥ ⎥ 0 ⎥ ⎦⎥

(D.4)

Aˆ 2 ⎤ ⎥ Aˆ 4 ⎦

⎡ ⎢ 0 ⎢ ⎢ω ⎢ s ⎢ 1 ⎢ ⎢C Therefore, Aˆ1 = ⎢ s ⎢ 0 ⎢ ⎢ 1 ⎢C p ⎢ ⎢ 0 ⎢⎣

⎡ sin(2π (1 − D )) ⎢ Ls ⎢ ⎢ 0 ⎢ Aˆ 2 = ⎢ 0 ⎢ ⎢ 0 ⎢ 0 ⎢ ⎢⎣ 0

(D.5)

− ωs

1 Ls

−

−

0

1 Ls

0

0

−

1 Ls

0

0

0

− ωs

0

1 Cs

ωs

0

0

0

0

0

1 Cp

0

0

sin(2π (1 − D )) Ls 0 0 0 0 0

−

1 C p Rac

ωs

⎤ ⎥ ⎥ 1 ⎥ − Ls ⎥ ⎥ 0 ⎥ ⎥ ⎥ 0 ⎥ ⎥ − ωs ⎥ ⎥ ⎥ 1 ⎥ − C p Rac ⎥⎦ 0

(D.6)

0

0

1 − cos(2π (1 − D )) Ls 0 0 0 0

1 − cos(2π (1 − D )) Ls 0 0 0 0

⎤ 0 0⎥ ⎥ 0 0⎥⎥ ⎥ 0 0⎥ 0 0⎥ ⎥ 0 0⎥ 0 0⎥⎦

………. (D.7)

211

________________________________________________Appendix D: Converter Modelling

⎡ 1− D ⎢− C b1 ⎢ ⎢ 0 ⎢ ⎢ ˆA = ⎢ D 3 ⎢ Cb 2 ⎢ ⎢ 0 ⎢ ⎢ 0 ⎢ ⎣ 0 ⎡ ⎢ 0 ⎢ ⎢ ω s ⎢ ⎢ ⎢ 0 ⎢ Aˆ 4 = ⎢ ⎢ 0 ⎢ ⎢ 1− D ⎢− ⎢ Lin ⎢ ⎢ 0 ⎣

Aˆ dql

⎡ ⎢ 0 ⎢ ⎢ 2ω l ⎢ ⎢ ⎢ 0 ⎢ =⎢ ⎢ 0 ⎢ ⎢ 1− D ⎢− ⎢ Lin ⎢ ⎢ 0 ⎣

0 −

1− D C b1 0 D Cb2 0 0

⎤ 0 0 0 0⎥ ⎥ 0 0 0 0⎥ ⎥ ⎥ 0 0 0 0⎥ ⎥ ⎥ 0 0 0 0⎥ ⎥ 0 0 0 0⎥ ⎥ 0 0 0 0⎦

− ωs

0

0

1− D C b1

0

0

0

0

0

0

−ω s

1− D Cb 2

0 0 −

(D.8)

1− D Lin

−

ωs

0

0

1− D Lin

0

0

1− D Lin

ωs

0

−

− 2ω l

0

0

1− D C b1

0

0

0

0

0

0

− 2ω l

1− D Cb 2

0 0 −

1− D Lin

−

2ω l

0

0

1− D Lin

0

0

1− D Lin

2ω l

0

−

⎤ 0 ⎥ ⎥ 1− D ⎥ C b1 ⎥ ⎥ 0 ⎥ ⎥ 1− D ⎥ ⎥ Cb 2 ⎥ ⎥ − ωs ⎥ ⎥ ⎥ 0 ⎥ ⎦ ⎤ 0 ⎥ ⎥ 1− D ⎥ C b1 ⎥ ⎥ 0 ⎥ ⎥ 1− D ⎥ ⎥ Cb 2 ⎥ ⎥ − 2ω l ⎥ ⎥ ⎥ 0 ⎥ ⎦

(D.9)

(D.10)

A similar approach is followed for the other modes of operation of this family of converters.

212

________________________________

___________ _Appendix E: Programs

Appendix E Matlab Programs E.1 Circuit Performance Analysis warning off; clear all; Ls=17e-6;Cs=47e-9;Cp=94e-9;a=6; Vs=400; Rl=1; f=170000; D=0.5; for f=220000:17500:220000 h=0; for x=1:0.125:5 h=h+1;Rac=(pi^2)*a^2*Rl/8;Cp=Cs*x; for n=1:21 %alpha(n)=2*pi*n*(1-D); Vm(n)=(-1)^((n-1)/2)*Vs*sin(n*pi*D)/n/pi; phi(n)=0; w(n)=2*pi*f*n; Re_Ztot(n)=Rac/(1+(n*w(n)*Rac*Cp)^2); Im_Ztot(n)=n*w(n)*Ls-1/(n*w(n)*Cs)-(n*w(n)*Cp*Rac^2)/(1+(n*w(n)*Rac*Cp)^2); Im_Zp(n)=-(n*w(n)*Cp*Rac^2)/(1+(n*w(n)*Rac*Cp)^2); magVp(n)=Vm(n)*sqrt(Re_Ztot(n)^2+Im_Zp(n)^2)/sqrt(Re_Ztot(n)^2+Im_Ztot(n)^2); phiVp(n)=phi(n)-atan(Im_Ztot(n)/Re_Ztot(n))+atan(Im_Zp(n)/Re_Ztot(n)); end i=0; Vptot(h)=0; for n=1:21 i=i+1; Vptot(h)=sqrt((Vptot(h)^2)+(magVp(n))^2); end Vo(h)=(1/(a))*(Vptot(h)); end x=1:0.125:5; plot(x,Vo) 213

________________________________

___________ _Appendix E: Programs

hold on end %______________________________________________________________________ D=0.4; h=0; for Rl=1:10 h=h+1;Rac=(pi^2)*a^2*Rl/8; for n=1:21 alpha(n)=2*pi*n*(1-D); Vm(n)=((Vs*2^1.5)/(n*pi))*sqrt(1-cos(alpha(n))); phi(n)=atan(sin(alpha(n))/(1-cos(alpha(n)))); w(n)=2*pi*f*n; Re_Ztot(n)=Rac/(1+(n*w(n)*Rac*Cp)^2); Im_Ztot(n)=n*w(n)*Ls-1/(n*w(n)*Cs)-(n*w(n)*Cp*Rac^2)/(1+(n*w(n)*Rac*Cp)^2); Im_Zp(n)=-(n*w(n)*Cp*Rac^2)/(1+(n*w(n)*Rac*Cp)^2); magVp(n)=Vm(n)*sqrt(Re_Ztot(n)^2+Im_Zp(n)^2)/sqrt(Re_Ztot(n)^2+Im_Ztot(n)^2); phiVp(n)=phi(n)-atan(Im_Ztot(n)/Re_Ztot(n))+atan(Im_Zp(n)/Re_Ztot(n)); end i=0; for t=0:0.1e-6:10e-6 i=i+1;Vp(i,h)=0; for n=1:21 Vp(i,h)=Vp(i,h)+magVp(n)*sin(w(n)*t+phiVp(n)); end end Vo(h)=(2/(pi*a))*max(Vp(:,h)); end %______________________________________________________________________ h=0; for f=170000:15000:260000 h=h+1; for n=1:21 alpha(n)=2*pi*n*(1-D); Vm(n)=((Vs*2^1.5)/(n*pi))*sqrt(1-cos(alpha(n))); phi(n)=atan(sin(alpha(n))/(1-cos(alpha(n)))); w(n)=2*pi*f*n; Re_Ztot(n)=Rac/(1+(n*w(n)*Rac*Cp)^2); Im_Ztot(n)=n*w(n)*Ls-1/(n*w(n)*Cs)-(n*w(n)*Cp*Rac^2)/(1+(n*w(n)*Rac*Cp)^2); Im_Zp(n)=-(n*w(n)*Cp*Rac^2)/(1+(n*w(n)*Rac*Cp)^2); magVp(n)=Vm(n)*sqrt(Re_Ztot(n)^2+Im_Zp(n)^2)/sqrt(Re_Ztot(n)^2+Im_Ztot(n)^2); phiVp(n)=phi(n)-atan(Im_Ztot(n)/Re_Ztot(n))+atan(Im_Zp(n)/Re_Ztot(n)); end i=0; for t=0:0.1e-6:10e-6

214

________________________________

___________ _Appendix E: Programs

i=i+1;Vp(i,h)=0; for n=1:21 Vp(i,h)=Vp(i,h)+magVp(n)*sin(w(n)*t+phiVp(n)); end end Vo(h)=(2/(pi*a))*max(Vp(:,h)); end

E.2 Digital Controller library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_signed.all; library dspbuilder; use dspbuilder.dspbuilderblock.all; library lpm; use lpm.lpm_components.all; Entity x3 is Port( clock : in std_logic; sclrp : in std_logic:='0'; iA2D_112BitSigneds : in std_logic_vector(11 downto 0); iA2D_212BitSigned1s : in std_logic_vector(11 downto 0); oD2A_114BitUnsigneds

:

out

downto 0); oLED0s oLED1s

: :

out std_logic; out std_logic

); end x3; architecture aDspBuilder of x3 is signal sclr signal A0W signal A1W signal A2W signal A3W signal A4W signal A5W signal A6W signal A7W signal A8W signal A9W

: : : : : : : : : : :

std_logic:='0'; std_logic_vector(11 downto 0); std_logic_vector(11 downto 0); std_logic_vector(8 downto 0); std_logic_vector(8 downto 0); std_logic_vector(9 downto 0); std_logic_vector(20 downto 0); std_logic_vector(20 downto 0); std_logic_vector(30 downto 0); std_logic_vector(21 downto 0); std_logic_vector(21 downto 0); 215

std_logic_vector(13

________________________________ signal A10W signal A11W signal A12W signal A13W signal A14W signal A15W signal A16W signal A17W signal A18W signal A19W signal A20W signal A21W signal sclr_u18 signal sclr_u19 signal sclr_u20

: : : : : : : : : : : :

___________ _Appendix E: Programs

std_logic_vector(15 downto 0); std_logic_vector(7 downto 0); std_logic_vector(7 downto 0); std_logic; std_logic; std_logic; std_logic_vector(8 downto 0); std_logic_vector(7 downto 0); std_logic_vector(7 downto 0); std_logic_vector(16 downto 0); std_logic_vector(8 downto 0); std_logic; : std_logic; : std_logic; : std_logic;

Begin assert (1<0) report altversion severity Note; -- Output - I/O assignment from Simulink Block "D2A_114BitUnsigned" oD2A_114BitUnsigneds(1) <= '0'; oD2A_114BitUnsigneds(2) <= '0'; oD2A_114BitUnsigneds(3) <= '0'; oD2A_114BitUnsigneds(4) <= '0'; oD2A_114BitUnsigneds(5) <= '0'; oD2A_114BitUnsigneds(6) <= '0'; oD2A_114BitUnsigneds(7) <= '0'; oD2A_114BitUnsigneds(8) <= '0'; oD2A_114BitUnsigneds(9) <= '0'; oD2A_114BitUnsigneds(10) <= '0'; oD2A_114BitUnsigneds(11) <= '0'; oD2A_114BitUnsigneds(12) <= '0'; oD2A_114BitUnsigneds(13) <= '0'; oD2A_114BitUnsigneds(0) <= A15W; -- Output - I/O assignment "LED0" oLED0s <= A11W(0); -- Output - I/O assignment "LED1" oLED1s <= A12W(0); sclr <= sclrp; -- Input - I/O assignment "iA2D_112BitSigneds" A0W <= iA2D_112BitSigneds;

216

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___________ _Appendix E: Programs

-- Input - I/O assignment "iA2D_212BitSigned1s" A1W <= iA2D_212BitSigned1s; -- Constant assignment - "Constant2" A2W(8) <= '0'; A2W(7 downto 0) <= "11111111"; -- Constant assignment - "Constant3" A3W(8) <= '0'; A3W(7 downto 0) <= "00000001"; -- Constant assignment - "Constant4" A4W(9 downto 0) <= "0000000000"; sclr_u18 <= A13W or sclr; A16W(8) <= '0'; sclr_u19 <= A14W or sclr; sclr_u20 <= A14W or sclr; A19W(16) <= '0'; A20W(8) <= '0'; -- "GND" A21W

<=

'0';

-- Gain Operator - "Gain1" Gain1i : AltiMult generic map ( LPM_WIDTHA =>12, LPM_WIDTHB =>9, SequenceLength =>1, SequenceValue =>1, PIPELINE =>0, one_input =>1, lpm_hint => "UNUSED", lpm =>0, cst_val =>"000001010", dspb_widthr =>21) port map ( DATAA => A0W, clock => '0', ena => '1', sclr => '0', result => A5W);

-- Gain Operator - "Gain2" Gain2i : AltiMult generic map ( LPM_WIDTHA =>12,

217

________________________________

___________ _Appendix E: Programs

LPM_WIDTHB =>9, SequenceLength =>1, SequenceValue =>1, PIPELINE =>0, one_input =>1, lpm_hint => lpm =>0, cst_val =>"000000010", dspb_widthr =>21)

"UNUSED",

port map ( DATAA clock ena sclr result

=> => => =>

=> A1W, '0', '1', '0', A6W);

-- Gain Operator - "Gain3" Gain3i : AltiMult generic map ( LPM_WIDTHA =>22, LPM_WIDTHB =>9, SequenceLength =>1, SequenceValue =>1, PIPELINE =>0, one_input =>1, lpm_hint => "UNUSED", lpm =>0, cst_val =>"000010100", dspb_widthr =>31) port map ( DATAA => A9W, clock => '0', ena => '1', sclr => '0', result => A7W); -- Sum Operator - "ParallelAdderSubtractor" ParallelAdderSubtractori : SAdderSub generic map ( LPM_WIDTH =>21, PIPELINE =>1, SequenceLength =>1, SequenceValue =>1, AddSubVal =>AddAdd) port map ( dataa => A5W, datab(7 downto 0) => A17W(7 downto 0), datab(8) => A17W(7),

218

________________________________ datab(9) datab(10) datab(11) datab(12) datab(13) datab(14) datab(15) datab(16) datab(17) datab(18) datab(19) datab(20) clock ena sclr result

___________ _Appendix E: Programs => A17W(7), => A17W(7), => A17W(7), => A17W(7), => A17W(7), => A17W(7), => A17W(7), => A17W(7), => A17W(7), => A17W(7), => A17W(7), => A17W(7), =>clock, => '1', => sclr, => A8W);

-- Sum Operator - "ParallelAdderSubtractor1" ParallelAdderSubtractor1i : SAdderSub generic map ( LPM_WIDTH =>21, PIPELINE =>1, SequenceLength =>1, SequenceValue =>1, AddSubVal =>AddAdd) port map ( dataa => A6W, datab(7 downto 0) => A18W(7 downto 0), datab(8) => A18W(7), datab(9) => A18W(7), datab(10) => A18W(7), datab(11) => A18W(7), datab(12) => A18W(7), datab(13) => A18W(7), datab(14) => A18W(7), datab(15) => A18W(7), datab(16) => A18W(7), datab(17) => A18W(7), datab(18) => A18W(7), datab(19) => A18W(7), datab(20) => A18W(7), clock =>clock, ena => '1', sclr => sclr, result => A9W); -- Divide Operator - "Divider"

219

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___________ _Appendix E: Programs

Divideri : divider generic map ( widthin =>16, isunsigned =>0, pipeline =>0) port map ( numer(15 downto 0) denom(15 downto 0) quotient => -- Divide Operator - "Divider1" Divider1i : divider generic map ( widthin =>8, isunsigned =>0, pipeline =>0) port map ( numer(7 downto 0) denom(7 downto 0) quotient remain =>

=> A19W(15 downto 0), => A8W(15 downto 0), A10W);

=> A7W(7 downto 0), => A20W(7 downto 0), => A11W, A12W);

-- Compare Operator - "Comparator" Comparatori : Comparator generic map ( LPM_WIDTH =>22, DIRECTION=> Altageb, LPM=> 0) port map ( DATAA(8 downto 0) => A16W(8 downto 0), DATAA(9) => A16W(8), DATAA(10) => A16W(8), DATAA(11) => A16W(8), DATAA(12) => A16W(8), DATAA(13) => A16W(8), DATAA(14) => A16W(8), DATAA(15) => A16W(8), DATAA(16) => A16W(8), DATAA(17) => A16W(8), DATAA(18) => A16W(8), DATAA(19) => A16W(8), DATAA(20) => A16W(8), DATAA(21) => A16W(8), DATAB => A8W, result => A13W); -- Compare Operator - "Comparator1" Comparator1i : Comparator generic map ( LPM_WIDTH =>10,

220

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___________ _Appendix E: Programs

DIRECTION=> Altageb, LPM=> 0) port map ( DATAA(8 downto 0) => A16W(8 downto 0), DATAA(9) => A16W(8), DATAB => A4W, result => A14W); -- Compare Operator - "Comparator2" Comparator2i : Comparator generic map ( LPM_WIDTH =>31, DIRECTION=> Altaleb, LPM=> 0) port map ( DATAA(8 downto 0) => A20W(8 downto 0), DATAA(9) => A20W(8), DATAA(10) => A20W(8), DATAA(11) => A20W(8), DATAA(12) => A20W(8), DATAA(13) => A20W(8), DATAA(14) => A20W(8), DATAA(15) => A20W(8), DATAA(16) => A20W(8), DATAA(17) => A20W(8), DATAA(18) => A20W(8), DATAA(19) => A20W(8), DATAA(20) => A20W(8), DATAA(21) => A20W(8), DATAA(22) => A20W(8), DATAA(23) => A20W(8), DATAA(24) => A20W(8), DATAA(25) => A20W(8), DATAA(26) => A20W(8), DATAA(27) => A20W(8), DATAA(28) => A20W(8), DATAA(29) => A20W(8), DATAA(30) => A20W(8), DATAB => A7W, result => A15W); -- DSP Builder Block - "Counter" Counteri : sLpmCount Generic map ( width => 8, modulus => 256) port map ( clock => clock, sclr => sclr_u18,

221

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___________ _Appendix E: Programs

data(0) data(1) data(2) data(3) data(4) data(5) data(6) data(7) sload updown clk_en q(7 downto 0)

=> => => => => => => => => => =>

A21W, '0', '0', '0', '0', '0', '0', '0', A21W, => A3W(0), A3W(0), A16W(7 downto 0));

-- DSP Builder Block - "Integrator" Integratori : sIntegratorAltr Generic map ( width => 8) port map ( clock => clock, sclr => sclr_u19, data(7 downto 0) => clk_en => A3W(0), q => A17W); -- DSP Builder Block - "Integrator1" Integrator1i : sIntegratorAltr Generic map ( width => 8) port map ( clock => clock, sclr => sclr_u20, data(7 downto 0) => clk_en => A3W(0), q => A18W);

A0W(7 downto 0),

A1W(7 downto 0),

-- DSP Builder Block - "Multiplier" Multiplieri : sMultAltr Generic map ( pipeline => 0, lpm_representation => "UNSIGNED", OutputMsb => 15, OutputLsb => 0, lpm_width => 8, lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=AUTO") port map ( clock => '1', sclr => '0', ena => '1',

222

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___________ _Appendix E: Programs

dataa(7 downto 0) datab(7 downto 0) result(15 downto 0)

=>

=> A16W(7 downto 0), => A2W(7 downto 0), A19W(15 downto 0));

-- Bus Conversion - "BusConversion" BusConversioni : SRED generic map( widthin=>16, widthout=>8, msb=>7, lsb=>0, round=>0, lpm_signed=>BusIsUnsigned, satur=>0) port map ( xin(15 downto 0) =>A10W(15 downto 0), yout => A20W(7 downto 0)); end architecture aDspBuilder;

223

______________________________

___________ _Appendix F: Comparison

Appendix F Comparison of the Proposed Converters

Table F.1 Comparison between PFC topologies Topology Two Stage (Boost+ Full Bridge)

Single Stage (VFAPWM)

Singe Stage (VFPSM)

Total Power Switches Bus Voltage (V)

2.3kW 5 450

Switch Voltage (V) Active current control?

450 Yes

2.3kW 4 400800(controlled) 200-400 No

Efficiency (%) @ 200kHz Control complexity Input current DC/DC converter freq. range (VF control) ZVS

Approx. 90-91% (estimated) Medium CCM 1-7fs

2.3kW 4 400-650 (controlled) 200-325 Depends on choice of operation mode 94% (measured)

91.2%(measured)

Medium CCM or DCM 1-2.5fs

Easy DCM 1-3fs

Obtained through natural operation

Obtained through natural operation

Feature

Auxiliary circuit(s) required

224

QUEEN’S UNIVERSITY Department of Electrical and Computer Engineering

Mohammed Agamy, Ph.D. Mohammed Agamy was born in Hamilton, Ontario and attended primary and secondary school in Alexandria, The Department of Electrical and Computer Engineering is very pleased to announce that,

Mohammed Agamy was awarded the Ph.D. degree on May 26, 2008.

Egypt. He received his B.Sc. and M.Sc. degrees in Electrical Engineering from Alexandria University, Egypt in 2000 and 2003, respectively and the Ph.D. from Queen’s University in 2008. He was an assistant lecturer at Alexandria University from September 2000- April 2003, and in May 2003 he joined the Energy and Power Electronics Applied Research Laboratory at Queen’s University to pursue his Ph.D. degree. For his doctoral research at Queen’s, he investigated new topologies and control methods to increase the power handling capability of single-phase single-stage power factor correction converters, under the

Department of Electrical and Computer Engineering Queen’s University 19 Union Street Kingston, Ontario Canada K7L 3N6

supervision of Professor P.K. Jain. Dr. Agamy was the recipient of several scholarships during his graduate studies, including an Ontario Graduate Scholarship and an IEEE-IES student scholarship. Life after Queen’s — Dr. Agamy is currently a post-doctoral fellow at the Energy & Power Electronics Applied Research Laboratory where he is continuing his research on topologies and analog and digital

Phone: 613-533-2925 Fax: 613-533-6615 E-mail: [email protected]

control techniques of single-stage power factor correction converters for telecom and computer applications.