Diodes For Power Electronic Applications: Lecture Notes

Lecture Notes

Diodes for Power Electronic Applications

OUTLINE

• PN junction power diode construction • Breakdown voltage considerations • On-state losses • Switching characteristics • Schottky diodes • Modeling diode behavior with PSPICE

Copyright © by John Wiley & Sons 2003

Diodes - 1

Basic Structure of Power Semiconductor Diodes Anode

i P+

v

N- epi

N+ substrate

10 microns

19 -3 N = 10 cm A

breakdown voltage dependent

14 -3 N = 10 cm D 19 -3 N = 10 cm D

250 microns

Cathode

anode

i 1

i v

v

R on

BVBD ≈ 1 V

v

cathode Copyright © by John Wiley & Sons 2003

Diodes - 2

Breakdown Voltage Estimate - Step Junction Φ

¥ N on-punch-through diode. Drift region length W d > W (BV BD ) =

W(V)

length of space charge region at breakdow n.

x Φ

¥ W (V ) = W o

∞ Ωο =

1+V /Φχ

χ

Φχ + ς

2 εΦχ( Να+ Νδ ) θ ΝαΝδ

2Φ χ ¥ Em ax = 1 ⊇+ ⊇ς / Φ χ Ωο ∞ Πο ω ε ρ δ ιο δ ε ατ ρε ϖε ρσε β ρε ακ δ ο ω ν: Να >> Νδ ; Ε = ΕΒ∆ ; ς = Βς Β∆ >> Φ χ Ω ο 2 ⊇Βς Β∆ 2 εΦ χ 2 2 = ∞ Ω ( Βς Β∆ ) = ; Ω ο Φχ θ ⊇Νδ

¥ Conclusions

4ÊΦ χ

¥

(Em ax )2 = (EBD )2 =

∞

Σο λϖε φο ρ Ω ( Βς Β∆ ) ανδ Βς Β∆ το ο β ταιν ( π υτ ιν Σι ϖαλυε σ) ε⊇ΕΒ∆ 2 1 .3 ξ 1 0 1 7 Βς Β∆ = = ; [ς ] 2 ⊇θ ⊇Νδ Νδ

Ω ο2

Βς Β∆

2 ⊇Βς Β∆ Ω ( Βς Β∆ ) = = 1 0 −5 Βς Β∆ ; [∝µ ] ΕΒ∆

1.Large BV BD (10 3 V ) requires N d < 10 15 cm -3 2.Large BV BD (10 3 V ) requires N - drift region > 100 µ m

Copyright © by John Wiley & Sons 2003

Diodes - 3

Breakdown Voltage - Punch-Through Step Junction ¥ Punch-through step junction - W (BV BD ) > W d - V + + P

N-

W

N

d

V E 2

¥ V 1 + V 2 = BV BD ¥ E1 + E2 = EBD

+

Electric field

E + E2 1

¥ A t breakdow n:

1

qN dW d2 ¥ BV BD = EBD W d 2ε

∞ Ιφ Νδ < <

V2

x

ε( ΕΒ∆) 2

( ρε θ υιρε δ 2 θ ( Βς Β∆ ) ϖαλυε οφ Νδ φορ νον−πυνχη−τηρυ δ ιοδ ε ) , τηε ν

¥ E1 = ∞

qN dW d

ε

;ς1 =

θ Νδ Ω δ 2

ς 2 = Ε2 Ω δ

Copyright © by John Wiley & Sons 2003

2ε

∞ ∞

Βς Β∆ ⊕ ΕΒ∆ Ω δ ανδ Ω δ ( Πυνχη−τηρυ) ⊕ 0 .5 Ω δ ( νον−πυνχη−τηρυ) Diodes - 4

Effect of Space Charge Layer Curvature incident acceptor impurities diffusing acceptor SiO2 impurities

P depletion layer

¥ If radius of curvature is comparable to depletion layer thickness, electric field becomes spatially nonuniform.

+ R NN

¥ Spatially nonuniform electric field reduces breakdown voltage.

+

¥ Impurities diffuse as fast laterally as vertically

¥ Curvature develops in junction boundary and in depletion layer.

Copyright © by John Wiley & Sons 2003

¥ R > 6 W(BVBD) in order to limit breakdown voltage reduction to 10% or less. ¥ Not feasible to keep R large if BVBD is to be large ( > 1000 V).

Diodes - 5

Control of Space Charge Layer Boundary Contour field plates

• Electrically isolated conductors (field plates) act as equipotential surfaces.

P+ depletion layer boundary

N

SiO 2 P depletion layer boundary

P+ guard N

P

ring -

N+ aluminum contact

Copyright © by John Wiley & Sons 2003

• Correct placement can force depletion layer boundary to have larger radius of curvature and t;hus minimize field crowding. • Electrically isolated p-regions (guard rings)has depletion regions which interact with depletion region of main pn junction. • Correct placement of guard rings can result in composite depletion region boundary having large radius of curvature and thus minimize field crowding. Diodes - 6

Surface Contouring to Minimize Field Crowding depletion layer boundary

+ N N-

SiO

N+

2 N-

P+ bonding pad

P+ bonding pad

high field region

• Large area diodes have depletion layers that contact Si surface. • Difference in dielectric constant of Si and air causes field crowding at surface. • Electric fields fringing out into air attract impurities to surface that can lower breakdown voltage. Copyright © by John Wiley & Sons 2003

• Proper contouring of surface can mimimize depletion layer curvature and thus field crowding. • Use of a passivation layer like SiO2 can also help minimize field crowding and also contain fringing fields and thus prevent attraction of impurities to surface. Diodes - 7

Conductivity Modulation of Drift Region • Forward bias injects holes into drift region from P+ layer. Electrons attracted into drift region from N+ layer. So-called double injection.

x P

+

+

N

-

-

N+

W d p(x) = n(x) 16

= n a= 10

n p(x) n

log scale

• If Wd ≤ high level diffusion length La , carrier distributions quite flat with p(x) ≈ n(x) ≈ na.

po

n no= 10 p

no

14

= 10 6

• For na >> drift region doping Nd, the resistance of the drift region will be quite small. So-called conductivity modulation.

p (x) n p no

x

Copyright © by John Wiley & Sons 2003

• On-state losses greatly reduced below those estimated on basis of drift region low-level (Nd) ohmic conductivity. Diodes - 8

Drift Region On-State Voltage Estimate QF

¥ IF = = τ

θ⊇Α⊇Ω δ ⊇να τ

; Χυρρεντ νεεδεδ

το µαινταιν στορεδ χηαργε Θ Φ.

W d

θ⊇[∝ ν⊇+⊇∝π ]⊇ν α⊇Α⊇ς δ ∞ ΙΦ = ; Ωδ

x

Οηµ∏σ Λαω (ϑ = σΕ) P

Ωδ2

∞ ςδ= ; Εθυατε αβοϖε ⊇[∝ν⊇+⊇∝π ]⊇τ τωο εθυατιονσ ανδ σολϖε φορ ς δ

+

+

N

IF +V j

+

-

V d

-

N+

Cross-sectional area = A

∞ Χονχλυσιον: λονγ λιφετιµε τ µινιµιζεσ ς δ .

Copyright © by John Wiley & Sons 2003

Diodes - 9

Diode On-State Voltage at Large Forward Currents ¥ µn + µp =

µo na 1Ê+Ê nb

; nb Å 10 17 cm -3 .

¥ M obility reduction due to increased carrier-carrier scattering at large na.

qÊnaÊA ÊV d ¥ IF = Wd

µo na 1Ê+Ê nb

; O hm s Law

w ith density-dependent m obility.

¥ Invert O hm Õs Law equation to find V d as function IF assum ing na >> nb.

IfÊW d ¥ Vd = qʵoÊnbÊA

¥ V d = IF Ron

¥ V = V j+ V d Copyright © by John Wiley & Sons 2003

Diodes - 10

Diode Switching Waveforms in Power Circuits Q rr = I di

F

/ dt

d i / dt R

I F

rr

t

rr

0.25

/2

I rr

t

I

t

V

FP

t

t 4

3

V on

rr

5

¥ t

rr

t t 2 t

1

Copyright © by John Wiley & Sons 2003

t S =

t

V

rr

V

R

¥

diF diR and determined dt dt by external circuit. Inductances or power semiconductor devices.

5 4

Diodes - 11

Diode Internal Behavior During Turn-on t 1

i F

+ P (t)

+ + + +

C sc

interval N -

Rd

i (t) F

Λ = στραψ ορ ωιρινγ ινδυχτανχε

L

t P+

δι Φ ς ΦΠ ⊕ Ι Φ Ρ δ + Λ δτ

ε⊇Α C sc(V) = ⊇Ω(ς) Ωδ Ρδ = θ⊇µ ν ⊇Νδ ⊇Α

N+

- + - + - +

2

interval N -

N+

V j Å 1.0 V time time

• Injection of excess carriers into drift region greatly reduces Rd.

time

x

Copyright © by John Wiley & Sons 2003

Diodes - 12

Diode Internal Behavior During Turn-off t i (t) R

P

3

-

- + - + +

+

t 4 N

interval N+

-

¥ R d increases as excess carriers are rem oved via recom bination and carrier sw eep-out (negative current).

V j Å 1.0 V C

sc

Rd

L time time

time

diR ¥ V r = IrrR d + L dt x

ts inte rv al ¥ Insufficient excess carriers rem ain to support Irr,so P + N - junction becom es reverse-biased and current decreases to zero. ¥ V oltage drops from V rr to V R as current decreases to zero.N egative current integrated over its tim e duration rem oves a total charge Q rr.

Copyright © by John Wiley & Sons 2003

Diodes - 13

Factors Effecting Reverse Recovery Time diR diR trr ¥ Irr = t = ; Defined on dt 4 dt(SÊ+Ê1) sw itching w aveform diagram

IrrÊ trr diR trr2 ¥ Q rr = = ; Defined 2 dt 2(SÊ+Ê1) on w aveform diagram

¥ If stored charge rem oved m ostly by sw eep-out Q rr Å Q F Å IF τ

∞ Υσινγ τηισ ιν ε θ σ. φορ Ιρρ ανδ τρρ ανδ ασσυµ ινγ Σ + 1 ⊕ 1 γ ιϖε σ

τρρ =

2 ⊇ΙΦ⊇τ δ ιΡ

ανδ

δτ ¥ Inverting Q rr equation to solve for trr yields

trr =

2Q rr(S+1) diR dt

and Irr =

Copyright © by John Wiley & Sons 2003

diR 2Q rr dt

Ιρρ =

δ ιΡ 2 ⊇ΙΦ⊇τ⊇ δτ

(SÊ+Ê1)

Diodes - 14

Carrier Lifetime-Breakdown Voltage Tradeoffs ¥ Low on-state losses require L =

DÊ τ =

κΤ ⊇τ θ⊇[∝ ν ⊇+⊇∝π ]

Λ = Ω δ ≥ Ω(ς) = 10

−5 Βς

Β∆

∞ Σολϖινγ φορ τηε λιφετιµε ψιελδσ Ω δ2 τ= = 4ξ10 −12 (Βς Β∆ ) 2 (κΤ/θ)⊇[∝ ν +∝π ]

∞ Συβστιτυτινγ φορ τ ιν Ιρρανδ τ ρρεθυατιονσ γιϖεσ ∞ τρρ= 2.8ξ10

−6 Βς Β∆

∞ Ιρρ= 2.8ξ10

−6 Βς Β∆

Copyright © by John Wiley & Sons 2003

ΙΦ (δι Ρ /δτ)

Conclusions 1. Higher breakdow n voltages require larger lifetim es if low on-state losses are to be m aintained. 2. High breakdow n voltage devices slow er than low breakdow n voltage devices. 3. Turn-off tim es shortened diR by large but Irr is dt increased.

διΡ ΙΦ⊇ δτ Diodes - 15

Schottky Diodes anode

Characteristics ¥ V (on) = 0.3 - 0.5 volts.

SiO2

P

P

¥ Breakdow n voltages ² 100-200 volts.

¥ M ajority carrier device - no stored charge.

guard ring depletion layer boundary with guard rings

N

¥ Fast sw itching because of lack of stored charge.

depletion layer boundary without guard rings

N+

cathode

Copyright © by John Wiley & Sons 2003

aluminum contact rectifying

aluminum contact ohmic Diodes - 16

Physics of Schottky Diode Operation

¥ Electrons diffuse from Sito A l because electrons have larger average energy in silicon com pared to alum inum . ¥ Depletion layer and thus potential barrier set up.Gives rise to rectifying contact. ¥ No hole injection into silicon.No source of holes in alum inum .Thus diode is a m ajority carrier device. ¥ Reverse saturation current m uch larger than in pn junction diode. This leads to sm aller V (on) (0.3 0.5 volts)

Copyright © by John Wiley & Sons 2003

+ V -

i(t) Aluminum

n-type Si Electron Energy E

E Al

Al Diffusing electrons

-

-

+ + +

Si

N-Si

Depletion layer

Diodes - 17

Schottky Diode Breakdown Voltage ¥ Breakdow n voltage lim ited to 100-200 volts. ¥ Narrow depletion region w idths because of heavier drift region doping needed for low on-state losses. ¥ Sm allradius of curvature of depletion region w here m etallization ends on surface of silicon.Guard rings help to m itigate this problem . ¥ Depletion layer form s right at silicon surface w here m axim um field needed for breakdow n is less because of im perfections,contam inants. Copyright © by John Wiley & Sons 2003

Diodes - 18

Schottky Diode Switching Waveforms ¥ Schottky diodes sw itch m uch faster than pn junction diodes.No m inority carrier storage.

Current I F

¥ Forew ard voltage overshoot V FP

t

m uch sm aller in Schottky diodes. Drift region ohm ic resistance RΩ. ∞ Ρε ϖε ρσε ρε χοϖε ρψ τιµ ε τρρ µ υχη σµ αλλε ρ ιν Σχηοττκψ δ ιοδ ε σ. Νο µ ινοριτψ χαρριε ρ στοραγ ε . ∞ Ρε ϖε ρσε ρε χοϖε ρψ χυρρε ντ Ιρρ χοµ παραβλε το πν ϕυνχτιον δ ιοδ ε σ. σπαχε χηαργ ε χαπαχιτανχε ιν Σχηοττκψ δ ιοδ ε λαργ ε ρ τηαν ιν πν ϕυνχτιον δ ιοδ ε βε χασυε οφ ναρροωε ρ δ ε πλε τιον λαψε ρ ωιδ τησ ρε συλτινγ φροµ ηε αϖιε ρ δ οπινγ σ. Copyright © by John Wiley & Sons 2003

V

FP

V(on) t voltage C(Schottky) Å 5 C(PN)

R

Ω

(Sch.) << ΩR

(pn)

Diodes - 19

Ohmic Contacts ¥ Electrons diffuse from A linto ptype Sibecasue electrons in A l have higher average energy. ¥ Electrons in p-type Siform an accum ulation layer of greatly enhanced conductivity. ¥ Contact potentialand rectifying junction com pletely m asked by enhanced conductivity.So-called ohm ic contact. ¥ In N + Sidepletion layer is very narrow and electric fields approach im pact ionization values.Sm all voltages m ove electrons across barrier easily becasue quantum m echanicaltunneling occurs. Copyright © by John Wiley & Sons 2003

Electron Energy E Al E

Si

Accumulation layer

i(t) Al

-

-

P-Si or N + -Si

Diffusing electrons

Diodes - 20

PN Vs Schottkys at Large BVBD ¥ M inority carrier drift region relationships qÊ[µnÊ+ʵp]ÊnaÊA ÊV d ¥ IF Å Wd ¥ M axim um practicalvalue of na =10 17 cm -3 and corresponding to µn + µp = 900 cm 2 /(V -sec) ¥ Desired breakdow n voltage requires W d ³ 10 -5 BV BD IF Vd = 1.4x10 6 A BV BD ¥ M ajority carrier drift region relationships qÊ[µnÊ+ʵp]ÊN dÊA ÊV d ¥ IF Å Wd Copyright © by John Wiley & Sons 2003

¥ Desired breakdow n voltage 1.3x10 17 requires N d = and BV BD W d ³ 10 -5 BV BD ¥ Large BV BD (1000 V ) requires N d = 10 14 cm -3 w here µn + µp = 1500 cm 2 /(V -sec) IF Vd 6 ¥ Å 3.1x10 A [BV BD ]2 ¥ Conclusion:M inority carrier devices have low er on-state losses at large BV BD .

Diodes - 21

PSPICE Built-in Diode Model •

• Components

Circuit diagram ¥

Cj - nonlinear space-charge capacitance

¥

Cd - diffusion capacitance. Caused by excess

i

+

diode

+

carriers. Based on quasi-static description of stored charge in drift region of diode.

v j

C

v

i

C

(v dc

j

) j

d

diode -

¥

Current source idc(vj) models the exponential I-V characteristic.

R s

-

¥ v

= diode

v

+

R

i j

s

diode

Copyright © by John Wiley & Sons 2003

Rs accounts for parasitic ohmic losses at high currents.

Diodes - 22

Stored Charge in Diode Drift Region - Actual Versus Quasi-static Approximation x

-

+

N

P

N

n(x,t)

• One dimensional diagram of a power diode.

+

n(x,t)

• Quasistatic view of decay of excess carrier distribution during diode turn-off. n(x,t) = n(x=0,t) f(x)

time

time time

• Redistribution of excess carriers via diffusion ignored. Equ;ivalent to carriers moving with inifinte velocity.

x

0

Wd

time

time time

x

Copyright © by John Wiley & Sons 2003

• Actual behavior of stored charge distribution during turn-off. Diodes - 23

Example of Faulty Simulation Using Built-in Pspice Diode Model L stray

50 nH

• Test circuit example - step-down converter.

I o

D f +

V

50 A

d

• PSPICE diode model parameters - (TT=100ns Cjo=100pF Rs=.004 Is=20fA)

-

100 V

Sw

Diode Voltage

0V

-100V

-200V

• Diode voltage transient

-300V

-400V

-500V 0s

100ns

200ns

300ns

400ns

500ns

time

Diode Current

100A

50A

0A

-50A

• Diode current transient.

-100A

0s

100ns

200ns

300ns

400ns

500ns

time

Copyright © by John Wiley & Sons 2003

Diodes - 24

Improved (lumped-charge) Diode Model N - region

• More accurately model distributed nature of excess carrier distribution by dividing it into several regions, each described by a quasi-static function. Termed the lumped-charge approach.

p(x) = n(x) P+ Q1 region δ

Θ

2

Q 4

Q3

N+ region x

d

1

i

• Circuit diagram of improved diode model. Circuit written in terms of physical equations of the lumped-charge model.

diode

+

D

v

Gd

CJ

j Vsense1 -

6

5

8

7 +

-

2 R s

+

+ Re

Ee 3

Em

-

+ Rm

Edm

-

-

Cdm

Rdm

+ Emo -

0

4

+

• Detailed equations of model given in subcircuit listing.

Vsense2 -

9

• Many other even better (but more complicated models available in technical literature..

Copyright © by John Wiley & Sons 2003

Diodes - 25

Details of Lumped-Charge Model Subcircuit Listing .Subckt DMODIFY 1 9 Params: Is1=1e-6, Ise=1e-40, Tau=100ns, +Tm=100ns,Rmo=Rs=.001, Vta=.0259, CAP=100p, Gde=.5, + Fbcoeff=.5, Phi=1, Irbk=1e20,Vrbk=1e20 *Node 1= anodeand Node 9 = cathode Dcj 1 2 Dcap ; Included for space charge capacitance and reverse *breakdown. .model Dcap D (Is=1e-25 Rs=0 TT=0 Cjo={CAP} M={Gde} +FC={Fbcoeff} Vj={Phi} +IBV={Irbk} BV=Vrbk}) Gd 1 2 Value={(v(5)-v(6))/Tm +Ise*(exp(v(1,2)/Vta)-1)} *Following components model forward and reverse recovery. Ee 5 0 VALUE = {Is1*Tau*(exp(V(1,2)/(2*Vta))-1)}; Ee=Qe Re 5 0 1e6 Em 6 0 VALUE = {(V(5)/Tm-i(Vsense1))*Tm*Tau/(Tm+Tau)} *Em=Qm Rm 6 0 1e6 Edm 7 0 VALUE = {v(6)};Edm=Qm Vsense1 7 8 dc 0 ; i(vsense1)=dQm/dt Cdm 8 0 1 Rdm 8 0 1e9 Rs 2 3 4e-3 Emo 3 4 VALUE={2*Vta*Rmo*Tm*i(Vsense2) +/(v(6)*Rmo+Vta*Tm)}; Vm Vsense2 4 9 dc 0 .ends Copyright © by John Wiley & Sons 2003

• Symbolize subcircuit listing into SCHEMATICS using SYMBOL WIZARD • Pass numerical values of parameters Tau, Tm, Rmo,Rs, etc. by entering values in PART ATTRIBUTE window (called up within SCHEMATICS). • See reference shown below for more details and parameter extraction procedures. • Peter O. Lauritzen and Cliff L. Ma, "A Simple Diode Model with Forward and Reverse Recovery", IEEE Trans. on Power Electronics, Vol. 8, No. 4, pp. 342-346, (Oct., 1993) Diodes - 26

Simulation Results Using Lumped-Charge Diode Model Diode voltage and current waveforms

Simulation Circuit L

10V Diode

stray

50 nH

Voltage

0V

0V

Io 50 A

.

+

V d

-

100 V

-10V 410ns

D

f

420ns

415ns

-100V

Sw

-200V

0s

100ns

200ns

300ns

400ns

500ns

time

Diode

Current

• Note soft reverse recovery and forward voltage overshoot. Qualitatively matches experimental measurements.

50A

0A

-50A 0s

100ns

200ns

300ns

400ns

500ns

time

Copyright © by John Wiley & Sons 2003

Diodes - 27