Digital Electronics Lab Manual For Cse & It (1).docx

LABORATORY MANUAL FOR THE COURSE DIGITAL ELECTRONICS LABORATORY (CODE: IT - 218)

Prepared By: Ms.G.GAYATRI Asst. Professor Dept. of ECE

Dr.K.Murali Krishna Prof.&HOD Dept. of ECE

DEPARTMENT OF

ELECTRONICS & COMMUNICATION ENGINEERING

ANIL NEERUKONDA INSTITUTE OF TECHNOLOGY & SCIENCES (Affiliated to Andhra University)

Sangivalasa-531162, Bheemunipatnam Mandal, Visakhapatnam Phone:089335084,226395.

ANIL NEERUKONDA INSTITUTE OF TECHNOLOGY & SCIENCES (Affiliated to AU, Approved by AICTE &Accredited by NBA) Sangivalasa-531162, Bheemunipatnam Mandal, Visakhapatnam Dt. Phone: 08933- 225084,226395

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING IT 218

Dt: :12-2-2016

The following are the list of laboratory experiments for DIGITAL ELECTRONICS Laboratory in 2-1 (CSE & I.T Dept Autonomous) for the academic year (2016-17). *NOTE: FOUR Experiments from each cycle should be done compulsorily.

CYCLE-I: 1. Study of passive, active components & Integrated Circuits. 2. To study the regulation characteristics of given Integrated Circuits. 3. To verify the adder operation & subtractor operation using Operational amplifiers. 4. To verify the truth tables of given Logic Gates.

CYCLE-II: 1. Verification of truth tables of Logic gates using IC’s. 2. Design a combinational circuit for Code Converters using IC’s. 3. Design a combinational circuit for Adders & Subtractors (HA & FA) using IC’s. 4. Design a sequential circuit for Flip-flop and verify its characteristics using IC’s.. 5. Design a bidirectional Universal Shift Register Using IC74LS194. 6. Design of Counters using IC74LS73. CYCLE-III: (Simulation using VHDL) 1. Write a program for verification of Basic Gates. 2. Write a program for Adder & Subtractor. 3. Write a program for flip flops. 4. Write a program for MUX & DEMUX. 5. Write a Program for Shift Registers. Dr. K.Murali Krishna Prof & HOD, Dept of ECE.

INTRODUCTION TO VHDL VHDL is an acronym for VHSIC Hardware Description Language (VHSIC is an acronym for Very High Speed Integrated Circuit).It is a Hardware Description Language that can be used to model a digital system at many levels of abstraction, ranging from algorithmic level to the gate level. The complexity of the digital system being modeled could vary from that of simple gate to a complex digital electronic system or anything in between. The digital system can also be described hierarchically. Timing can also be explicitly modeled in the same description. The VHDL language can be regarded as an integrated amalgamation of following languages. Sequential language + Concurrent language + Net-list language + Timing specifications + Waveform generation language =>VHDL. The language not only defines the syntax but also defines very clear simulation semantics for each language construct. Therefore models written in this language can be verified using a VHDL simulation.

CAPABILITIES: The following are the major capabilities that the language provides along with the features that differentiate it from other hardware description languages. 

The language can be used as an exchange medium between chip vendors and CAD tool users. Different chip vendors can provide VHDL descriptions of their components to system designers. CAD tool users can use it to capture the behavior of the design at a high level of abstraction of functional simulation.



The language can also be used as a communication medium between different CAD and CAE tools. For example, a schematic capture PROGRAM may be used to generate a VHDL description for the design which can be used as an input to a simulation PROGRAM.



The language supports hierarchy, that is, a digital system can be modeled as a set of interconnected subcomponents.



The language supports flexible design methodologies: top-down, bottom-up or mixed.



It supports both synchronous and asynchronous timing models.



Various digital modeling techniques, such as finite state machine descriptions, algorithmic descriptions and Boolean equations can be modeled using the language.



The language supports three basic different description styles: structural, dataflow and behavioral. A design may also be expressed in any combination of these three descriptive styles.



The language is not technology-specific, but is capable of supporting technology specific features. It can also support various hardware technologies.

BASIC TERMINOLOGY: A hardware abstraction of a digital system is called an entity. An entity X when used in another entity Y becomes a component for the entity Y. therefore the component is also an entity, depending on the level at which you are trying to model. To describe an entity, VHDL provides five different types of primary constructs called design units. They are:  Entity declaration.  Architecture body.  Configuration declaration.  Package declaration.  Package body. 

ENTITY DECLARATION: The entity declaration specifies the name of the entity being modeled and lists the set of interface

ports. Ports are signals through which the entity communicates with the other models in its external environment. 

ARCHITECTURE BODY: The internal details of an entity are specified by an architecture body using any of the following

modeling styles:  As a set of interconnected components (to represent structure).  As a set of concurrent assignment statements (to represent dataflow).  As a set of sequential assignment statements (to represent behavior). 

CONFIGURATION DECLARATION: This is used to select one of the many possibly architecture bodies that an entity may have, and to

bind components , used to represent structure in that architecture body, to entities represented by an entity-architecture pair or by a configuration which reside in a design library. 

PACKAGE DECLARATION: This is used to store a set of common declarations, such as components, types, procedures and

functions. These declarations can then be imported into other design units using a ‘use’ clause.



PACKAGE BODY: This is used to store the definitions of functions and procedures that were declared in the

corresponding package declaration, and also complete constant declarations for any deferred constants that appear in the package in the package declaration.

STRUCTURAL MODELING: In the structural style of modeling, an entity is described as a set of interconnected components. Example: Half adder. The entity declaration for half adder specifies the interface ports for this architecture body. The architecture body is composed of two parts: the declarative part (before the keyword begin) and the statement part(after the keyword begin). Two component declarations are present in the declarative part of the architecture body. These declarations specify the interface of components that are used in the architecture body. The declared components are instantiated in the statement part of the architecture body using component labels for these component instantiation statements. The signals in the port map of a component instantiated and the port signals in the component declaration are associated by position (called positional association). However the structural representation for the Half adder does not say anything about its functionality. Separate entity models would be described for the components XOR2 and AND2, each having its own entity declaration and architecture body. A component instantiated statement is a concurrent statement. Therefore, the order of these statements is not important. The structural style of modeling describes only an interconnection of components, without implying any behavior of the components themselves nor the entity that they collectively represent.

DATAFLOW MODELING: In this modeling style, the flow of data through the entity is expressed primarily using concurrent signal assignment statements. The structure entity of the entity is not explicitly specified in this modeling style, but it can be implicitly deduced. In a signal assignment statement, the symbol <= implies an assignment of a value to a signal. The value of the expression on the right-hand-side of the statement is computed and is assigned to the signal on the left-hand-side, called the target signal. A concurrent signal assignment statement is executed only when any signal used in the expression on the right-hand-side has an event on it, that is, the value for the signal changes.

BEHAVIORAL MODELING: The behavioral modeling specifies the behavior of an entity as a set of statements that are executed sequentially in the specified order. This set of sequential statements, which are specified inside a process statement, do not explicitly specify the structure of the entity but merely its functionality. A process statement is a concurrent statement that can appear within an architecture body. A process statement also has a declarative part (before the keyword begin) and a statement part (between the keywords begin and end process). The statements appearing within the statement part are sequential statements and are executed sequentially. The list of signals specified within the parenthesis after the keyword process constitutes a sensitivity list, and the process statement is invoked whenever there is an event on any signal in this list. A variable is assigned using the assignment operator: = compound symbol; contrast this with a signal that is assigned a value using the assignment operator <= compound symbol. Signal assignment statements appearing within a process are called sequential signal assignment statements. Sequential signal statements, including variable assignment statements, are executed sequentially independent of whether an event occurs on any signals in its right-hand-side expression; contrast this with the execution of concurrent signal assignment statements in the dataflow modeling style.

CYCLE-I: EXPERIMENT NO: 1 Study of Passive, Active components & Integrated circuits Objective: To get familiar with basic electronic components such as Resistor, capacitors, Inductor, diodes, transistors, integrated circuits (IC) and to understand their functions. Introduction: Basic Components: Basic components like capacitors, resistors, inductors, diodes, and transistors can be divided into 2 categories: (i) (ii)

Passive components like resistors, capacitors and inductors. Active components like diodes , transistors, batteries, generators, operational amplifiers, vacuum tubes etc The difference between the above two categories is that active components can generate energy whereas passive components can not generate energy, they which consume rather than produce energy. In other words active components can increase power of a signal whereas passive components often cause the power to be lost.

RESISTORS: A resistor is a passive two-terminal electrical component that implements electrical resistance as a circuit element. The current through a resistor is in direct proportion to the voltage across the resistor's terminals. This relationship is represented by Ohm's law. A device used in electrical circuits to maintain a constant relation between current flow and voltage. Resistors are used to step up or lower the voltage at different points in a circuit and to transform a current signal into a voltage signal or vice versa, among other uses. The electrical behavior of a resistor obeys Ohm's law for a constant resistance; however, some resistors are sensitive to heat, light, or other variables. Resistors are one of the most used components in a circuit. Most are color coded, but some have their value in Ohms and their tolerance printed on them. A multimeter that can check resistance can also be helpful providing the resistor is already removed from the board (measuring it while still soldered in can give inaccurate results, due to connections with the rest of the circuit). They are typically marked with an “R” on a circuit board.

Colour Code for Resistors Band colour Band colour & its & its value tolerance Black = 0 Brown = 1 Red = 2 Orange = 3 Yellow = 4 Green = 5 Blue = 6 Violet = 7 Grey = 8 White = 9

Gold = ±5% Silver = ±10 % No colour means 20 %

The first two bands near an end indicate first 2 digits, digit corresponding to 3rd band is the power of 10 to be multiplied and fourth band indicates tolerance as mentioned in the table.

Where brown = 1, black = 0, red = 2 and silver = 10 % tolerance. Hence its value is 10 x 10 2 Ω = 1000Ω (or) 1k Ω. CAPACITORS: A capacitor (originally known as a condenser) is a passive two-terminal electrical component used to store energy electrostatically in an electric field. By contrast, batteries store energy via chemical reactions. The forms of practical capacitors vary widely, but all contain at least two electrical conductors separated by a dielectric (insulator); for example, one common construction consists of metal foils separated by a thin layer of insulating film. Capacitors are widely used as parts of electrical circuits in many common electrical devices. Capacitors are also very commonly used. A lot have their values printed on them, some are marked with 3-digit codes, and a few are color coded. The same resources listed above for resistors can also help you identify capacitor values. They are typically marked with a “C” on a circuit board. Colour and Number code of capacitors: Different marking schemes are used for electrolytic and nonelectrolytic capacitors. Temperature coefficient is of minor importance in an electrolytic filter capacitor, but it is very important in ceramic trimmers for attenuator use. One never finds temperature coefficient on an electrolytic label, but it is always present on ceramic trimmers.

(i) Electrolytic Capacitors: There are two designs of electrolytic capacitors: (i) Axial where the leads are attached to each end (220µF in picture) and (ii) Radial where both leads are at the same end (10µF in picture). (ii) Non-polarized capacitors (< 1µF): Small value capacitors have their values printed but without a multiplier. For example 0.1 means 0.1µF = 100nF. Sometimes the unit is placed in between 2 digits indicating a decimal point. For example: 4n7 means 4.7nF. Capacitor Number Code: A number code is often used on small capacitors where printing is difficult: the 1st number is the 1st digit, the 2nd number is the 2nd digit, the 3rd number is the power of ten to be multiplied, to give the capacitance in pF. Any letters just indicate tolerance and voltage rating. For example:102K means 10 X 10 2 pF = 10 X 10 2 X 10 -12 F =10 -9 F =1nF

INDUCTORS: An inductor, also called a coil or reactor, is a passive two-terminal electrical component which resists changes in electric current passing through it. It consists of a conductor such as a wire, usually wound into a coil. When a current flows through it, energy is stored in a magnetic field in the coil. When the current flowing through an inductor changes, the time-varying magnetic field induces a voltage in the conductor, according to 4 Faraday’s law of electromagnetic induction, which by Lenz's law opposes the change in current that created it. Inductors, also called coils, can be a bit harder to figure out their values. If they are color coded, the resources listed for resistors can help; otherwise a good meter that can measure inductance will be needed. They are typically marked with an “L” on a circuit board.

DIODES: In electronics, a diode is a two-terminal electronic component with asymmetric conductance; it has low (ideally zero) resistance to current flow in one direction, and high (ideally infinite) resistance in the other. Semiconductors, such as Diodes (typically marked with a “D” on a circuit board). A diode is a single junction device made of p and n type materials.. Its main function is to rectify an ac signal although other special purpose diodes like zener and led’s used for other purposes. A normal diode comes in a black casing whereas a zener diode has a transparent casing. Their pictures and symbols are given in fig.

Other diodes may be made by a p type and n type materials or between a semiconductor and a metal. If the junction is made between a metal and semiconductor then it is called a Schottky diode whose application is in rectifying and non-rectifying contacts and Schottky devices. If the PN junction is made between very heavily doped materials then it forms a Zener diode. These are used for voltage regulation in power supplies. and have breakdown voltages which are very low. The normal diode has a breakdown voltage of greater than 100 V. Table gives some of the most commonly used diodes with their specifications. Table Device Material IF (mA) VF (V) VBR (V) Number used. OA91 Ge 50 2.1 115 IN 4007

Si

1000

1.6

1000

TRANSISTORS: A transistor is a semiconductor device used to amplify and switch electronic signals and electrical power. It is composed of semiconductor material with at least three terminals for connection to an external circuit. A voltage or current applied to one pair of the transistor's terminals changes the current through another pair of terminals. Because the controlled (output) power can be higher than the controlling (input) power, a transistor can amplify a signal. Today, some transistors are packaged individually, but many more are found embedded in integrated circuits. Transistors (typically marked with a “Q” on a circuit board). It’s a two junction and 3 terminal device made of three layers of n and p type materials. The three regions are emitter, base and collector. They are of 2 types (i) pnp (ii) npn. Their most important specifications are Ic, Vce, hfe and Power rating.

Code

Structure

Case style

IC max.

VCE max.

hFE Ptot min. max.

Category (typical use)

Possible substitutes

BC107

NPN

TO18

100mA

45V

110

300mW

Audio, low power

BC182 BC547

BC108

NPN

TO18

100mA

20V

110

300mW

General purpose, low BC108C BC183 BC548 power

BC108C

NPN

TO18

100mA

20V

420

600mW

General purpose, low power

BC109

NPN

TO18

200mA

20V

200

300mW

Audio (low noise), low BC184 BC549 power

Fig gives some of the transistors with the symbols. For NPN and PNP.

PNP –PN2907

NPN-2N4401

NPNBC 107

INTEGRATED CIRCUITS (IC): An integrated circuit or monolithic integrated circuit (also referred to as an IC, a chip, or a microchip) is a set of electronic circuits on one small plate ("chip") of semiconductor material, normally silicon. This can be made much smaller than a discrete circuit made from independent components. Integrated circuits are used in virtually all electronic equipment today and have revolutionized the world of electronics. Computers, mobile phones, and other digital home appliances are now inextricable parts of the structure of modern societies, made possible by the low cost of producing integrated circuits. Integrated Circuits (typically marked with a “U” or “IC” on a circuit board) They can give various functions like: (i) the function of a full microprocessor circuit (e.g. 8085), (ii) a memory chip, (iii) a voltage regulator (LM 7805). They come in a black bench like casing with a notch on one side and with electrical legs for connections, which are called pins. The size is usually around 1 cm2 X 1 cm2. Refer to the pictures. Its name is always written on top which contains a few letters with numerals, according to its type, make and company. For example an IC with name LS 7400 would mean LS series with And gates, LM741C - mA741C is an operational amplifier (Op-Amp). Datasheets can be referred to, to know the details of pin configurations and make etc. The pins are usually read starting from left of notch and going anticlockwise as shown in picture for 555 timer IC.

Pin Digrams of ICs: 1. IC 741

APPLICATIONS OF IC741: o o o o o o o

IC 741 is used in Amplifier. It is used in Arithmetic circuit. IC 741 is used in log and antilog amplifier. It is used in voltage comparator. It is used in waveform generator. It is used in Multiplier. It is used in regulated power supply (RPS).

2. 555 Timer

APPLICATION OF 555 Timer is to build infrared (IR) transmitter and receiver

3. IC 78XX

The 78xx family is commonly used in electronic circuits requiring a regulated power supply due to their ease-of-use and low cost. For ICs within the family, the xx is replaced with two digits, indicating the outputvoltage (for example, the 7805 has a 5-volt output, while the 7812 produces 12 volts).

OBSERVATIONS: 1. 2. 3. 4. 5.

Resistors: Calculate some resistors values by using color codes. Capacitor: Calculate some capacitor values by identifying the readings on them Diode: indentify types of diodes & polarities of it. Transistor: identify the types of transistor and parities of it. Integrated circuits: Indentify the ICs and its Pin notations.

PRECAUTIONS; 1. Handle the components with care & read the color code carefully.

RESULT:

EXPERIMENT: 2 IC VOLTAGE REGULATOR AIM: To verify the voltage regulation of a 3-terminal fixed IC voltage regulator. APPARATUS: 1) Ammeter (0-100) mA 2) Voltmeter (0-10) V 3) Capacitor 1µF, 0.1 µF 4) Voltage regulator 7808 5) Decade resistance box (DRB) 6) TRPS 7) Bread board 8) Connecting wires. THEORY: A voltage regulator is an electronic device that provides a stable dc voltage independent of load current, temperature and a.c voltage variations. Figure shows a regulated power supply using discrete components. The circuit consists of following parts. 1. Reference voltage circuit 2. Error amplifier 3. Series pass transistor 4. Feedback network. It can be seen from the figure that the power transistor Q1 is in series with the un-regulated dc voltage Vin and the regulated output voltage Vo so it must absorb the difference between these two voltages whenever any fluctuation in output voltage Vo occurs The transistor Q1 is also connected as an emitter follower and therefore provides sufficient current gain to drive the load. The output voltage is sampled by R1-R2 divider and feedback to the negative input terminal of op-amp error amplifier sample the output voltage. This sampled voltage is compared with the reference voltage Vref. The output voltage Vo’ of the error amplifier drives the transistor Q1. Diagram: Series pass transistor BC 107

Ro +VEE

7

R1

2

-

-VEE

+

A

6

-

4

+

IMZ 5.1

power supply

3

RL

LM 307(error amp) R2

78XX series are three terminal positive fixed voltage regulators. There are seven voltage options available such as 5, 6, 8,12,15,18 and 24V. In 78XX series the last two numbers indicate the output voltage. For example 7808 indicates 8V regulator. 79XX series are also 3-terminal IC regulator with fixed output negative voltage regulator. In the standard representation of monolithic voltage regulator a capacitor ‘C’ is usually connected between input terminal and ground to cancel the inductive effect due to long distribution leads.

CIRCUIT DIAGRAM:

3-Terminal Fixed Voltage Regulator

1 7808

3

(0-100mA)

+ A -

Regulator

MC

+ 12V

C1

-

2

C2

+ DRB

V (0-10V) MC

-

C1 = 1µF , C2 = 0.1 µF Procedure: 1. Connections are made as per the circuit diagram. 2. By adjusting the Voltage across RPS to 12V, the load terminals open circuited, the voltmeter reading is noted. This gives the no load voltage. 3. The load is varied from 10KΩ to 50Ω with the help of decade resistance box the corresponding voltmeter and ammeter reading are noted. 4. A graph is drawn between % voltage regulation on y-axis and load resistance on x-axis. 𝑉𝑁𝐿−𝑉𝑙 % voltage Regulation = 𝑉𝐿 × 100

Tabular form : VNL = RL (Ω) 10K Ω to 50Ω

I (mA)

V (Volts)

% Regulation

Model Graph:

% Regulation

RL in Ohms

PRECAUTIONS: 1. Loose and wrong connections are to be avoided. 2. The output waveforms should be obtained without and distortion. 3. Parallax error should be avoided

RESULT:

EXPERIMENT NO: 3

Summer & Subtracter operations by using 741 Op-Amp AIM : To verify the adder & subtracter operations by using 741 Op-Amp . APPARATUS: 1. Op-Amp LM 741 2. Resistors – 1KΩ (4) 3. TRPS(0-30V) 4. Multimeter (0-20V) 5. Bread Board 6. Connecting Wires THEORY: An Operational Amplifier is a direct-coupled high gain amplifier usually consisting of one or more differential amplifiers and usually followed by a level translator and an output stage. The output stage is generally a push-pull or push – pull complementary symmetry pair. An Operational Amplifier is available as a single integrated circuit package. The schematic symbol for an OP – AMP

V1

-

A V2

+

V0

where V2 = voltage at non – inverting input (volts). V1= voltage at inverting input (volts). V0 = Output Voltage (volts) All these voltages are measured with respect to ground A = large signal voltage gain. THE IDEAL OP- AMP: An ideal op amp would exhibit the following electrical characteristics. 1. Infinite voltage gain A. 2. Infinite input resistance Ri so that almost any signal source can drive it and there is no loading of the preceding stage. 3. Zero output resistance R0 so that output can drive an infinite number of other devices. 4. Zero output voltage when input voltage is zero. 5. Infinite bandwidth so that any frequency signal from 0 to ∞ Hz can be amplified without attenuation. 6. Infinite common mode rejection ratio so that output common – mode noise voltage is zero. 7. Infinite slew rate so that output voltage changes occur 8. Simultaneously with input voltage changes.

APPLICATIONS OF OP -AMP: 1. Summing Amplifier: Op amp may be used to design a circuit whose output is the sum of several input signals. Such a circuit is called a summing amplifier or a summer. If V1, V2 are two input signals given to the inverting terminal, then Vo = - RF (V1 + V2) R 2. Subtracting Amplifier: The function of a subtractor is to provide an output, which is equal to the difference of two input signals (or) proportional to the difference of two input signals. If V1 and V2 are the input voltages at inverting and non – inverting terminals, then Vo = -RF (V1 - V2) R

CIRCUIT DIAGRAM: Summer

R1 Vcc = +15 V 4

R2 2

7

-

LM 741

R3 3

+

6 4

-Vee = -15 V V1

V2

R1=R2=R3=1KΩ

Vo

Subtractor

R1 Vcc = +15 V 4

R2 2

-

LM 741

R3 3

+

R4 V1

7 6 4

-VEE = -15 V

Vo

V2

R1=R2=R3=R4=1KΩ PROCEDURE: I. Summing Amplifier: 1. Connections are made as per the circuit diagram. 2. Input voltages V1 and V2 are given and the corresponding output voltage Vo is measured from CRO. 3. Output varies as Vo = - (V1 + V2), since RF = R. II. Subtracting Amplifier: 1. Connections are made as per the circuit diagram. 2. Input voltage V1 and V2 are given to the inverting and non – inverting terminals respectively and corresponding output voltage is measured from CRO. 3. Output varies as Vo = V2 – V1. PRECAUTIONS: 1. Loose and wrong connections are to be avoided. 2. Waveforms should be obtained without any distortion. RESULT:

EXPERIMENT NO: 4 LOGIC GATES AIM: To verify the truth table for various logic gates using resistors, diodes and transistors. APPARATUS:

1. 2. 3. 4. 5. 6. 7.

Diodes IN4007-2NO.S Transistor BC 107-1 Resistor 1kΩ-3no.s Digital multimeter (0-5V) Bread board Connecting wires TRPS.

THEORY: Circuits used to process digital signals are called logic gates. Gate is a digital circuit with one or more inputs but only one output. The basic gates are AND, OR, NOT, NAND, NOR. By connecting these gates in different ways we can build circuits that can perform arithmetic and other functions. The logic gates NAND,NOR are universal gates.

CIRCUIT DIAGRAM: 1. AND GATE: TRUTH TABLE:

A

B

O/P, Y=A.B

0

0

0

0

1

0

1

0

0

1

1

1

2. OR GATE

TRUTH TABLE:

3. NOT GATE:

A

B

O/P, Y=A+B

0

0

0

0

1

1

1

0

1

1

1

1

A

B

O/P, Y=(A.B)’

0

0

1

0

1

1

1

0

1

1

1

0

TRUTH TABLE: +5 V

A

1 KW

3

1 KW

+

BC 107

1

O/P, Y=(A)’ 0

0

1

2 1

5V

+ -

V0

-

1

2

NOT

4. NAND GATE:

TRUTH TABLE

5. NOR GATE:

TRUTH TABLE

A

B

O/P, Y=(A+B)’

0

0

1

0

1

0

1

0

0

1

1

0

PROCEDURE: 1. Connections are made as per the circuit diagram.

2. Output is taken across the load resistance. 3. Outputs are tabulated and truth table is verified.

PRECAUTIONS:

1. Loose and wrong connections should be avoided. 2. Supply should be switched on only after giving all the input connections. 3. power should be switched off while connecting

RESULT:

CYCLE-III: (Simulation using VHDL) 1. Functionality Verification of Logic Gates. AIM : To develop a VHDL Code for Logic Gates-AND, OR, NOT, NAND, NOR, XOR, XNOR and to verify its functionality. APPARATUS: Model Sim 5.7 .VHDL CODE: library ieee; use ieee.std_logic_1164.all; entity logicgates is port(a,b: in std_logic;c,d,e,f,g,h,i: out std_logic); end logicgates; architecture dataflow of logicgates is begin c<= a and b; d<= a or b; e<= not b; f<= a xor b; g<= a nand b; h<= not(a xor b); i<= a nor b; end dataflow;

TRUTH TABLE:INPUTS

OUTPUTS

a

b

AND c

OR d

NOT e

XOR f

NAND g

XNOR h

NOR i

0

0

0

0

1

0

1

1

1

0

1

0

1

0

1

1

0

0

1

0

0

1

1

1

1

0

0

1

1

1

1

0

0

0

1

0

RTL SCHEMATIC:

BASIC LOGIC GATES

WAVEFORMS:

RESULT: - Hence all the logic gates are simulated in VHDL using dataflow modeling and their functionality is verified. VIVA QUESTIONS:

1. What is VHDL? 2. What is the need for VHDL? 3. What is meant by simulation? 4. What is meant by synthesis? 5. Who initialized the VHDL and in which year? ANSWERS:

1. It is acronym for Very high-speed digital integrated circuit Hardware Descriptive Language. 2. VHDL is needed to synthesize circuits with millions of gates. 3. It is a software program that tests the functionality and timing of a circuit to be designed. 4. A translation from a higher level of abstraction to a lower level is synthesis. 5. United States Department of Defense (DoD) in the year 1980.

2. Adder & Subtractor. (a) Half Adder AIM : (a) To write a Program in VHDL for simulating the half adder and to verify its functionality. APPARATUS: Model Sim 5.7 VHDL CODE: library ieee; use ieee.std_logic_1164.all; entity halfadder is port(a,b: in std_logic; s,c: out std_logic); end halfadder; architecture dataflow of halfadder is begin s<= a xor b; c<= a and b; end dataflow;

TRUTH TABLE:INPUTS

OUTPUTS

0

Sum s 0

Carry c 0

0

1

1

0

1

0

1

0

1

1

0

1

a

b

0

RTL SCHEMATIC:

HALF ADDER

WAVEFORMS:

RESULT:- Hence the half adder is simulated in VHDL using data flow modeling and its functionality is verified .

(b) Full Adder AIM: - To write a PROGRAM in VHDL for simulating the full adder and to verify its functionality. APPARATUS: Model Sim 5.7 VHDL CODE: library ieee; use ieee.std_logic_1164.all; entity fulladder is port(a,b,c: in std_logic;s,cy: out std_logic); end fulladder; architecture dataflow of fulladder is begin s<= (a xor b)xor c; cy<= (a and b) or (b and c) or (c and a); end dataflow;

TRUTH TABLE:INPUTS

OUTPUTS

a

b

c

s

cy

0

0

0

0

0

0

0

1

1

0

0

1

0

1

0

0

1

1

0

1

1

0

0

1

0

1

0

1

0

1

1

1

0

0

1

1

1

1

1

1

RTL SCHEMATIC:

FULL ADDER

WAVEFORMS:

RESULT: - Hence the full adder is simulated in VHDL and its functionality is verified. VIVA QUESTIONS: 1. What is the assignment operator for i) signal ii) variable? 2. What is the difference between signal and variable? 3.

Is process used for combinational or sequential logic?

4. What is the difference between function and procedure? 5. Define i) entity ii) architecture. ANSWERS: 1. ‘<=’ and ‘:=’. 2. Nonstatic values can be passed in VHDL by two ways: signals and variables. A signal can be declared in package, entity or architecture, while a variable can be declared within a piece of sequential code. The value of former can be global and the later can be local. 3. Process can imply combinational or sequential logic, depending upon how it is used. 4. Function can return only one value, whereas procedure can return any no. of values. 5. The entity declaration describes the input and output of the design. It describes the external interface to the design. Architecture describes the internal implementation of the design. The architecture body describes the internal working of the entity and contains any combination of structural, dataflow, or behavioral descriptions used to describe the internal working of the entity.

3. Sequential circuits-Flip Flops (a) SR-FF AIM: - (a) To write a code in VHDL for simulating the SR flip-flop and to verify its functionality. APPARATUS: Model Sim 5.7 VHDL CODE: library ieee; use ieee.std_logic_1164.all; entity SR is port(S,R,clk: in std_logic;Q:inout std_logic:='0';Qb:inout std_logic:='1'); end SR; architecture ff of SR is begin process(S,R,clk) variable t,tb: std_logic; begin t:=Q; tb:=Qb; if (clk='0'and clk'event) then if(S='0'and R='0') then t:=t;tb:=tb; elsif(S='0'and R='1') then t:='0';tb:='1'; elsif(S='1'and R='0') then t:='1';tb:='0'; elsif(S='1'and R='1') then t:='U';tb:='U'; end if; Q<=t; Qb<=tb; end if; end process; end ff;

TRUTH TABLE:INPUTS

OUTPUTS

S

R

Q

Qb

0

0

Q

Qb

0

1

0

1

1

0

1

0

1

1

X

X

RTL SCHEMATIC:

S R CLK

SR FLIP FLOP

Q Qb

WAVEFORMS: CLK

RESULT:- Hence the SR flip-flop is simulated in VHDL and its functionality is verified.

(b) D-FF AIM:- (b) To write a code in VHDL for simulating the D flip-flop and to verify its functionality. APPARATUS: Model Sim 5.7 VHDL CODE:library ieee; use ieee.std_logic_1164.all; entity d_ff is port(d,clk:in std_logic; Q:inout std_logic:='0';Qb:inout std_logic:='1’); end d_ff; architecture behaviour of d_ff is begin process(d,clk) begin if (clk='0' and clk'event)then q<=d; qb<=not(d); end if; end process; end behaviour;

TRUTH TABLE:INPUTS

OUTPUTS

D

Q

Qb

0

0

1

1

1

0

RTL SCHEMATIC:

D_FF

WAVEFORMS:

RESULT:- Hence the D flip-flop is simulated in VHDL and its functionality is verified. VIVA QUESTIONS: 1. What are the various types of operators supported by VHDL? 2. What are the different concurrent assignment statements? 3. What are the different sequential assignment statements? 4. What is the purpose of PROCESS statement? 5. Give the general form of CASE statement.

ANSWERS: 1.

Boolean(AND,

OR,NAND,

NOR,XOR,

XNOR),

arithmetic(*,/.MOD,REM,-,&),

and

relational(=,/<,<=,>,>=) 2. Simple signal assignment, selected signal assignment, conditional signal assignment, and generate statements. 3. IF statement, CASE statement, and two types of Loop statement(FOR-LOOP and WHILE-LOOP) 4. To separate the sequential statements from concurrent statements, PROCESS statement is used. The PROCESS statement appears inside an architecture body, and it encloses other statements within it. The IF, CASE, and LOOP statements can appear only inside a process.

5. CASE expression IS WHEN constant_value => statement; {statement;} WHEN constant_value => statement; {statement;} WHEN OTHERS => statement; {statement;} END CASE;

4. Combinational Circuits Multiplexer and Demltiplexer (a) Multiplexer (MUX) (i) AIM: - To write a code in VHDL for simulating the 2x1 multiplexer and to verify its functionality. APPARATUS: Model Sim 5.7 VHDL CODE:library ieee; use ieee.std_logic_1164.all; entity mux21 is port(a,b:in std_logic; s:in std_logic; y:out std_logic); end mux21; architecture beh of mux21 is begin process(a,b,s) begin case s is when '0'=>y<=a; when '1'=>y<=b; when others=>y<='U'; end case; end process; end beh;

TRUTH TABLE:SELECT INPUT

RTL SCHEMATIC:

OUTPUT

S

Y

0

a

1

b

MUX 2 x 1

WAVEFORMS:

RESULT:- Hence the 2x1 multiplexer is simulated in VHDL and its functionality is verified.

(ii) AIM:- To write a code in VHDL for simulating the 4x1 multiplexer and to observe the waveforms. APPARATUS: Model Sim 5.7 VHDL CODE:library ieee; use ieee.std_logic_1164.all; entity mux41 is port(a,b,c,d:in std_logic;s:in std_logic_vector(1 downto 0);y:out std_logic); end mux41; architecture beh of mux41 is begin

process(a,b,c,d,s) begin case s is when "00"=>y<=a; when "01"=>y<=b; when "10"=>y<=c; when "11"=>y<=d; when others=>y<='U'; end case; end process; end beh; TRUTH TABLE:SELECT DATA INPUTS S1 S0 0 0 0 1 1 0 1 1

OUTPUTS Y D0 D1 D2 D3

RTL SCHEMATIC:

WAVEFORMS:

MUX 4 x 1

RESULT:- Hence the 4x1 multiplexer is simulated in VHDL and its functionality is verified.

(iii) AIM:- To write a code in VHDL for simulating the 8x1 multiplexer and to verify its functionality. APPARATUS: Model Sim 5.7 VHDL CODE:library ieee; use ieee.std_logic_1164.all; entity mux81 is port(x:in std_logic_vector(0 to 7);s:in std_logic_vector(2 downto 0);y:out std_logic); end mux81; architecture structure of mux81 is component mux41 port(a,b,c,d:in std_logic;s: in std_logic_vector(1 downto 0);y: out std_logic); end component; component mux21 port(a,b,s: in std_logic;y: out std_logic); end component; signal p1,p2: std_logic; begin X1: mux41 port map(x(0),x(1),x(2),x(3),s(1 downto 0),p1); X2: mux41 port map(x(4),x(5),x(6),x(7),s(1 downto 0),p2); X3: mux21 port map(p1,p2,s(2),y); end structure; RTL SCHEMATIC:

WAVEFORMS:

RESULT:- Hence

the 8x1 multiplexer is simulated in VHDL using structural modeling and its

functionality is verified. 4(b) 1x8 Demultiplexer AIM:- To write a code in VHDL for simulating the 8x1 demultiplexer and to verify its functionality. APPARATUS: Model Sim 5.7 VHDL CODE:Library ieee; use ieee.std_logic_1164.all; entity dmux81 is port(a: in std_logic;s: in std_logic_vector(2 downto 0);y: out std_logic_vector(0 to 7)); end dmux81; architecture dmux of dmux81 is begin process(a,s)

begin y<="00000000"; case s is when "000"=>y(0)<=a; when "001"=>y(1)<=a; when "010"=>y(2)<=a; when "011"=>y(3)<=a; when "100"=>y(4)<=a; when "101"=>y(5)<=a; when "110"=>y(6)<=a; when "111"=>y(7)<=a; when others=>y<="UUUUUUUU"; end case; end process; end dmux;

TRUTH TABLE:DATA INPUT

OUTPUTS

SELECT INPUTS

S2

S1

S0

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

a

0

0

0

a

0

0

0

0

0

0

0

a

0

0

1

0

a

0

0

0

0

0

0

a

0

1

0

0

0

a

0

0

0

0

0

a

0

1

1

0

0

0

a

0

0

0

0

a

1

0

0

0

0

0

0

a

0

0

0

a

1

0

1

0

0

0

0

0

a

0

0

a

1

1

0

0

0

0

0

0

0

a

0

a

1

1

1

0

0

0

0

0

0

0

a

RTL SCHEMATIC:

DEMUX 8 x 1

WAVEFORMS:

RESULT:- Hence the 1x8 demultiplexer is simulated in VHDL using behavioral modeling and its functionality is verified. VIVA QUESTIONS: 1. What are the basic sections of a VHDL code? 2. Define i) STD_LOGIC_1164 ii) STD_LOGIC_ARITH iii) STD_LOGIC_UNSIGNED 3. What are the rules to be followed while specifying data object names? 4. What are the values the data type STD_LOGIC can assume? 5. How the value of individual SIGNAL and multibit SIGNAL are specified?

ANSWERS: 1. Library, entity and architecture. 2. i) defines the standard for describing the interconnection ii) defines UNSIGNED and SIGNED types, conversion iii) defines functions to allow the use of STD_LOGIC_VECTOR types as if they were UNSIGNED types 3. Any alphanumeric character may be used in the name, as well as the ‘_’underscore character. A name cannot be a VHDL keyword, it must begin with a letter, it cannot end with an ‘_’ underscore, and it cannot have two successive underscores. 4. ‘U’ --Unintaialized ‘X’ -- Forcing unknown ‘0‘ -- Forcing 0 ‘1‘-- Forcing 1 ‘Z‘ -- High impedance ‘W‘ -- Weak unknown ‘ L‘ -- Weak 0 ‘H‘ --Weak 1 ‘- ‘ --Don’t care 5. The value of an individual SIGNAL is specified using apostrophes, as in ‘0’ or ‘1’. The value of a multibit SIGNAL is given with double quotes.

5. SHIFT REGISTERS 5(a) SISO & SIPO Shift Register AIM:- To write a code in VHDL for simulating the Serial In Serial Out(SISO) and Serial In Parallel Out(SIPO) shift registers using single entity and multiple architectures and to verify its functionality. APPARATUS: Model Sim 5.7 VHDL CODE:- COMPONENT : library ieee; use ieee.std_logic_1164.all; entity D is port(D,clk: in std_logic;Q:inout std_logic:='0'); end D; architecture behaviour of D is begin process(D,clk) begin if (clk='0' and clk'event) then Q<=D; end if; end process; end behaviour; SISO : library ieee; use ieee.std_logic_1164.all; entity siso_sipo is port(si,clk: in std_logic;s0,p01,p02,p03:inout std_logic); end siso_sipo; architecture siso_d of siso_sipo is component D port(D,clk: in std_logic;Q:inout std_logic:='0'); end component; begin D1: D port map(si,clk,p01); D2: D port map(p01,clk,p02);

D3: D port map(p02,clk,p03); D4: D port map(p03,clk,s0); end siso_d; SIPO: architecture sipo_d of siso_sipo is component D port(D,clk: in std_logic;Q:inout std_logic:='0';Qb:inout std_logic:='1'); end component; begin D1: D port map(si,clk,p01); D2: D port map(p01,clk,p02); D3: D port map(p02,clk,p03); D4: D port map(p03,clk,p04); end sipo_d; RTL SCHEMATIC:

D FF D FF

D FF

D

D FF

F F

WAVEFORMS:

RESULT:- Hence the Serial In Serial Out(SISO) and Serial In Parallel Out(SIPO) shift registers using single entity and multiple architectures is simulated in VHDL and its functionality is verified.

5(b)

PISO & PIPO Shift Register

PISO Shift Register AIM:- To write a code in VHDL for simulating the Parallel In Serial Out shift register(PISO) and to verify its functionality. APPARATUS: Model Sim 5.7 VHDL CODE:COMPONENT D:library ieee; use ieee.std_logic_1164.all; entity D is port(D,clk: in std_logic;Q:inout std_logic:='0';Qb:inout std_logic:='1'); end D; architecture behaviour of D is begin process(D,clk) begin if (clk='0' and clk'event)then Q<=D; Qb<=not(D); end if; end process; end behaviour; COMPONENT OR2:library ieee; use ieee.std_logic_1164.all; entity or2 is port(a,b: in std_logic;c: out std_logic); end or2; architecture dataflow of or2 is begin c<= a or b; end dataflow;

COMPONENT AND2:library ieee; use ieee.std_logic_1164.all; entity and2 is port(a,b: in std_logic;c: out std_logic); end and2; architecture dataflow of and2 is begin c<= a and b; end dataflow;

COMPONENT NOT1:library ieee; use ieee.std_logic_1164.all; entity not1 is port(a: in std_logic;c: out std_logic); end not1; architecture dataflow of not1 is begin c<= not(a); end dataflow;

TOP MODULE:library ieee; use ieee.std_logic_1164.all; entity piso is port(p0,p1,p2,p3,s,clk: in std_logic;Qo: inout std_logic); end piso; architecture piso of piso is component D port(D,clk: in std_logic;Q:inout std_logic:='0';Qb:inout std_logic:='1'); end component; component and2 port(a,b: in std_logic;c: out std_logic); end component;

component or2 port(a,b: in std_logic;c: out std_logic); end component; component not1 port(a: in std_logic;c: out std_logic); end component; signal s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,q1,q2,q3: std_logic; begin n1: not1 port map(s,s1); D1: D port map(p0,clk,q1,open); a1: and2 port map(s,q1,s2); a2: and2 port map(s1,p1,s3); O1: or2 port map(s2,s3,s4); D2: D port map(s4,clk,q2,open); a3: and2 port map(s,q2,s5); a4: and2 port map(s1,p2,s6); O2: or2 port map(s5,s6,s7); D3: D port map(s7,clk,q3,open); a5: and2 port map(s,q3,s8); a6: and2 port map(s1,p3,s9); O3: or2 port map(s8,s9,s10); D4: D port map(s10,clk,Qo,open); end piso; RTL SCHEMATIC:

p0 p1 p2 p3 s clk

PISO

Q0

WAVEFORMS:

RESULT:- Hence the Parallel In Serial Out shift register(PISO) is simulated in VHDL and its functionality is verified.

PIPO Shift Register AIM:- To write a code in VHDL for simulating the Parallel In Parallel Out shift register(PIPO) and to verify its functionality. APPARATUS: Model Sim 5.7 VHDL CODE:library ieee; use ieee.std_logic_1164.all; entity pipo is port(d: in std_logic_vector(3 downto 0);cl,en,clk: in std_logic;q: out std_logic_vector(3 downto 0)); end pipo; architecture beh of pipo is begin

process(cl,clk) begin if(cl='1') then q<="0000" after 5 ns; elsif(clk'event and clk='1') then if(en='1') then q<= d after 5 ns; end if; end if; end process; end beh;

RTL SCHEMATIC:

PIPO

WAVEFORMS:

RESULT:- Hence the Parallel In Parallel Out shift register(PIPO) is simulated in VHDL and its functionality is verified. VIVA QUESTIONS: 1. Give the general form of PROCESS statement. 2. Give the general form of FOR-LOOP statement. 3. Give the general form of WHILE-LOOP statement. 4. What is meant by sensitivity list? 5. How the input and output signals are specified in the ENTITY declaration? ANSWERS: 1.

[process_label:] PROCESS [(signal name {, signal name})] [VARIABLE declarations] BEGIN [WAIT statement] [Simple Signal Assignment Statements] [Variable Assignment Statements] [IF statements] [CASE statements] [LOOP statements] END PROCESS [process_label];

2. [loop_label:] FOR variable_name IN range LOOP statement; {statement;} END LOOP[loop_label];

3. [loop_label:] WHILE boolean_expression LOOP statement; {statement;} END LOOP[loop_label]; 4. The signals declared inside the parentheses in a PROCESS statement are called sensitivity list. They indicate which signals the process depends on. 5. Using the keyword PORT.

IC’s LABORATORY

CYCLE-II:

1. Verification of truth tables of Logic Gates using IC’s. AIM: To verify the truth tables of all logic gates. APPARATUS: i) ii iii) iv) v) vi) vii) viii)

IC 74LS04 (NOT Gate) IC 74LS08 ( two input AND gate) IC 74LS32 (two input OR gate) IC 74LS86 (two input EX-OR gate) IC 74LS00 (two input NAND gate) IC 74LS02 (two input NOR gate) Digital IC Trainer Kit Connecting Wires

NOT GATE: Symbol:

Truth table: Input A

Output Q

A 0

1

1

0

Q

PIN DIAGRAM:

AND GATE:

TRUTH TABLE:

SYMBOL: Input A Input B Output Q A

0

0

0

0

1

0

1

0

0

1

1

1

Q

B

PIN DIAGRAM:

OR GATE: SYMBOL:

TRUTH TABLE:

Input A Input B Output Q A B

Q

PIN DIAGRAM:

0

0

0

0

1

1

1

0

1

1

1

1

NAND GATE: SYMBOL & TRUTH TABLE:

PIN DIAGRAM:

EXCLUSIVE –OR GATE (EX-OR): SYMBOL:

TRUTH TABLE: Input A

Input B

Output Q

A B

Q

PIN DIAGRAM:

0

0

0

0

1

1

1

0

1

1

1

0

NOR GATE: SYMBOL:

TRUTH TABLE

A

Input A Input B Output Q

B

Q

PIN DIAGRAM:

0

0

1

0

1

0

1

0

0

1

1

0

PROCEDURE: 1. Connect six gates as per the circuit diagram 2. Verify the truth tables. PRECAUTIONS: 1. Avoid loose and wrong connections. 2. The truth tables should be verified properly. RESULT: The truth tables of six logic gates are verified. VIVA VOICE: 1. What is a Logic gate? Logic gate are the basic elements that can make up a digital system. The electronic gate is a circuit that is able to operate on a number of binary inputs in order to perform a particular logical function. 2. What are the universal gates and why they are called so? NAND and NOR gates are called universal gates because these can be used to form any basic gates AND, OR and NOT.

2. Design a combinational circuit for Code Converters using IC’s. (i)AIM: To convert 4 bit gray code to binary code. APPARATUS: I. IC 74LS86 (two input EX-OR gate) II. Digital IC Trainer Kit III. Connecting Wires

CONVERTION TABLE: INPUT BCD Code

OUTPUT GRAY CODE

B4

B3

B2

B1

G4

G3

G2

G1

0 0 0 0 0 0 0 0 1 1

0 0 0 0 1 1 1 1 0 0

0 0 1 1 0 0 1 1 0 0

0 1 0 1 0 1 0 1 0 1

0 0 0 0 0 0 0 0 1 1

0 0 0 0 1 1 1 1 1 1

0 0 1 1 1 1 0 0 0 0

0 1 1 0 0 1 1 0 0 1

Minimized expressions using K-map G4=B4 G3=B4 XOR B3 G2=B3 XOR B2 G1=B2 XOR B1 LOGIC DIAGRAM:

PROCEDURE: 1. Connects are made as per the logic diagram 2. Verify the conversion table. PRECAUTIONS: 1. Avoid loose and wrong connections. 2. The truth tables should be verified properly. RESULT: The conversion of BCD code to Gray Code is designed and verified using conversion table.

(Ii)AIM: To convert 4 bit Gray code to Binary code. APPARATUS: I. IC 74LS86 (two input EX-OR gate) II. Digital IC Trainer Kit III. Connecting Wires

CONVERTION TABLE: INPUT GRAYCODE

OUTPUT Binary Code

G4

G3

G2

G1

B4

B3

B2

B1

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0

0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0

0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Minimized expressions using K-map B 4= G 4 B3=B4 XOR G3 B2=B3 XOR G2 B1=B2 XOR G1

LOGIC DIAGRAM:

PROCEDURE: 1. Connects are made as per the logic diagram 2. Verify the conversion table. PRECAUTIONS: 1. Avoid loose and wrong connections. 2. The truth tables should be verified properly. RESULT: The conversion of Gray Code to Binary code is designed and verified using conversion table.

3. Design a combinational circuit for Adders & Subtractors using IC’s. AIM: To design an adder and subtractor circuit to perform the following Arithmetic Operations. i) D+7 iii) 9E+FC ii) F-C iv) 3C-1E APPARATUS: 1) 2) 3) 4)

2 Input Ex-Or Gates (74LS86) –2 NO’S 4 Bit Binary Adder (74LS83)-2NO’S Digital IC Trainer Kit Logic Probes and Connecting Wires 10 8 3 1

PIN DIAGRAM OF 74LS83

A1 A2 A3 U1 A4

11 7 4 16

C0

C4

74LS83

LOGIC CIRCUIT 4-BIT ADDER SUBTRACTOR B2

U5

B1

U4

B0

U2

M

U3

7486 A3

1

Cout

A2

3

14

A1

8

A0

10

16

4

7

11

4 BIT BINARY ADDER

13

15

S4

2

S1 9

6

S3

C in

=0,ADD

74LS83

S2

=1.SUB

S1

9 6 2 15

B1 B2 B3 B4

13

B3

S1 S2 S3 S4

14

LOGIC CIRCUIT FOR 8-BIT ADDER SUBTRACTOR

PROCEDURE: 4 BIT BINARY ADDER-SUBTRACTOR 1) Set the circuit of 7483 IC for addition (D+7) and 2’s complement subtraction (F-C).

2) For addition operation the ‘m’ input is set ‘0’ and the inputs D and 7 bits are set as a and b carry input ‘cin’ is set ‘ 0’. 3) The result obtained is the sum of D and 7. 4) For subtraction operation the ‘ m’ input is set ‘1’ and the inputs F and C are fed as a and b the carry input ‘ cin’ is set as ‘ 1’. 5) The result is the 2’s complement subtraction F-C. 8 BIT ADDERS AND SUBTRACTOR 1) Set the cascade circuit of two 4 bit Binary Adder (2no’s Of 7483 ICs) as shown. 2) For addition operation the ‘ m’ input is set ‘0’ and the inputs 9e and Fc bits are set as a and b carry input ‘cin’ is set ‘ 0’. 3) The result obtained is the sum of 9e and Fc. 4) For subtraction operation the ‘ m’ input is set ‘1’ and the inputs 3c and 1e are fed as a and b the carry input ‘ cin’ is set as ‘ 1’. 5) The result is the 2’s complement subtraction 3c-1e

OBSERVATIONS:

4 BIT BINARY ADDER - SUBTRACTOR INPUTS

M

Cin

0

OUT PUTS Σ4 Σ3 Σ2 Σ1

A3 A2 A1 A0

B3 B2 B1 B0

0

1

1

1

1

1

1

0

0

1

0

1

1

0

1

1

1

1

1

1

1

0

0

1

1

0

0

1

0

1

1

1

1

1

1

0

0

0

0

1

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

0

0

1

1

0

1

0

1

1

1

0

1

0

0

0

1

1

1

0

1

0

1

1

1

0

1

0

1

1

0

1

1

0

1

0

1

1

1

0

1

0

1

1

1

1

1

0

1

0

1

1

1

0

1

1

0

8 BIT BINARY ADDER - SUBTRACTOR INPUTS

OUT PUTS

A7 A6 A5 A4 A3 A2 A1 A0

B7 B6 B5 B4 B3 B2 B1 B0

Σ8 Σ7 Σ6 Σ5 Σ4 Σ3 Σ2 Σ1

Cout

0

0

0 1 1 1 1 0 0

0 0 0 1 1 1 1 0

0 1 0 1 1 0 1 0

0

0

1

0

0 1 1 1 1 0 0

0 0 0 1 1 1 1 0

0 1 0 1 1 0 1 1

0

1

0

0

0 1 1 1 1 0 0

0 0 0 1 1 1 1 0

0 0 0 1 1 1 0 1

1

1

1

0

1 1 1 1 0 0 0

0 0 0 1 1 1 1 0

0 0 0 1 1 1 1 0

1

0

0

1

0 0 1 1 1 1

0

1 1 1 1 1 1 1 0

1 0 0 1 1 0 1 0

1

0

1

1

0 0 1 1 1 1

0

1 1 1 1 1 1 1 0

1 0 0 1 1 0 1 1

1

1

0

1

0 0 1 1 1 1

0

1 1 1 1 1 1 1 0

1 0 1 0 0 0 0 1

0

1

1

1

0 0 1 1 1

0

1 1 1 1 1 1 1 0

1 0 1 0 0 0 1 0

0

M

Cin

0

1

PRECAUTIONS: 1. Avoid loose and wrong connections. 2. Handle the equipment carefully. RESULT: The given function is realized & the values of the truth table are verified.

VIVA VOICE: 1. What is 1’s compliment of a binary no? 1’s complement of a binary number is obtained by simply inverting (replacing 1 with 0 or 0 with 1) each bit in the number. 2. What is 2’s compliment of a binary no? 2’s complement is obtained by simply adding binary 1 to the 1’s complement. 3. What are the advantages of 1’s compliment subtraction? The 1’s complement subtraction can be accomplished with a binary adder. Therefore this method is useful in arithmetic logic circuits. 4. Which gate can be used for I’s complement? NOT gate or inverter is used for 1’s complement.

4. Design a sequential circuit for Flip-flop and verify its characteristics using IC’s. AIM: To verify the truth table of various flip-flops using logic gates i) R-S Flip-Flop iii) J-K Flip-Flop ii) D- Flip-Flop iv) T-Flip-Flop APPARATUS: 1) Quad 2-Input NAND Gate (7400) – 1 NO 2) Triple 3-Input NAND Gate (7420) – 1 NO 3) Quad 2-input NOR Gate (7402) -1 NO. 3) Not Gate (7404) – 1 NO 4) Digital IC Trainer Kit 5) Logic Probes and Connecting Wires SR FLIP FLOP:

(a) Logic diagram

(b) Truth table

Basic flip-flop circuit with NOR gates

Basic flip-flop circuit with NAND gates (a) Logic diagram

(b) Truth table

1. CLOCKED SR FLIP FLOP Logic diagram:

Truth table:

Characteristic Table for S – R Flip Flop: INPUTS

PREVIOUS OUTPUT (Qn)

(Qn+1)I

R

PRESENT OUTPUT(Qn+1)

S

0

0

X

X

Qn=0 (No change

QnI

0

1

X

X

Qn=1 (No change

QnI

1

0

0

0

Qn=0 (No change

QnI

1

1

0

0

Qn=1 (No change

QnI

1

1

0

1

0 (reset)

1

1

x

1

0

1 (set)

0

1

x

1

1

Forbidden

Forbidden

CLOCK

Characteristic Equation Qn+1 = S+RI Qn 2. D- FLIP-FLOP Logic diagram

Characteristic table

Characteristic Equation Qn+1= D

TRUTH TABLE: CLOCK 0 0 1 1

D 0 1 0 1

Qn+1 Qn= (No change Qn= (No change 0 1

3. J-K FLIP-FLOP:

Characteristic table:

Logic diagram

TRUTH TABLE: CLOCK 0 1 1 1 1

J X 0 0 1 1

4. T- FLIP-FLOP: Logic diagram

K X 0 1 0 1

Qn+1 Qn Qn 0 1 QnI

(Qn+1)I QnI QnI 1 0 Qn

Condition No change No change Reset Set Toggle

TRUTH TABLE: clock 0 1 1

T

Qn+1

(Qn+1)I

X 0 1

no change 1 0

0 0 1

CHARACTERISTIC TABLE: Qn

T

(Qn+1)I

0 0 1 1

0 1 0 1

0 1 1 0

CONDITION No change Toggle No change Toggle

PROCEDURE: 1) Connect the circuit as per the circuit diagrams. 2) For various flip-flops, the circuits are connected. 3) Giving various inputs for the connected flip-flops respectively. 4) And for different combinations of inputs the truth tables (outputs) are verified. PRECAUTIONS: 1. Avoid loose and wrong connections. 2. RESULT:

Handle the equipment carefully.

The Values of the Truth table are verified.

VIVA VOICE: 1. What is a flip flop? Flip-flop is a storage element used to store one bit of information. A flip-flop maintains its output state either at 1 or 0 until directed by an input signal to change its state. 2. What is the difference between a Latch and Flip flop? Storage elements that operate with signal levels are called latches where as those controlled by a clock transition are filp-flops. 3. What is the operation of D flip-flop? In D flip-flop during the occurrence of clock pulse if D=1, the output Q is set and if D=0, the output is reset.

5. Design a bidirectional Universal Shift Register Using IC74LS194. AIM: To verify the operation of Universal Shift Registers APPARATUS: i)

Universal Shift Registers (74194)

ii)

J-K Flip-Flop (7473)

iii)

Digital IC Trainer Kit

iv)

Logic Probes and Connecting Wires

PIN DIAGRAM:

Truth Table for Universal Shift Register: Inputs Mode Clr

Outputs

Serial

Parallel

Clk S1

S0

Left

L

X

X

X

X

H

X

X

H

X

H

H

H

H

X

H

L

H

H

H

L

H

H

H

H

H

Right

A

B

C

D

QA

QB

QC

QD

X

X

X

X

L

L

L

L

X

X

X

X

QAO

QBO

QCO

QD$O

X

a

b

c

d

a

b

c

D

X

H

X

X

X

X

H

QAn

QDn

QCn

H

X

L

X

X

X

X

L

QAn

QDn

QCn

L

H

H

X

X

X

X

X

QDn

QCn

QDn

H

H

L

H

L

X

X

X

X

X

QDn

QCn

QDn

L

L

L

H

X

X

X

X

X

X

QAO

QBO

QCO

QD$O

X X

Parallel Inputs CIRCUIT DIAGRAM:

PROCEDURE: 1) Connections are made as per the circuit diagram 2) For different combinations of inputs, the outputs Qa, Qb, Qc, Qd are observed and truth table is verified.

PRECAUTIONS: 1. Avoid loose and wrong connections. 2.

Handle the equipment carefully.

RESULT: The given function is realized using universal shift registers & its values of the truth table are verified. VIVA VOICE: 1. What is a shift register? A register capable of shifting binary information held in each cell to its neighboring cell, in a selected direction is called a shift register. 2. What are different types of shift registers? There are 4 types. They are 1. Serial in serial out shift register 2. Serial in parallel out shift register 3. Parallel in serial out shift register 4. Parallel in parallel out shift register 3. What is the difference between counter and register? The clock inputs of the flip-flops are from the previous flip-flop outputs in the counters. The output of the counter may be sequential or random. All clock inputs of all the flip-flops of shift register are connected to a single clock input. The output of the shift register will not be sequential.

6. Design of Counters using IC74LS73. AIM: To Design A Mod 6 Synchronous Counter Using J-K Flip-flops. APPARATUS: 1. 2. 3. 4.

J-K Flip-Flop (74LS73) – 2 2-Input Quad AND Gate (74LS08) –1 Digital IC Trainer Kit Logic Probes and Connecting Wires

Excitation Table for J – K Flip-Flop: Qn 0 0 1 1 Present state QC 0 0 0 0 1 1 1 1

QB 0 0 1 1 0 0 1 1

QA 0 1 0 1 0 1 0 1

Qn+1 0 1 0 1

J 0 1 X X

K X X 1 0

Nest state QC 0 0 0 1 1 0 1 0

QB 0 1 1 0 0 0 1 0

Excitation Values

QA 1 0 1 0 1 0 1 0

JC 0 0 0 1 X X X X

KC X X X X O 1 X X

JB 0 1 X X 0 0 X X

Minimization: Q BQ A QC

QBQA

QBQA

QBQ

1

X

X

1

1

X

X

X

QBQA

QBQ

QBQA

JA = 1

Q BQ A QC

QBQA

QBQA

X

1

1

X

X

1

X

X

KA = 1

KB X X 0 1 X X X X

JA 1 X 1 X 1 X X X

KA X 1 X 1 X 1 X X

Q BQ A

QC

QBQA

QC

QBQ

0

1

X

X

0

0

X

X

JB = Q BQ A

QBQA

QBQA

QC QA

QBQA

QBQA

QBQA

QBQ

X

X

1

0

X

X

X

X

KB = Q A Q BQ A

QBQA

QBQA

QBQA

0

0

1

0

X

X

X

X

QC

QBQ

JC = QAQB Q BQ A QC

QBQA

QBQA

QBQA

QBQ

X

X

X

X

0

1

X

X

KC = Q A TRUTH TABLE: CLK PULSE

Qc

Qb

Qa

0

0

0

0

1

0

0

1

2

0

1

0

3

0

1

1

4

1

0

0

5

1

0

1

CIRCUIT DIAGRAM:

clk

PROCEDURE: 1. The circuit for mod 6 synchronous counter is designed using J-K flip- flops. 2. After the circuit is realized, it is connected as per the circuit diagram. 3. First a clock pulse is given and the truth table is verified. 4. Next a clock pulse is applied to flip-flops and the timing diagram is noted from the C.R.O 5. The various time periods are noted and the timing diagram is plotted. PRECAUTIONS: 1. Avoid loose and wrong connections. 2. Handle the equipment carefully.

RESULT: The given function is realized using J-K FLIP-FLOP (7473) & their values of the truth table are verified. VIVA VOICE: 1. What is the difference between synchronous & asynchronous counters? In Asynchronous counters the count value cannot be changed easily, each flip-flop clock is driven by previous flip-flop output. In Synchronous counters the count value can be changed by design & flip-flop type, all the flip-flops must have a common clock input. 2. How lock out condition is avoided in counters? Lock out condition is avoided in practical circuits by giving a reset input or CLEAR input. 3. What are asynchronous inputs of a flip flop? CLEAR and PRESET are asynchronous inputs of a flip-flop.