Design Guidelines For Noise Optimization In Lna

Analog Integrated Circuits and Signal Processing, 46, 193–201, 2006 c 2006 Springer Science + Business Media, Inc. Manufactured in The Netherlands. 

Design Guidelines for the Noise Optimization of a 0.18 μ m CMOS Low-Noise Amplifier AHMED A. YOUSSEF Department of Electrical and Computer Engineering, University of Calgary, Calgary, AB, Canada T2N 1N4; Wireless Research Center, TRLab, AB, Canada E-mail: [email protected]

Received February 17, 2005; Revised April 7, 2005; Accepted April 28, 2005

Abstract. This paper presents the design considerations for the noise optimization of fully integrated tuned lownoise amplifiers (LNA) based on the four noise parameters and two-port noise theory. Specifically, this paper provides the design guidelines for a 0.18 μm CMOS tuned LNA. These guidelines give a useful indication to the design tradeoffs associated with noise figure, power dissipation and gate overdrive voltage for the LNA designed using this technology. As a case study, a 10 GHz LNA has been designed using 0.18 μm CMOS technology for a wireless LAN application. The amplifier has a 2.4 dB noise figure with a −13 dBm third-order input intercept point, while drawing 5 mW from a 1.8 V power supply. The results show that the proposed theoretical contours of constant noise figure which relate the gate overdrive voltage and power dissipation can accurately predict the noise performance of a 0.18 μm CMOS LNA design Key Words: Low-noise amplifier, noise figure, RF MOSFET design, noise optimization

1.

Introduction

The first stage of a receiver is typically a low-noise amplifier (LNA). The LNA should provide gain with sufficient linearity while providing stable 50 ohm input impedance. The additional constraint of low power consumption which is required for portable wireless systems further complicates the design process. The LNA noise figure is also one of the major design factors. The overall noise figure of the receiver depends primarily on the LNA noise performance. Therefore, the noise optimization procedure should be carefully analyzed taking the aforementioned constraints into consideration. The types of constraints, whether they are hard or soft, depend primarily on the target application. In some applications like a wireless LAN terminal the target for the front-end is to achieve the minimum possible noise figure (soft constraint) with the lowest power consumption (hard constraints) afforded by the technology used to implement the design. Therefore, the physical limits for these constraints should be analyzed and examined carefully. In traditional monolithic microwave integrated circuit (MMIC) design, active devices are used with fixed geometries and characteristics. For the given bias and frequency conditions, source impedance is selected to minimize the noise figure [1]. Since the optimum source impedance for noise differs from the power-match condition in general, this technique often results in large power consumption or input mismatching.

The noise optimization techniques for CMOS RF circuits permit greater flexibility in the selection of device geometries as well as matching elements and biasing conditions to minimize the noise figure for a specific gain or power dissipation [2]. This paper presents considerations for noise optimization of tuned LNAs. A quantitative analysis is conducted. Exact expressions for the noise are given. From these expressions, explicit design guidelines for 0.18 μm CMOS tuned LNAs are presented. Section 2 reviews the basic concepts of the noise figure, the four noise parameters and the classical noise optimization approach. Section 3.1 describes the Q-optimization approach used for noise optimization. This approach has been applied to 0.18 μm CMOS technology to find the optimum transistor size which corresponds to the minimum noise figure, for this technology. In Section 3.2, the noise optimization with power constraint, which is proposed in [2], has been applied to the same 0.18 μm CMOS technology to estimate the amount of noise figure degradation which must be tolerated in exchange for reduced power consumption. The expression for the optimum transistor size which is required to minimize the noise figure with a power constraint condition is also given in this section. This allows exploitation of the entire potential of integrated LNA designed in 0.18 μm CMOS technology. In Section 4, a design framework for the tuned LNA designed using a commercial 0.18 μm CMOS technology is described. In Section 5, a case study of the design of a 10 GHz 0.18 μm CMOS LNA

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for a wireless LAN terminal is presented. Section 6 concludes this study. 2.

The Classical Optimization Approach

2.1. Four-Noise Parameters Concept

the classical approach to determine the optimum source admittance, Yopt = G opt + jBopt . The effects of the thermally noisy channel charge are modeled by drain and gate current noise generators [5]. These currents are partially correlated with each other because they share a common origin, and possess spectral power given by the following equations:

The noise performance of a circuit is typically characterized by a noise factor F which indicates how much degradation occurs in the output signal-to-noise ratio due to the circuit’s internal noise.

i d2 = 4K T  f γ gdo

(3)

i g2 = 4K T  f δgg

(4)

where Total output noise power F= Output noise power due to the source impedance The noise factor of a linear circuit depends on the source impedance driving the given circuit. This dependence can be illustrated in terms of four-noise parameters (G u , Rn , and Yc (real and imaginary)) [3]: F =1+

G u + (Yc + Ys )2 Rn Gs

(1)

where G s is the real part of the source admittance, Ys is the source admittance, Yc is the correlation admittance, G u is the real part of the uncorrelated admittance and Rn is the equivalent noise resistance. The goal of the classical optimization approach is to find the optimum source admittance required to minimize the noise factor F. This approach can be readily applied to optimize the noise performance of MOSFET devices. A MOSFET device can be considered as a linear two-port network such that the four-noise parameters required to characterize its noise behavior can be extracted. These parameters can then be used to find the optimum source admittance Yopt . By presenting Yopt to a given MOSFET transistor, the lowest F that can be obtained with the given technology (Fmin ) could be achieved. In general, we can say that by using this technique, the LNA can be designed to achieve an F equal to Fmin .

The noise factor F can be expressed as follows [4]: |Ys − Yopt |2 Rn Gs

ig i ∗ c=  d i g2 i d2

(6)

With long channel devices, c can be predicted theoretically as −j0.395 [9]. The value of c is purely imaginary, reflecting the capacitance coupling between the channel and gate noise sources. After some lengthy algebraic derivation [5], the optimum source admittance for the MOSFET Yopt can be expressed as:  Yopt = ωC gs

   δα 2 δ (1 − |c|2 ) − jωC gs 1 − α|c| 5γ 5γ (7)

where a = gm /gd is unity for long channel devices and decreases as channel length scales down. The optimum source admittance is a parallel R-L circuit. As a result we can define an optimum quality factor Q opt which corresponds to the optimum source admittance [9]:

2.2. RF Noise in MOSFETs

F = Fmin +

ω2 C gs (5) ζ gdo and where gdo is the drain output conductance under zero drain bias, K is the Boltzmann constant, T is the absolute temperature,  f is the bandwidth, gg is the real part of the input admittance, and C gs is the gatesource capacitance. For long channel MOSFETs, noise parameters [γ ,δ,ξ ] in saturation are 2/3, 4/3, and 5 respectively [2, 6]. Recent research describes the behavior of those parameters for modern deep submicron processes. Some authors argue that the behavior is similar to the long channel model [7]. The correlation between the channel and gate noise sources can be represented by the correlation factor which is give by: gg =

(2)

where Fmin is the best performance that the circuit can achieve with the optimum source admittance condition (Ys = Yopt ), and Rn determines the sensitivity of F when Ys differs from Yopt . Knowing the four noise parameters for the MOSFET, we can directly apply the theory of

Q optc

   5γ  Bopt  2 − |c|  = δα =  ≈ 1.3  G opt 1 − |c|2

(8)

where the subscript c is used to depict that this is the quality factor deduced from classical optimization approach. Because (8) depends on the ratio of

Design Guidelines for the Noise Optimization of a 0.18 μm CMOS LNA

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impedance Z in of the amplifier is: Z in = s(L g + L s ) +

Fig. 1.

Tuned LNA input stage architecture.

1 + ωT L s sC gs

Where ω T is the cutoff angular frequency (gm /C gs ). As can be seen from (9), the source degeneration generates the real part at the input impedance. By choosing L s and L g independently, the desired input impedance can be obtained over a narrow band. Using the small-signal model, the output noise power density due to the drain thermal noise current i d and the gate thermal noise current i g can be found. Recalling the expression for the power spectral density of the drain noise current source from (3), and assuming the series resonance condition, the output noise power density Sd due to drain noise current can be written as: 4K T γ gdo Sd =  2 1 + ωTRLs s

Fig. 2.

Small-signal model for LNA noise calculations.

γ and δ it is reasonable to expect that those short channel phenomena will have only a second-order effect on Q optc .We observe that the optimum source susceptance is inductive in nature which is undesirable with respect to the requirements of the RF IC design. The requirement of a real optimum source impedance leads to the inductive source degenerated architecture or what is called the tuned amplifier. The series feedback with inductive source degeneration is used to shift the optimum noise admittance Yopt to the desired point. This shift allows having LNA design with a minimum noise figure and a maximum power gain condition simultaneously.

3.

Noise Performance of a Tuned Amplifier

3.1. The Q-Optimization Approach In the Q-optimization approach, we are going to extend the idea of the classical optimization approach to adopt a modern RF IC design. In this approach, the source resistance is assumed to be fixed to 50 ohm. The active device itself will be used to achieve Fmin for a designed LNA. The tuned amplifier input stage illustrated in Fig. 1 is one of the most commonly used LNA architectures because of its potential to achieve the best input match with excellent noise performance [10–12]. The input

(9)

(10)

where Rs is the source resistance. In the same manner the output noise power density due to i g can be found. However, additional mathematical steps are required to take the correlation between i d and i g into consideration. The gate noise current will be divided into two components, one component, i gc , is fully correlated with drain noise current and the other component, i gu , is uncorrelated to the drain noise current. The output noise power density Sgu due to the uncorrelated portion, assuming a series resonance condition, is given by: 4K T γ gdo δα 2 Sgu =  (1 − |c|2 )(1 + Q 2 ) 2 1 + ωTRLs s 5γ

(11)

where Q=

ωo (L s + L g ) 1 = Rs ωo Rs C gs

(12)

Note that the quality factor Q is a function in the source resistance Rs and the gate-source capacitance C gs of the MOSFET. Finding the output noise power density due to the correlated component is not straightforward. After some mathematical manipulations (see the Appendix) the output noise power density Sgc due to the correlated component of the gate noise current, assuming a series resonance condition, is given by:    δα 2 4K T γ gdo δα 2 2 2 Sgc =  |c| + 1 . (1+Q )−2|c| 2 5γ 5γ 1 + ωTRLs s (13)

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Hence, the noise factor F can be expressed as: F=

S Rs + Sd + Sgu + Sgc S Rs

(14)

where S Rs is the output noise power density due to the source impedance. Using (10), (11), and (13), the noise factor F can be expressed as:

 γ χ ωo F =1+ (15) α Q ωT where,  χ = 1 − 2|c|

α2δ α2δ + (1 + Q 2 ) 5γ 5γ

(16)

It is observed that χ includes terms which are constant and proportional to Q 2 . It follows that (15) will contain terms which are proportional to Q as well as inversely proportional to Q. Therefore, a minimum F exists for a particular Q. Q could be tuned by changing the device C gs to find the minimum noise factor (Rs is fixed). Keeping ω T constant, we can minimize the noise factor F by taking ∂F =0 ∂Q

Fig. 3. Contours of constant transconductance relating Q and F for 0.18 μm CMOS technology (freq. = 10 GHz, γ = 1 [7], δ = 3.3 [7]).

the corresponding optimum device width Wopt would be: Wopt =

17 25ωo LCox Rs

(19)

In this approach, we tune the transistor width rather than Rs . It is expected to achieve noise factor equal to Fmin of a single transistor because both of these approach have the same basis. 3.2. Comparison to Power Constrained Design

which, after some algebraic manipulation results in  Q opt =



1+

5γ 5γ − 2|c| ≈ 1.6. δα 2 δα 2

(17)

Since F is a function of two variables (Q and ω T ), one can define contours for the constant ω T which illustrate the behavior of F for arbitrary Q. However, it is more effective for the designer to plot these contours for fixed gate overdrive, for example, as device width varies, resulting in variable Q with approximately constant ω T . Using the relation between ω T and the effective transconductance G m of the amplifier, assuming a series resonance condition, results in [13]: Gm =

ωT 2ωo Rs

(18)

The contours for constant G m (fixed ω T ) are shown in Fig. 3, where input impedance match is maintained at all Q values and G m values. Note that the minimum F occurs around Q opt = 1.6 as deduced earlier in (17). To generate this plot, we have adopted the assumption that the ratio of γ and δ is unchanged by hot electron effects and that c is bias independent [14]. Once Q opt has been determined for fixed G m or overdrive voltage,

Since power consumption is an important design constraint, a useful noise optimization technique must consider power as a design parameter. In some application, the power consumption could be considered as a hard constrained while the noise factor F as a soft constrained. To develop the desired noise optimization technique, Shaffer and Lee [2] express (15) in a way that takes power consumption explicitly into account. Given a specified bound on power consumption the method should yield the optimum device that minimizes noise. The resulting noise factor is [2]: F =1+

γ ωo L f (V, PD ) 3υsat

(20)

where υsat is the carrier saturation velocity, PD is the power consumption of the amplifier, and V is the relative gate overdrive voltage with respect to the velocity saturation field strength. In this expression, f (V, PD ) is a ratio of two sixth-order polynomials of V , given by [9]: f (V, PD ) =

f 1 (V ) + PPDo f 2 (V )  2 V 3 1 + V2 (1 + V ) PD Po

(21)

Design Guidelines for the Noise Optimization of a 0.18 μm CMOS LNA

Fig. 4. Contours of constant noise figure relating V and PD for 0.18 μm CMOS technology (freq. = 10 GHz, γ = 1 [7], δ = 3.3 [7]).

Fig. 5. Contours of constant PD relating F and Q for 0.18 μm CMOS technology (freq. = 10 GHz, , γ = 1 [7], δ = 3.3 [7]).

where 



In this case the optimum transistor width is given by:



δ V (1 + V )4 1 + 5γ 2

 δ V 2 2 + (1 + V ) 1 + 5γ 2 (22)

f 1 (V ) = (1 + V )6 − 2|c|

and

 δ V 2 4 f 2 (V ) = V 1+ 5γ 2

(23)

where Po is a constant determined by physical technological parameters and design target specifications. Based on this technique, the contours of the constant F relating PD and V for a commercial 0.18 μm CMOS technology are shown in Fig. 4. These contours give a useful indication of the design tradeoffs between noise figure, power dissipation and gate overdrive voltage for this CMOS technology. The noise factor can be minimized, for fixed power, by taking ∂ f (V, PD ) =0 ∂V

(24)

which results in Q opt P D =

√



 3 1 − 2|c|

5γ 5γ + 2 δα 2 δα

0.5 ≈ 2.6 (25)

The Q opt P D yields the best noise performance for a given power dissipation. We could observe that it is larger than the optimum Q opt which is derived in Section 3.1.

197

Wopt P =

2 5ωo LCox Rs

(26)

Similarly to Fig. 4, we show the contours of constant power relating Fand Q, for a commercial 0.18 μm CMOS technology in Fig. 5. These contours are useful for selecting device geometries for a particular power dissipation and desired F. This power-constrained approach permits power consumption to be considered as an explicit parameter which is useful in low-power systems. 4.

Discussion

The optimum Q is that which balances the contribution of drain and gate noise generators. In the classical approach, Rs is varied to locate the optimum, which is not suitable for the modern RF IC design. In the Q-optimization approach, the device C gs is varied, and this consequently changes the relative powers of the two noise generators. The minimum noise factor is achieved for the optimum balance of these two generators without altering ω T , and hence the result is similar to Q optc obtained by the classical approach. The principal difference between Q optc and Q opt is that the LNA is operated off-resonance in the classical optimization approach due to the fact that Im{Yopt } = sCgs , as indicated in (7). In Q-optimization approach, a series resonance condition has been assumed. Figure 3 suggests finding the optimum Q for fixed ω T which correspond to fixed G m , overdrive voltage. This means that the designer will tune the transistor width to achieve the minimum noise factor for a fixed overdrive voltage. Changing the transistor width actually affects the bias current and at the same times the

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power consumption. Therefore, we can say that Fig. 3 seeks the optimum power consumption which yield the best noise behavior for a given overdrive voltage, all under the assumption of a matched input impedance. On the other hand, we can say that Fig. 5 illustrates the optimum Q, and therefore the optimum transistor width under a power constrained condition. This means that the designer will seek the optimum overdrive voltage which yields the best noise behavior for a given power, under the assumption of matched input impedance. In this approach, we could say that the achievable minimum noise factor is higher than Fmin of a single transistor. The question now arises as to which profile the designer should use for the LNA design. The powerconstrained analysis suggests an optimum Q opt P D that is quite different from that derived in the Q-optimization approach. To compare between them, Eq. (15) can be used to find the minimum noise factor in each case. The minimum noise factor Fmin for each case is given as follows:

Fmin Q ≈ 1 + 0.8

Fmin P ≈ 1 +

ωo ωT

ωo ωT

 (27)

 (28)

where the subscripts, Q and P refer to the Q-optimization approach and the power constrained approach respectively. Assuming a fixed ω T , we can see that the power constrained condition results in a loss of 0.5 dB to 1 dB in the noise figure. Therefore, the designer may use Fig. 3 for superior noise performance design. However, s/he could use Fig. 5 for reduced power consumption design and excellent noise figures are still possible. Another important issue appears when we compare between these two approaches at the same power dissipation. Since ω T is not fixed, we can say that the higher Q of the power constraint result leads to a narrow optimum device with higher current density for a given power consumption. The ω T ratio for the two cases is: ωTP D gm P D C gs Q = ≈ ω TQ gm Q C gs P D



Q optPD Q optQ

 32

= 2.32 (29)

In this expression the subscript PD refers to powerconstrained optimization and Q refers to the Qoptimization approach. Based on (27), (28), and (29), we note that for a given power consumption the power constrained optimization yields superior noise performance with larger gain than

Fig. 6.

Design framework trade-offs.

its lower Q counterpart. The result is that the best LNA design in this case could be achieved using Fig. 5. In summary, we can say that if the noise factor F is a hard constraint imposed by your target application, Fig. 3 will help you to find the optimum transistor width for your LNA design. Hence, you could achieve the lowest F that can be obtained with the given technology. However, if the power dissipation is a hard constraint for your design, Fig. 5 should be used to optimize your LNA. You could select the transistor width which helps to achieve the best possible F, not the lowest F, at the required power consumption. The Matlab code used to generates all the noise optimization contours could be generic. Therefore, the LNA design could be automated as long as the designer provides the parameters which are related to the underlying technology and assigns the supply voltage and the frequency of operation. Another feature is the inverse dependence of the noise figure on ω T . Continued improvements in technology will therefore lead to improve the noise performance at a given frequency of operation. However, this improvement is limited because of the finite on-chip inductor Q’s. The design framework provided in this section deals with power consumption, noise figure and amplifier gain trade-offs, as shown in Fig. 6. Aside from these trade-offs, the LNA should accommodate large signals without distortion, which is quantified by IP3. However, we can say that for two stages LNA design, the noise and linearity burdens are separated to each stage. The first stage amplifier is designed for optimum noise performance and the second stage is implemented to prevent linearity degradation.

5.

A Case Study: Wireless LAN Low—Noise Amplifier

To evaluate the LNA performance, a single-ended LNA intended to achieve 5 mW of power consumption is designed using a 0.18 μm CMOS technology. The LNA has been designed for the TRLabs Gigabit Radio which is considered as a prototype gigabit-per-second wireless network operating at 10 GHz [15–17]. A complete schematic diagram is shown in Fig. 7. The cascoded architecture [18–20] has been selected to provide

Design Guidelines for the Noise Optimization of a 0.18 μm CMOS LNA Table 1.

LNA specifications.

Parameter Frequency Supply voltage Power consumption Available gain S11 IIP3 Noise figure (input stage)

Fig. 7.

199

Value 10 GHz 1.8 V 5 mW 20 dB −24 dB −13 dBm 1.7 dB

The complete schematic diagram for the LNA.

a high reverse isolation, which improve the stability and simplify input port matching. All the equations derived earlier are still valid since the effect of the common gate transistor M2 on the noise and frequency response are neglected [20]. Figure 5 will be used during the design due to the power constraint condition. Using Fig. 5, the optimum Q opt for the best noise figure at that power is about 3, which a corresponding Fmin P of 1.7 dB. At frequency f equal to 10 GHz and gate oxide capacitance Cox equal to 8.45 mF/m2 the width of M1 is equal to 120 μm. The supply voltage is chosen to be 1.8 V to provide voltage headroom for the cascoded transistor M2. The bias current is chosen to provide the optimum overdrive voltage for M1 (corresponding to 5 mW), using M3 and R1. The spiral inductor Ls is implemented using the metal 6 layer and its value is chosen to be 0.25 nH to provide a 50 input impedance. The required gate inductor Lg to cancel out the imaginary part of the input impedance is 2 nH. To achieve the best noise figure, M2 needs to be optimized as well. As the width of the cascoded transistor (W2 ) increases, the generated noise power from the cascoded stage also increases. Therefore, we can say that the smaller W2 improves the noise figure by reducing the noise contribution of M2. However, due to the Miller effect, the required Ls for the 50 input match increases as W2 . become smaller. Consequently, smaller W2 yields a different optimum condition for the noise behavior. W2 is swept with the minimum channel length. An optimum width is found to be W2 – W1 and it increases the overall noise figure by about 0.3 dB. Figure 8 shows simulated power gain S21, input matching S11 and the reverse isolation S12. The noise figure for the input stage is quite close to the predicted value and demonstrate that the proposed methodology accurately predict the noise performance of 0.18 μm CMOS LNA designs. The performance of the LNA is summarized in Table 1.

Fig. 8. The simulated power gain, input matching and the reverse isolation.

6.

Conclusion

Based on the noise parameters of a 0.18 μm MOSFET and on the results derived from two-port noise theory, considerations for a fully integrated LNA design are presented. The noise performance of the tuned LNA is primarily controlled by the device width which determines the noise-matching condition. Contours of constant noise figure relating the gate overdrive voltage and power dissipation for a commercial 0.18 μm MOSFET device are generated. These contours give a useful indication of the design tradeoffs between noise figure, power dissipation, and gate overdrive voltage for the LNA design. A case study as a proof of concept has been presented and examined.

Appendix Finding the output noise power due to the correlated component is not straightforward since the amplitudes of the drain noise current and the correlated component of the gate noise current should be summed together

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before the powers of the various contributors are summed. To do that let us use the small-signal model represented at Fig. 2, the output noise current taking the correlated portion of the gate noise current into consideration is given by: In,out = gm vgs + i d

(A1)

where i d is the drain noise current, vgs is the sourcegate voltage, and gm is the transconducatance. Apply Kirchoff’s voltage law (KVL) to the input loop of Fig. 2 to find an expression for vgs in terms of the correlated component of the gate noise current and the drain noise current, result in: vgs =

4K T γ gdo δα 2 2 |c| (1 + Q 2 ) 2 5γ ωT L s 1 + Rs

S1 ( f )|H1 ( f )|2 = 

(A9) 4K T γ gdo S2 ( f )|H2 ( f )| =  2 1 + ωTRsL s 2

 δα 2 4K T γ g do 2Re[S12 ( f )H1 ( f )H2∗ ( f )] = −  2 2|c| 5γ 1 + ωTRsL s (A11)

Hence, the output noise power So due to the correlated component of the gate noise (So = Sgc ) can be given by: Sgc

{ jω(L g + L s ) + Rs }i gc − jωL s i d gs (L g + L s ) + jωC gs + jωL s gm + 1 (A2)

−ω2 C

gm Q 1+

ωT L s Rs

1+

This work is supported by the Alberta informatics Circle of Research Excellence (iCORE), NSERC, TRLabs, and the Canadian Microelectronics Corporation, CMC.



Rs + jω(L g + L s ) i gc

1

+

ωT L s Rs

id

(A3) References

where Q is given in (12). To find the output noise power So , we should take the correlation between i gc and i d into account. This can be done by using: So ( f ) = S1 ( f )|H1 ( f )|2 + S2 ( f )|H2 ( f )|2 + 2Re[S12 ( f )H1 ( f )H2∗ ( f )]

(A4)

In our case, 2 S1 ( f ) = i gc

S2 ( f ) = i d2  2 .i 2 S12 ( f ) = i gc i d∗ = − i gc d H1 ( f ) = 

gm Q

H2 ( f ) = 

1

1+ 1+

ωT L s Rs ωT L s Rs

 4K T γ gdo δα 2 2 =  |c| (1 + Q 2 ) 2 5γ 1 + ωTRLs s   δα 2 − 2|c| +1 (A12) 5γ

Acknowledgments

Now, using (A2) to re-express (A1) as:

In,out = 

(A10)

(A5) (A6)

[Rs + jω(L g + L s )] (A7)

(A8)

Using (A5)–(A8), the three parts of the right-hand side of (A4) can be expressed as:

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Ahmed A. Youssef received the B.Sc. (Hon.) and M.Sc. degrees both in electrical engineering from Ain Shams University, Cairo, Egypt, in 1998 and 2002, respectively. Since 2003, he has been with the University of Calgary, AB, Canada, where he is currently working toward the Ph.D. degree in RF integrated circuits and systems. Mr. Youssef has joined the Wireless Research Center at TRLab, Alberta, Canada as a research associate in 2004. His research interests include the analog high speed integrated circuit for the wireless LAN applications. Mr. Youssef is the recipient of the Mobinil Telecommunication Inc. Pre-master Fellowship in 1999. He also received the Young Scientist award at the Maastricht General Assembly of the International Union of Radio Science in 2002 and an Honorable Mention at 2003 in the Symposium of the Microelectronics Research & Development in Canada, Montreal. Mr. Youssef received the Gordon Lewis Hedberg Doctoral Scholarship in 2005.