#design Experiments For Measurement And Modelling Of Substrate Noise
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Design Experiments for Measurement and Modeling of Digital Substrate Noise Generation Marc van Heijningen John Compiet Piet Wambacq Stephane Donnay
© IMEC 2000
1
IMEC, Belgium
Project partners
IWT project FRONTENDS
ESPRIT project BANDIT
- Alcatel Microelectronics - K.U. Leuven - IMEC
- IMEC - K.U. Leuven - Ericsson Radio Systems
© IMEC 2000
Outline • Motivation • Introduction Substrate Noise Generation • low-level (SPICE) modeling and measurements • Conclusions
© IMEC 2000
Goal: simulate substrate noise generation of large digital circuits
generation propagation © IMEC 2000
impact
Approach: • Find simple but accurate SPICE substrate models for digital standard cells • Very the SPICE substrate noise simulations with measurements • Develop a high-level substrate noise simulation methodology, based on the SPICE models • At first, for low-ohmic epi-type substrates (Alcatel Microelectronics 0.5 um CMOS)
© IMEC 2000
Outline • Motivation • Introduction Substrate Noise Generation • low-level (SPICE) modeling and measurements • Conclusions
© IMEC 2000
Two sources of substrate noise: switching gates and the power supply
digital
analog
Vdd
Vdd
Vss
Vss
2 1 2
© IMEC 2000
External parasitics create power supply noise package
bondwire
IC trace pin L
R
L,R,C
L
R
1 Ghz => Z = 75 ohm 4 nH 0.01 ohm
© IMEC 2000
4 nH 1 ohm 2 pF
4 nH 0.1 ohm
Dominant noise source is determined by the external parasitics Vsub_pp[mV] 1000 noise coupling from MOSFETs is dominant
noise coupling from power supply is dominant
100
total generated substrate noise 10
only MOSFET noise only power supply noise coupling
1 1 pH
10 pH
100 pH
1 nH
inductance in power supply connection
© IMEC 2000
10 nH
Substrate noise versus package parasitics Wirebond and Flipchip implementation
W
Log(Vsub,rms)
F
Log(R) © IMEC 2000
Log(L)
Outline • Motivation • Introduction Substrate Noise Generation • low-level (SPICE) modeling and measurements • Conclusions
© IMEC 2000
Epi-type substrate can be approximated by one electrical substrate bulk node
p- epi
10 Ùcm
4 ìm
epi type substrate low-ohmic bulk 500 ì m
↓
1 electrical node p+ bulk
© IMEC 2000
0.01 Ùcm
Low-level (SPICE) substrate model
in
Vss
Vdd
out
p+
n+
n+
p-well
p- epi p+ bulk
© IMEC 2000
p+
n-well
p+
n+
Active substrate noise sensor to directly measure the substrate voltage
© IMEC 2000
Transfer function of the noise sensor
10
peaking due to parasitics in measurement setup
amplification [dB]
5
measurement simulation
0 -5 -10 -15 -20 3 10 © IMEC 2000
4
10
5
10
6
7
10 10 10 frequency [Hz]
8
9
10
10
10
Experimental ASICs to verify the lowlevel SPICE substrate models AuE 0.5um CMOS, 3.3 V test chip with noise generators
AuE 0.5um CMOS, 3.3V 86kgate ASIC DIGITAL MULTIRATE UP/DOWN CONVERTER
power region 1 power region 2
ANALOG NOISE SENSORS
© IMEC 2000
DIGITAL NOISE GENERATORS
ANALOG NOISE SENSORS
Clocked ring oscillator used for substrate noise generation
7x D
Q
CLK 4 or 6 x
© IMEC 2000
4 or 6 x
4 or 6 x
Dominant substrate noise source determines the noise waveform Vsub [mV]
Noise coupling from source/drain nodes
6
0
-6
0
Vsub [mV]
10
time [ns]
20
30
Noise coupling from the on-chip power/ground
50
0
-50 0 © IMEC 2000
10
time [ns]
20
30
Good agreement between measured and simulated substrate noise Vsub [mV] 25
measurement SPICE
20 15 10 5 0 -5 -10 -15 0
5
10
15 time [ns]
© IMEC 2000
20
25
30
>80% of noise power is generated by simultaneous switching of core cells Vsub [mV] 40
20
0
-20 core switching
output switching
-40 20
20.1
20.2
20.3 time [us]
© IMEC 2000
20.4
20.5
Substrate noise power scales as CMOS power consumption : Vsub2 ~ f Vdd2
Vsub [mVrms] at Vdd=3.3V
25
100
Vsub [mVrms] at Fclk = 50 MHz linear
20
slope 0.5
15
10
10 1 0.1
5 1
10 Fclk [MHz]
© IMEC 2000
100
2
2.5
3
3.5 Vdd [V]
4
4.5
Frequency spectrum of generated substrate noise
MOSFETs
© IMEC 2000
power supply
Increase of substrate noise at clock multiples and due to ringing Vsub [dBV] data input clock
data output clock
-40
+40 dB at clock multiples
+20 dB from ringing
-60
-80
-100
0
50
ringing © IMEC 2000
100 Freq [MHz]
150
200
Conclusions from the measurements • in most practical cases, substrate noise is caused by power supply noise coupling • simultaneous switching of core cells (mostly flipflops) generate more noise than IO buffers • ringing of the power supply will increase the substrate noise • in the frequency domain, substrate noise is concentrated at multiples of the digital clock frequency, with peaks up to 40 dB above the substrate noise floor © IMEC 2000
Conclusions on modeling • when modeling and simulating substrate noise generation all noise sources should be taken into account: • switching gates • power supply noise • package parasitics
• for epi-type substrates a simple SPICE substrate model can be used
© IMEC 2000
Related work and References • Related work: High-level modeling and simulation of digital substrate noise generation • BANDIT project (see HTTP://www.imec.be/bandit/)
• References: • M. van Heijningen, J. Compiet, P. Wambacq, S. Donnay, M. Engels, and I. Bolsens, "Analysis and Experimental Verification of Digital Substrate Noise Generation for Epi-Type Substrates," IEEE J. Solid-State Circuits, vol. 35, pp. 1002-1008, July 2000. • M. van Heijningen, M. Badaroglu, S. Donnay, M. Engels, and I. Bolsens, "High-Level Simulation of Substrate Noise Generation Including Power Supply Noise Coupling," in Proc. 37nd Design Automation Conference, pp. 446-451, 2000. • Y. Rolain, W. van Moer, G. Vandersteen, and M. van Heijningen, "Measuring mixed signal substrate coupling," in Proc. IMTC'2000, Baltimore, May, 2000. • M. van Heijningen, J. Compiet, P. Wambacq, S. Donnay, M. Engels, and I. Bolsens, "Modeling of Digital Substrate Noise Generation and Experimental Verification Using a Novel Substrate Noise Sensor," in Proceedings of the ESSCIRC, pp. 186-189, 1999. • M. van Heijningen, J. Compiet, P. Wambacq, S. Donnay, and I. Bolsens, "A Design Experiment for Measurement of the Spectral Content of Substrate Noise in Mixed-Signal Integrated Circuits," in Proc. 1999 Southwest Symposium on Mixed-Signal Design, April 11-13, Tucson AZ, USA, pp. 27-32, 1999.
© IMEC 2000
© IMEC 2000
1
IMEC, Belgium
Project partners
IWT project FRONTENDS
ESPRIT project BANDIT
- Alcatel Microelectronics - K.U. Leuven - IMEC
- IMEC - K.U. Leuven - Ericsson Radio Systems
© IMEC 2000
Outline • Motivation • Introduction Substrate Noise Generation • low-level (SPICE) modeling and measurements • Conclusions
© IMEC 2000
Goal: simulate substrate noise generation of large digital circuits
generation propagation © IMEC 2000
impact
Approach: • Find simple but accurate SPICE substrate models for digital standard cells • Very the SPICE substrate noise simulations with measurements • Develop a high-level substrate noise simulation methodology, based on the SPICE models • At first, for low-ohmic epi-type substrates (Alcatel Microelectronics 0.5 um CMOS)
© IMEC 2000
Outline • Motivation • Introduction Substrate Noise Generation • low-level (SPICE) modeling and measurements • Conclusions
© IMEC 2000
Two sources of substrate noise: switching gates and the power supply
digital
analog
Vdd
Vdd
Vss
Vss
2 1 2
© IMEC 2000
External parasitics create power supply noise package
bondwire
IC trace pin L
R
L,R,C
L
R
1 Ghz => Z = 75 ohm 4 nH 0.01 ohm
© IMEC 2000
4 nH 1 ohm 2 pF
4 nH 0.1 ohm
Dominant noise source is determined by the external parasitics Vsub_pp[mV] 1000 noise coupling from MOSFETs is dominant
noise coupling from power supply is dominant
100
total generated substrate noise 10
only MOSFET noise only power supply noise coupling
1 1 pH
10 pH
100 pH
1 nH
inductance in power supply connection
© IMEC 2000
10 nH
Substrate noise versus package parasitics Wirebond and Flipchip implementation
W
Log(Vsub,rms)
F
Log(R) © IMEC 2000
Log(L)
Outline • Motivation • Introduction Substrate Noise Generation • low-level (SPICE) modeling and measurements • Conclusions
© IMEC 2000
Epi-type substrate can be approximated by one electrical substrate bulk node
p- epi
10 Ùcm
4 ìm
epi type substrate low-ohmic bulk 500 ì m
↓
1 electrical node p+ bulk
© IMEC 2000
0.01 Ùcm
Low-level (SPICE) substrate model
in
Vss
Vdd
out
p+
n+
n+
p-well
p- epi p+ bulk
© IMEC 2000
p+
n-well
p+
n+
Active substrate noise sensor to directly measure the substrate voltage
© IMEC 2000
Transfer function of the noise sensor
10
peaking due to parasitics in measurement setup
amplification [dB]
5
measurement simulation
0 -5 -10 -15 -20 3 10 © IMEC 2000
4
10
5
10
6
7
10 10 10 frequency [Hz]
8
9
10
10
10
Experimental ASICs to verify the lowlevel SPICE substrate models AuE 0.5um CMOS, 3.3 V test chip with noise generators
AuE 0.5um CMOS, 3.3V 86kgate ASIC DIGITAL MULTIRATE UP/DOWN CONVERTER
power region 1 power region 2
ANALOG NOISE SENSORS
© IMEC 2000
DIGITAL NOISE GENERATORS
ANALOG NOISE SENSORS
Clocked ring oscillator used for substrate noise generation
7x D
Q
CLK 4 or 6 x
© IMEC 2000
4 or 6 x
4 or 6 x
Dominant substrate noise source determines the noise waveform Vsub [mV]
Noise coupling from source/drain nodes
6
0
-6
0
Vsub [mV]
10
time [ns]
20
30
Noise coupling from the on-chip power/ground
50
0
-50 0 © IMEC 2000
10
time [ns]
20
30
Good agreement between measured and simulated substrate noise Vsub [mV] 25
measurement SPICE
20 15 10 5 0 -5 -10 -15 0
5
10
15 time [ns]
© IMEC 2000
20
25
30
>80% of noise power is generated by simultaneous switching of core cells Vsub [mV] 40
20
0
-20 core switching
output switching
-40 20
20.1
20.2
20.3 time [us]
© IMEC 2000
20.4
20.5
Substrate noise power scales as CMOS power consumption : Vsub2 ~ f Vdd2
Vsub [mVrms] at Vdd=3.3V
25
100
Vsub [mVrms] at Fclk = 50 MHz linear
20
slope 0.5
15
10
10 1 0.1
5 1
10 Fclk [MHz]
© IMEC 2000
100
2
2.5
3
3.5 Vdd [V]
4
4.5
Frequency spectrum of generated substrate noise
MOSFETs
© IMEC 2000
power supply
Increase of substrate noise at clock multiples and due to ringing Vsub [dBV] data input clock
data output clock
-40
+40 dB at clock multiples
+20 dB from ringing
-60
-80
-100
0
50
ringing © IMEC 2000
100 Freq [MHz]
150
200
Conclusions from the measurements • in most practical cases, substrate noise is caused by power supply noise coupling • simultaneous switching of core cells (mostly flipflops) generate more noise than IO buffers • ringing of the power supply will increase the substrate noise • in the frequency domain, substrate noise is concentrated at multiples of the digital clock frequency, with peaks up to 40 dB above the substrate noise floor © IMEC 2000
Conclusions on modeling • when modeling and simulating substrate noise generation all noise sources should be taken into account: • switching gates • power supply noise • package parasitics
• for epi-type substrates a simple SPICE substrate model can be used
© IMEC 2000
Related work and References • Related work: High-level modeling and simulation of digital substrate noise generation • BANDIT project (see HTTP://www.imec.be/bandit/)
• References: • M. van Heijningen, J. Compiet, P. Wambacq, S. Donnay, M. Engels, and I. Bolsens, "Analysis and Experimental Verification of Digital Substrate Noise Generation for Epi-Type Substrates," IEEE J. Solid-State Circuits, vol. 35, pp. 1002-1008, July 2000. • M. van Heijningen, M. Badaroglu, S. Donnay, M. Engels, and I. Bolsens, "High-Level Simulation of Substrate Noise Generation Including Power Supply Noise Coupling," in Proc. 37nd Design Automation Conference, pp. 446-451, 2000. • Y. Rolain, W. van Moer, G. Vandersteen, and M. van Heijningen, "Measuring mixed signal substrate coupling," in Proc. IMTC'2000, Baltimore, May, 2000. • M. van Heijningen, J. Compiet, P. Wambacq, S. Donnay, M. Engels, and I. Bolsens, "Modeling of Digital Substrate Noise Generation and Experimental Verification Using a Novel Substrate Noise Sensor," in Proceedings of the ESSCIRC, pp. 186-189, 1999. • M. van Heijningen, J. Compiet, P. Wambacq, S. Donnay, and I. Bolsens, "A Design Experiment for Measurement of the Spectral Content of Substrate Noise in Mixed-Signal Integrated Circuits," in Proc. 1999 Southwest Symposium on Mixed-Signal Design, April 11-13, Tucson AZ, USA, pp. 27-32, 1999.
© IMEC 2000
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