Dem V Sem.pdf

Government Polytechnic, Muzaffarpur Name of the Lab: Digital Electronics & M.P. Lab Subject Code: 1621507

Operation of Mono stable multivibrator circuit Aim of experiment: To design and simulate a Monostable Multivibrator circuit. Components

Name

EDWin Components Used

Description

Number of components required

BC107

BC107A

Transistor

2

RES

RC05

Resistor

6

CAP

CASE-A600

Capacitor

2

DIODE

1N4007

Diode

1

VDC

SMB_VDC

Dc voltage source

2

VGEN

SMB_VGEN

Ac Voltage Source

1

GND

SMB_SPL0

Ground

3

Theory A multivibrator in which one transistor is always conducting (i.e. in the ON state) and the other is non-conducting (i.e. in the OFF state) is called a monostable

multivibrator. Monostable Multivibrator or one-shot multivibrator has one stable state and one quasi-stable state. i.e. When one transistor is conducting and the other is nonconducting, the circuit will remain in this stable state until the application of external trigger pulse. After a certain time the circuit will automatically switch back to the original stable state and remains there until another pulse is applied. The circuit of a transistor monostable multivibrator is shown in the figure. With the above circuit arrangement Q1 is at cut-off and Q2 is at saturation. This represents the stable state. The base of Q1 is kept at a negative potential to ensure that it is always OFF unless when trigger is applied. The triggering network consists of the voltage source, the input capacitor, R4, R5 and D1.

When a trigger pulse is applied, Q1 turns ON and the collector voltage of Q1 drops from VCC to the saturation voltage of 0.2V. This negative change is coupled to the base of Q2 by the capacitor which inturn causes Q2 to turn OFF. This represents the quasi-stable state. Now the capacitor starts charging towards VCC. When the capacitor voltage reaches 0.7V, transistor Q2 turns ON and Q1 switches back to the OFF state.

Procedure EDWin 2000 -> Schematic Editor: The circuit diagram is drawn by loading components from the library. Wiring and proper net assignment has been made. The values are assigned for relevant components.

EDWin 2000 -> Mixed Mode Simulator: The circuit is preprocessed. The desired test points and waveform markers are placed. The Transient Analysis parameters have been set. The Transient Analysis is executed and output observed in Waveform Viewer. Result The output waveform may be observed in the waveform viewer.

Government Polytechnic, Muzaffarpur Name of the Lab: Digital Electronics & M.P. Lab Subject Code: 1621507

Operation of Bi stable multivibrator circuit. 1. Aim of experiment To Design a Bi stable Multivibrator & observe its response.

2. Apparatus: 1. 2. 3. 4. 5. 6. 7. 8. 9.

CRO 0 to 20 MHz (Dual channel) Function generator 1Hz to 1 MHz Capacitor (0.001 F, 0.33 F) Resistors (1 k , 10k , 100K ) Transistor (BC 107) Diode (IN4007) Regulated Power supply 0 – 30 V(dual ) Connecting wires Bread board

3. Circuit diagram:

1No. 1No. 2 Nos each. 2 Nos each. 2 No. each. 4 No. each. 1 No.

4. Theory: A Bi stable circuit is one which can exist indefinitely in either of two stable states and which can be induced to make an abrupt transition from one state to the other by means of external excitation. The Bi stable circuit is also called as Bi stable multivibrator, Eccles Jordon circuit, Trigger circuit, Scale-of-2 toggle circuit, Flip-Flop & Binary. A Bi stable multivibratior is used in a many digital operations such as counting and the storing of binary information. It is also used in the generation and processing of pulse-type waveform. They can be used to control digital circuits and as frequency dividers. There are two outputs available which are complements of one another. i.e. when one output is high the other is low and vice versa .

5. Operation: When VCC is applied, one transistor will start conducting slightly more than that of the other, because of some differences in the characteristics of a transistor. Let Q2 be ON and Q1 be OFF. When Q2 is ON, The potential at the collector of Q2 decreases, which in turn will decrease the potential at the base of Q1 due to potential divider action of R1 and R2. The potential at the collector of Q1 increases which in turn further increases the base to emitter voltage at the base of Q2. The voltage at the collector of Q2 further decreases, which in turn further reduces the voltage at the base of Q1. This action will continue till Q2 becomes fully saturated and Q1 becomes fully cutoff. Thus the stable state of binary is such that one device remains in cut-off and other device remains at saturation. It will be in that state until the triggering pulse is applied to it. It has two stable states. For every transition of states triggering is required. At a time only one device will be conducting.

6. NEED OF COMMUTATING CAPACITORS (SPEED UP CAPACITORS): It is desired that the transition should take place as soon as the trigger pulse is applied but such is not the case. When transistor is in active region it stores charge in its base and when it is in the saturation region it stores even more charge. Hence transistor cannot come out of saturation to cut- off. Until all such charges are removed. The interval during which conduction transfer one transistor to other is called as the transition

7. Design Procedure:

-1.2 = (-15R1 + 0.2R2) /(R1 + R2) ; given R1=10K

R2 = 100K Fmax = (R1 + R2)/2C R1 R2

R1 = 10K , R2 = 100K and C = 0.1µF

= (10 + 100) X 103 / (2 X 0.3 X 10-6 X 10 X 100 X 106) = 55KHz 8. Procedure: 1. 2. 3. 4.

Make the connections as per the circuit diagram. Apply trigger pulse of 1 KHz 5v (p-p) from function generator. Obtain waveforms at different points such as VB1, VB2, VC1 & VC2. Trace the waveform at collector and base of each transistor with the help of dual trace CRO. Note the Time relation of waveforms.

9. Expected Waveforms:

Inference: Bi stable Multivibrator is designed; and the waveforms are observed

Government Polytechnic, Muzaffarpur Name of the Lab: Digital Electronics & M.P. Lab Subject Code: 1621507 Operation of Astable multivibrator circuit. 1. Aim of experiment To Design a Bi stable Multivibrator & observe its response.

Apparatus: 1. 2. 3. 4. 5. 6. 7. 8. 9.

CRO 0 to 20 MHz (Dual Channel) Function Generator 1Hz to 1 MHz Bread board Resistor (1K , 10K ) Capacitors (0.1µF) Transistor (BC 107) Regulated D.C Power Supply 0 to 30V Connecting wires Bread board

Circuit diagram:

Fig. 1.1 Astable Multivibrator

-

(dual)

1 No. 1 No. 1 No. 2 Nos. each 2 No.’s 2 No.’s 1 No.

Theory: The Astable circuit has two quasi-stable states. Without external triggering signal the Astable configuration will make successive transitions from one quasi-stable state to the other. The Astable circuit is an oscillator. It is also called as free running multivibrator and is used to generate “Square Wave”. Since it does not require triggering signal, fast switching is possible. Operation: When the power is applied, due to some imbalance in the circuit, the transistor Q2 conducts more than Q1 i.e. current flowing through transistor Q2 is more than the current flowing in transistor Q1. The voltage VC2 drops. This drop is coupled by the capacitor C1 to the base by Q1 there by reducing its forward base-emitter voltage and causing Q1 to conduct less. As the current through Q1 decreases, VC1 rises. This rise is coupled by the capacitor C2 to the base of Q2. There by increasing its base- emitter forward bias. This Q2 conducts more and more and Q1 conducts less and less, each action reinforcing the other. Ultimately Q2 gets saturated and becomes fully ON and Q1 becomes OFF. During this time C1 has been charging towards VCC exponentially with a time constant T1 = R1C1. The polarity of C1 should be such that it should supply voltage to the base of Q1. When C1 gains sufficient voltage, it drives Q1 ON. Then VC1 decreases and makes Q2 OFF. VC2 increases and makes Q1 fully saturated. During this time C2 has been charging through VCC, R2, C2 and Q2 with a time constant T2 = R2C2. The polarity of C2 should be such that it should supply voltage to the base of Q2. When C2 gains sufficient voltage, it drives Q2 On, and the process repeats. Design Procedure: The period T is given by T = T1 + T2 = 0.69 (R1C1 + R2C2) For symmetrical circuit, with R1 = R2 = R & C1 = C2 = C T = 1.38 RC Let VCC = 12V; hfe = 51 (for BC107), VBESat = 0.7V; VCESat = 0.3V Let C = 0.1 F & T = 1mSec. 10-3 = 1.38 x R X 0.1 X 10-6 R = 7.24K

(Practically choose 10K ) i.e., R1 and R2 resistors.

Let ICmax=10mA RC =

= 1.17K

( 1K

is selected for Rc1 and Rc2)

Procedure: 1. Make then connections as per the circuit diagram. 2. Observe the Base Voltage and Collector Voltages of Q1 & Q2 on CRO in DC mode and measure the frequency (f = 1/T). 3. Trace the waveforms at collector and base as each transistor with the help of dual trace CRO and plot the waveforms.

4. Verify the practical output frequency with theoretical values f = 1/T, where T = 1.38 RC

Expected Waveforms:

Theoretical calculations: F = 1/ T = (1/1.38RC) R = 10K

C = 0.1 F

Result: An Astable Multivibrator is designed; the waveforms are observed and verified the results theoretically.

Government Polytechnic, Muzaffarpur Name of the Lab: Digital Electronics & M.P. Lab. Subject Code: 1621507 Operation of Schmitt trigger circuit Aim of experiment Aim is to study the working of a schmitt trigger

Schmitt Trigger or Regenerative Comparator Circuit A Schmitt trigger circuit is also called a regenerative comparator circuit. The circuit is designed with a positive feedback and hence will have a regenerative action which will make the output switch levels. Also, the use of positive voltage feedback instead of a negative feedback, aids the feedback voltage to the input voltage, instead of opposing it. The use of a regenerative circuit is to remove the difficulties in a zero-crossing detector circuit due to low frequency signals and input noise voltages. Shown below is the circuit diagram of a Schmitt trigger. It is basically an inverting comparator circuit with a positive feedback. The purpose of the Schmitt trigger is to convert any regular or irregular shaped input waveform into a square wave output voltage or pulse. Thus, it can also be called a squaring circuit.

Schmitt Trigger Circuit Using Op-Amp uA741 IC

As shown in the circuit diagram, a voltage divider with resistors Rdiv1 and Rdiv2 is set in the positive feedback of the 741 IC op-amp. The same values of Rdiv1 and Rdiv2 are used to get the resistance value Rpar = Rdiv1||Rdiv2 which is connected in series with the input voltage. Rpar is used to minimize the offset problems. The voltage across R1 is fedback to the non-inverting input. The input voltage Vi triggers or changes the state of output Vout every time it exceeds its voltage levels above a certain threshold value called Upper Threshold Voltage (Vupt) and Lower Threshold Voltage (Vlpt). Let us assume that the inverting input voltage has a slight positive value. This will cause a negative value in the output. This negative voltage is fedback to the non-inverting terminal (+) of the op-amp through the voltage divider. Thus, the value of the negative voltage that is fedback to the positive terminal becomes higher. The value of the negative voltage becomes again higher until the circuit is driven into negative saturation (-Vsat). Now, let us assume that the inverting input voltage has a slight negative value. This will cause a positive value in the output. This positive voltage is fedback to the non-inverting terminal (+) of the op-amp through the voltage divider. Thus, the value of the positive voltage that is fedback to the positive terminal becomes higher. The value of the positive voltage becomes again higher until the circuit is driven into positive saturation (+Vsat). This is why the circuit is also named a regenerative comparator circuit.

Schmitt Trigger Input and Output Waveform When Vout = +Vsat, the voltage across Rdiv1 is called Upper Threshold Voltage (Vupt). The input voltage, Vin must be slightly more positive than Vupt inorder to cause the output Vo to

switch from +Vsat to -Vsat. When the input voltage is less than Vupt, the output voltage Vout is at +Vsat. Upper Threshold Voltage, Vupt = +Vsat (Rdiv1/[Rdiv1+Rdiv2]) When Vout = -Vsat, the voltage across Rdiv1 is called Lower Threshold Voltage (Vlpt). The input voltage, Vin must be slightly more negaitive than Vlpt inorder to cause the output Vo to switch from -Vsat to +Vsat. When the input voltage is less than Vlpt, the output voltage Vout is at -Vsat. Lower Threshold Voltage, Vlpt = -Vsat (Rdiv1/[Rdiv1+Rdiv2]) If the value of Vupt and Vlpt are higher than the input noise voltage, the positive feedback will eliminate the false output transitions. With the help of positive feedback and its regenerative behaviour, the output voltage will switch fast between the positive and negative saturation voltages. Hysteresis Characteristics Since a comparator circuit with a positive feedback is used, a dead band condition hysteresis can occur in the output. When the input of the comparator has a value higher than Vupt, its output switches from +Vsat to -Vsat and reverts back to its original state, +Vsat, when the input value goes below Vlpt. This is shown in the figure below. The hysteresis voltage can be calculated as the difference between the upper and lower threshold voltages. Vhysteresis = Vupt – Vlpt Subsituting the values of Vupt and Vlpt from the above equations: Vhysteresis = +Vsat (Rdiv1/Rdiv1+Rdiv2) – {-Vsat (Rdiv1/Rdiv1+Rdiv2)} Vhysteresis = (Rdiv1/Rdiv1+Rdiv2) {+Vsat – (-Vsat)}

Schmitt-Trigger-Hysteresis Characteristics Applications of Schmitt Trigger Schmitt trigger is mostly used to convert a very slowly varying input voltage into an output having abruptly varying waveform occurring precisely at certain predetermined value of input voltage. Schmitt trigger may be used for all applications for which a general comparator is used. Any type of input voltage can be converted into its corresponding square signal wave. The only condition is that the input signal must have large enough excursion to carry the input voltage beyond the limits of the hysteresis range. The amplitude of the square wave is independent of the peak-to-peak value of the input waveform.

Government Polytechnic, Muzaffarpur Name of the Lab: Digital Electronics & M.P. Lab Subject Code: 1621507 An op-amp comparator circuit

Aim of experiment To observe the performance of an op-amp comparator circuit. Equipment required: +/- 12 volt power supply unit Oscilloscope DVM Function Generator Test Leads Theory: A comparator is a circuit that performs a comparison between two voltages (V1 and V2) and provides an output that indicates which of the two voltages is greater by switching its output either high (if V1 > V2) or low (if V1 < V2). An operational amplifier may be used to perform this function. +V + Vo ut V1

V2

-V

Figure 1 The op amp gives: Vout AOL . V1 V2 If V1>V2, Vout will swing up to the positive output saturation voltage +VSAT (+VSAT +V).

If V2>V1 , Vout will swing down to the negative output saturation voltage -VSAT (-VSAT - V). Thus for any values of V1 and V2 (except V1 = V2), Vout will go to either +VSAT (high) or –VSAT (low). High or low values for Vout may be used as a signal to show that either V1>V2 or V1
+V R1 + Vout V1

V2

-V

Figure 2 This circuit will switch the output low if V1 falls below a threshold voltage: R1 R2 VTHL .V2 R1 .VSAT R2 R2 and the circuit will switch the output high if V1 rises above a threshold voltage: R1 R2 VTHU .V2 R1 .VSAT R R 2 2 (Note that if R2 is open circuit (R2 = ) VTHU = VTHL = V2.) Procedure: 1. Build the circuit in figure 1 and with V2 = 5 volts, +V = 12 volts, -V = -12 volts. 2. Plot VOUT as a function of V1 and comment on your results. 3. Build the circuit in figure 2 with R1 = 1k, R2 = 10k,V2 = 5 volts, +V = 12 volts, -V = - 12 volts. 4. Plot VOUT as a function of V1 and comment on your results. 5. Connect V1 = 10 volt peak sine wave at 1 kHz with other voltages as before. 6. Measure both V1 and VOUT on an oscilloscope and sketch both waveforms to scale. Comment on the relationship between the two signals.

Government Polytechnic, Muzaffarpur Name of the Lab: Digital Electronics & M.P. Lab Subject Code: 1621507 Operation of Integrator circuit. Aim: different input To design and simulate an Integrator circuit and observe output with waveforms .

Components required: Function generator, CRO, Regulated Power supply, resistor, capacitor, 741 IC, connecting wires. Vlab Specifications Taken:

Integrator circuit design has been implemented on the virtual breadboard using following specifications:  Power Supply: +10v and -10v  Function generator: Selected wave with following specifications:  Frequency=50Hz,55Hz,60Hz,100Hz. Amplitude:2V Duty cycle = 50%  Capacitor C: 1000nF  Resistor R1: 1.369K

Theory: The circuit in fig 1 is an integrator, which is also a low-pass filter with a time constant=R1C. When a voltage, Vin is firstly applied to the input of an integrating amplifier, the uncharged capacitor C has very little resistance and acts a bit like a short circuit (voltage follower circuit) giving an overall gain of less than 1, thus resulting in zero output. As the feedback capacitor C begins to charge up, its reactance Xc decreases and the ratio of Zf/R1 increases producing an output voltage that continues to increase until the capacitor is fully charged. At this point the ratio of feedback capacitor to input resistor (Zf/R1) is infinite resulting in infinite gain and the output of the amplifier goes into saturation. (Saturation is when the output voltage of the amplifier swings heavily to one voltage supply rail or the other with no control in between). The

circuit design generate triangular wave providing square wave as input to the integrator. Hence, the integrator circuit generates integral output with respect to the input waveform.

The integrator Circuit

Procedure: 1.

2. 3. 4. 5.

Connect the circuit as shown in the circuit diagram. Give the input signal as specified. Switch on the power supply. Note down the outputs from the CRO Draw the necessary waveforms on the graph sheet.

Observations: 1. Observe the output waveform from CRO. A square wave will generate a triangular wave and sine wave will generate a cosine wave. 2. Measure the frequency and the voltage of the output waveform in the CRO. 3. Calculate

4. 5.

Compare the calculated output voltage with the experimentally observed voltage from the output waveform. Observe outputs of the integrator circuit using different input waveforms.

VLab Observations Obtained: For example, a case has been taken and the required parameters values is being noted down below: 1. Input Voltage: 2.09V 2. Frequency: 50Hz 3. Output Voltage: 4.31V 4. Phase Difference: -92

Calculations: If input Vin = 2.09 sin (2*50*t) Output of the integrator will be equal to

Thus,

Hence theoretically, output voltage should be 4.72V and phase difference between input outputs should be -90°. Experimentally phase difference observed is about 92 and output voltage 4.31V.

Result: The integrator circuit design output waveforms have been studied.

Precautions: 1.

2. 3.

Connections should be verified before clicking run button. The resistance to be chosen should be in Kohm range. Best performance is being obtained within 50Hz to 1Mhz.

Government Polytechnic, Muzaffarpur Name of the Lab: Digital Electronics & M.P. Lab Subject Code: 1621507

Operation of Blocking Oscillator circuit Aim: Aim is to study the working of a Blocking Oscillator circuit An oscillator is a circuit that provides an alternating voltage or current by its own, without any input applied. An Oscillator needs an amplifier and also a feedback from the output. The feedback provided should be regenerative feedback which along with the portion of the output signal, contains a component in the output signal, which is in phase with the input signal. An oscillator that uses a regenerative feedback to generate a nonsinusoidal output is called as Relaxation Oscillator. We have already seen UJT relaxation oscillator. Another type of relaxation oscillator is the Blocking oscillator.

Blocking Oscillator A blocking oscillator is a waveform generator that is used to produce narrow pulses or trigger pulses. While having the feedback from the output signal, it blocks the feedback, after a cycle, for certain predetermined time. This feature of blocking the output while being an oscillator, gets the name blocking oscillator to it. In the construction of a blocking oscillator, the transistor is used as an amplifier and the transformer is used for feedback. The transformer used here is a Pulse transformer. The symbol of a pulse transformer is as shown below.

Pulse Transformer A Pulse transformer is one which couples a source of rectangular pulses of electrical energy to the load. Keeping the shape and other properties of pulses unchanged. They are wide band transformers with minimum attenuationand zero or minimum phase change. The output of the transformer depends upon the charge and discharge of the capacitor connected. The regenerative feedback is made easy by using pulse transformer. The output can be fed back to the input in the same phase by properly choosing the winding polarities of the pulse transformer. Blocking oscillator is such a free-running oscillator made using a capacitor and a pulse transformer along with a single transistor which is cut off for most of the duty cycle producing periodic pulses. Using the blocking oscillator, Astable and Monostable operations are possible. But Bistable operation is not possible. Let us go through them.

Monostable Blocking Oscillator If the blocking oscillator needs a single pulse, to change its state, it is called as a Monostable blocking oscillator circuit. These Monostable blocking oscillators can be of two types. They are 

Monostable blocking oscillator with base timing



Monostable blocking oscillator with emitter timing

In both of these, a timing resistor R controls the gate width, which when placed in the base of transistor becomes base timing circuit and when placed in the emitter of transistor becomes emitter timing circuit. To have a clear understanding, let us discuss the working of base timing Monostable Multivibrator.

Transistor Triggered Monostable blocking oscillator with Base timing A transistor, a pulse transformer for feedback and a resistor in the base of the transistor constitute the circuit of a transistor triggered Monostable blocking oscillator with base timing. The pulse transformer used here has a turns ratio of n: 1 where the base circuit has n turns for every turn on the collector circuit. A resistance R is connected in series to the base of the transistor which controls the pulse duration. Initially the transistor is in OFF condition. As shown in the following figure, VBB is considered zero or too low, which is negligible.

The voltage at the collector is VCC, since the device is OFF. But when a negative trigger is applied at the collector, the voltage gets reduced. Because of the winding polarities of the transformer, the collector voltage goes down, while the base voltage rises. When the base to emitter voltage becomes greater than the cut-in voltage, i.e. VBE>VγVBE>Vγ Then, a small base current is observed. This raises the collector current which decreases the collector voltage. This action cumulates further, which increases the collector current and

decreases the collector voltage further. With the regenerative feedback action, if the loop gain increases, the transistor gets into saturation quickly. But this is not a stable state. Then, a small base current is observed. This raises the collector current which decreases the collector voltage. This action cumulates further, which increases the collector current and decreases the collector voltage further. With the regenerative feedback action, if the loop gain increases, the transistor gets into saturation quickly. But this is not a stable state. When the transistor gets into saturation, the collector current increases and the base current is constant. Now, the collector current slowly starts charging the capacitor and the voltage at the transformer reduces. Due to the transformer winding polarities, the base voltage gets increased. This in turn decreases the base current. This cumulative action, throws the transistor into cut off condition, which is the stable state of the circuit. The output waveforms are as follows −

The main disadvantage of this circuit is that the output Pulse width cannot be maintained stable. We know that the collector current is ic=hFEiBic=hFEiB As the hFE is temperature dependent and the pulse width varies linearly with this, the output pulse width cannot be stable. Also hFE varies with the transistor used. Anyways, this disadvantage can be eliminated if the resistor is placed in emitter, which means the solution is the emitter timing circuit. When the above condition occurs, the transistor turns OFF in the emitter timing circuit and so a stable output is obtained.

Astable Blocking Oscillator If the blocking oscillator can change its state automatically, it is called as an Astable blocking oscillator circuit. These Astable blocking oscillators can be of two types. They are 

Diode controlled Astable blocking oscillator



RC controlled Astable blocking oscillator

In diode controlled Astable blocking oscillator, a diode placed in the collector changes the state of the blocking oscillator. While in the RC controlled Astable blocking oscillator, a timing resistor R and capacitor C form a network in the emitter section to control the pulse timings. To have a clear understanding, let us discuss the working of Diode controlled Astable blocking oscillator.

Diode controlled Astable blocking oscillator The diode controlled Astable blocking oscillator contains a pulse transformer in the collector circuit. A capacitor is connected in between transformer secondary and the base of the transistor. The transformer primary and the diode are connected in the collector. An initial pulse is given at the collector of the transistor to initiate the process and from there no pulses are required and the circuit behaves as an Astable Multivibrator. The figure below shows the circuit of a diode controlled Astable blocking oscillator.

Initially the transistor is in OFF state. To initiate the circuit, a negative trigger pulse is applied at the collector. The diode whose anode is connected to the collector, will be in reverse biased condition and will be OFF by the application of this negative trigger pulse. This pulse is applied to the pulse transformer and due to the winding polarities (as indicated in the figure), same amount of voltage gets induced without any phase inversion. This voltage flows through the capacitor towards the base, contributing some base current. This base current,

develops some base to emitter voltage, which when crosses the cut-in voltage, pushes the transistor Q1 to ON. Now, the collector current of the transistor Q1 raises and it gets applied to both the diode and the transformer. The diode which is initially OFF gets ON now. The voltage that gets induced into the transformer primary windings induces some voltage into the transformer secondary winding, using which the capacitor starts charging. As the capacitor will not deliver any current while it is getting charged, the base current iB stops flowing. This turns the transistor Q1 OFF. Hence the state is changed. Now, the diode which was ON, has some voltage across it, which gets applied to the transformer primary, which is induced into the secondary. Now, the current flows through the capacitor which lets the capacitor discharge. Hence the base current iB flows turning the transistor ON again. The output waveforms are as shown below.

As the diode helps the transistor to change its state, this circuit is diode controlled. Also, as the trigger pulse is applied only at the time of initiation, whereas the circuit keeps on changing its state all by its own, this circuit is an Astable oscillator. Hence the name diode controlled Astable blocking oscillator is given. Another type of circuit uses R and C combination in the emitter portion of the transistor and it is called as RC controlled Astable blocking oscillator circuit.

Government Polytechnic, Muzaffarpur Name of the Lab: Digital Electronics & M.P. Lab Subject Code: 1621507

Operation of Shift registers and counters.

Aim of experiment: Aim is to study the Shift registers and counters.

Introduction Shift registers are specialized memory systems composed of flip-flops or other types of memory cells. The distinguishing feature of shift registers is that data can be transferred on command from one cell to the adjacent memory cell as many times as needed. The simplest shift registers will transfer one data bit in for each clock cycle until the register capacity is reached. At this time the register contents may be sampled. More complex registers will allow direct sampling of each output stage so that the register contents can be examined on each clock cycle. Other registers allow parallel loading where the entire register is loaded at once. A special type of shift register known as the universal shift register will shift entries left or right, and input or output data serially or parallel. Shift registers may be constructed from either J-K flip-flops as shown in Figure.6.1 or from D flip-flops as shown in Figure.6.2.

Parallel output Serial input J

Q

CLK

J

Q

CLK Q

K

J

Q

CLK Q

K

Q

Clock

Figure.6.1. J-K flip-flop Shift Register

Serial output

Serial input

Serial output D

Q

D

CLK

CLK

Q

D

Q

CLK

Clock

Figure.6.2. D flip-flop Shift Register The single data input of the shift register in Figure.6.1 is known as a single rail input. If the J and K inputs are used as separate data inputs then the shift register is said to have a dual rail input. Likewise if the shift register uses both the true and complement outputs the circuit is called a dual rail output circuit. Of course if only one of the outputs is used then the circuit is described as having a single rail output. Note that the output of the J-K shift register shown can be either serial or parallel. Shift registers can be classified as : a. Serial-in/serial-out b. Serial-in/parallel-out c. Parallel-in/serial-out d. Parallel-in/parallel-out

: SISO : SIPO : PISO : PIPO

All parallel input registers can be operated as serial input registers and the same is true for output. The reverse situation is not true in that serial input registers cannot be operated as parallel input registers.

Johnson Counter : Shift registers can be used to form a special kind of counter known as a ring counter. A ring counter works by loading a binary ONE into the input flip-flop of a shift register and tying the register output to the input. When the register is clocked the ONE will move through the register one cell at a time. After a number of clock pulses equal to the number of cells in the register, the ONE will circuit back to the input flip-flop. This allows a form of counting. This type of counter uses more flip-flops than required to perform the count. For example, three flip-flops configured as a ring counter can have only three states or counts while a binary counter with three flip-flops can count eight states when properly decoded. The advantage of the ring counter is that no decoding is required to determine the count. The ring counter has 2N-N disallowed states where that N is the number of flip-flops. A special type of ring counter is the Johnson counter. The Johnson counter has the output inverted before it is fed back into the input so that the maximum count is 2·N with N being the number of flip-flops. This, of course means that the

Johnson counter has (2N)-(2 · N) disallowed states. The Johnson counter makes better use of the flip-flops than a simple ring counter and it also can be decoded by using a two-input AND for each decoded output. Schematic for a 3-flip-flop Johnson counter is shown in Figure.6.3.

Q1 D

Q2

Q

CLK

D CLK

Q1' Q

Q3

Q

D

Q2' Q

Q

CLK

Q3' Q

Clock

Figure.6.3. Johnson counter

Exercises 2.1. Objective The purpose of this lab is to investigate shift registers. We will implement shift register and johnson counter using discrete flip-flop ICs..

2.2. Materials 2x74LS74 Dual D-Type Positive Edge-Triggered Flip-Flop 1x74LS174 Hex D Flip-Flop 2x74LS08 Quadruple 2 Input Positive AND Gate 1x74LS32 Quadruple 2 Input Positive OR Gate

2.3. Procedure 1. Set up the circuit shown in Figure.6.4. led1

switch2 (serial input)

2 3

D

Q

5

led2

12 11

CLK

D

Q

9

led3

2 3

CLK

CL

CL

6

Q

8

D

Q

5

led4

12 11

CLK

CL

Q

Q

6

D

Q

9

CLK

CL

Q

8

1

7

1

7

switch1 (reset) PB2 Clock

2. 3. 4. 5.

Figure.6.4. Shift Register Turn on power. Turn switch1 to logic-1 position.. Use switch2 as the input bit, PB2 as the clock input and Led1-Led4 as the output. Reset the outputs of the register using switch1. Fill in the following table.

Serial input (Switch2)

Reset input (Switch1)

x

0

Clock pulse (PB2)

Led1

Led2

Led3

Led4

1

1

0

1

1

1

1

1

x = Don't care. 6. Connect the complement output of the fourth flip-flop to the input of the first flip-flop. This counter is called Johnson counter. 7. Reset the outputs of the counter. 8. Rotate the single bit with the shift condition. Observe and record the state of the register after each clock pulse. 9. Some additional circuitry will be required to allow us to use the 74174 as a parallel loading shift register. Set up the circuit shown in Figure.6.5. 10. Connect inputs A, B, and C to the switch1, switch2, and switch3, respectively. 11. Turn switch1-switch3 to logic-0 position. Turn on power. 12. Use A, B, and C as the parallel inputs, switch8 as the load enable input, PB2 as the clock input and Led1-Led3 as the parallel outputs. Observe the operation of this circuit and record your observations. Notice that to load the parallel data you must turn switch8 to logic-1 position. 13. Leave the circuit.

A

1 3

3 4 6 11 13 14

2 74LS08#2

9 1 1 3 1 3 2

B

74LS32

4 6 5 74LS08#1

9 8 10

PB2 (Clock)

1

74LS08#1

3 2

12

switch8

switch7

11

C

CLK CLR 74174

2 74LS08#1

D1 D2 D3 D4 D5 D6

74LS32

13 74LS08#1

Figure.6.5 PIPO Shift Register

Q1 Q2 Q3 Q4 Q5 Q6

2 5 7 10 12 15

Led1 Led2 Led3

Government Polytechnic, Muzaffarpur Name of the Lab: Digital Electronics & M.P. Lab Subject Code: 1621507

Operation of EPROM eraser. Aim of experiment Aim is to study the EPROM eraser.

Introduction - Ultraviolet Light The invisible band of radiation just beyond the violet end of the visible spectrum is called ultraviolet light. That spectrum includes the wavelength that is instrumental in erasing EPROMs: 253.7nm, frequently referred to as approximately 254nm or 2537 Angstrom. The radiant incidence of this energy at the location of the EPROM is a function of the distance between the light source and the EPROM and the geometry of the light source. The DE-50 EPROM Erasing System design optimizes these elements to give the best possible performance.

Design Features The DE-50 EPROM Erasing System is designed to provide safe tools for exposure of EPROMs to shortwave ultraviolet radiation. Features include: · · · · · · · ·

Superior reflectors that maximize UV output and distribution A 60 minute automatic shut-off timer A safety interlock prevents UV exposure to personnel PC board compatibility Long life, high intensity UV tubes for minimum erase times A viewport for each UV tube to observe tube operation A conductive foam pad to eliminate electrostatic build up A rugged metal housing

Specifications The DE-50 EPROM Eraser has the following specifications: Capacity: Size: cm)

50 EPROMs (24 pin type) 4.11 in. H (10.44 cm) x 11.70 in. W (29.72 cm) x 13.44 in. D(34.14

Drawer Depth: 1.375 in. (3.49 cm) Weight: 13.75 lbs (6.25 kg) Power: 100V, 50 Hz, 1 Amp 110V, 60 Hz, 1 Amp 230V, 50 Hz, 1 Amp

Operating Instructions Set-Up Procedures 1. Slide the tray out unit it stops. 2. Press the EPROMs to be erased down into the foam pad. As the radiant incidence is somewhat greater near the center than the edges, place the EPROMs more towards the center unless the full capacity of the unit is to be used. 3. Close the drawer all the way. (The unit has a safety interlock and will not operate if the drawer is open.) 4.

Plug in the unit and set the timer for the desired erase time. When the timer is set and the unit is in operation, the five view ports will glow green without emitting harmful shortwave radiation.

Erase Time and Exposure Considerations Erase time is inversely proportional to the radiant incidence from the lamp at the EPROM surface. Radiant incidence from the lamp at the EPROM surface varies with EPROM location in the unit and with lamp temperatures, running time and individual lamp differences. The following table lists recommended times to erase all EPROMs placed in a new unit. Most EPROMs require a dosage of 15 W-sec/cm2 for erasure. However, erasure requirements vary from 6 W-sec/cm2 to 25 W-sec/cm2. Check with the EPROM manufacturer for specific recommended dosages.

Model DE-50

Nominal # of Intensity 24 Pin μ W/cm2 EPROMs 12,000 1 - 50

Typical EPROM Erasure Time in Minutes 15 W-sec/cm2 5.9 *

Average erasure time for repeated tests of 50 Intel 2732A EPROMs with recommended erasure dosage of 15 W-sec/cm2.

Maintenance CAUTION: Do not attempt to operate this unit while it is plugged into the AC outlet. Failure to unplug the unit from the AC outlet before disassembly will result in an electrical shock hazard. WARNING: Do not attempt to operate this unit in the disassembled condition as that may expose the eyes and skin to shortwave UV light that is harmful to the unprotected eyes and skin! This unit is virtually maintenance free. If the lamp fails to start, check to see that: 1. The unit is plugged in. 2. The drawer is pushed all the way in (listen for the click of the limited switch). 3. The timer is on. 4. Check the fuse to see if they are operational. If a problem still exists, return the unit to the factory for inspection and repair. If the unit has been heavily used for a long time, it may be desirable to replace the lamp to reduce erase times to their original values. Tube Replacement Steps 1. Unplug the unit. 2. Use a Phillip’s screwdriver to remove back cover. 3. Remove drawer by sliding all the way out and then tilting upwards. 4. Using both hands, reach in each side of unit, grasp the tube and gently twist 90o (it does not matter which direction). Tube should easily slip out. 5. Slide new tube into the unit. Using both hands, gently push the replacement tube up and twist into place. 6. Replace unit back cover. 7. Replace drawer (be sure it is fully closed or safely shut-off will prevent unit operation). 8. Plug unit in and observe the viewport for that specific lamp to verify lamp operation.

Schematic Diagram The schematic diagram for DE-50 models is shown below.

Accessories UVX Radiometer Maximum efficiencies of all EPROM erasers rely on proper knowledge of lamp intensities. As with all mercury vapor discharge lamps, intensity decreases over time with use. Due to the general unpredictability of the rate of UV intensity decline, cumulative hour meters in EPROM erasers cannot accurately indicate lamp condition. Use of a shortwave ultraviolet measuring device is therefore the most effective method of determining proper erasure time and monitoring useful life of any UV source. The UVX Radiometer equipped with a UVX-25 Sensor is such a state-of-the-art measuring device. Ideal for obtaining accurate UV irradiance measurements, the UVX is calibrated to NIST standards to assure accuracy of readings. Built to withstand day-to-day use in a production environment, the UVX delivers the needed measurements to assure accurate erasure time calculations.

Government Polytechnic, Muzaffarpur Name of the Lab: Digital Electronics & M.P. Lab Subject Code: 1621507 Name of the Lab: Operation of Multiplexers ICs Aim:- Implementation of 4x1 multiplexer, using logic gates. Objective: Learn to convert word statement in logical equation. Learn to simplify the logical equation Learn to convert the simplified equation in logic circuit and implement and verify the design Theory:MULTIPLEXER:b> A multiplexer (MUX) is a many to one device. It allows input from many different sources to be transmitted to a common destination. The destination to which a particular source connects depends on the select/ control lines. Thus MUX is a device that accepts data from one of many input sources for transmission over a common shared line.

To achieve this MUX has several data lines and a single output along with data-select inputs, which permit digital data on any of the inputs to be switched to the output line. The logic symbol for a 1- to-4 data selector/multiplexer is shown in Figure

The truth table for a Multiplexer is given below:

The logic equation for the output can be written as: Output= I0.S1'.S0' + I1.S1'.S0 + I2.S1.S0' + I3.S1.S0 And the logic diagram for implementing the above equation is drawn below:

Apparatus Required: Digital trainer kit, AND-7411, OR-7432, NOT-7404 Gate IC, Connecting wires, LEDs, 220Ohm Resistor. PROCEDURE:1 . Connections are made as per circuit diagram. 2. Verify the truth table. 3. Also connect Vcc and Ground then performed experiment. Precautions:a. All ICs should be checked before starting the experiment. b. All the connection should be tight. c. Always connect ground first and then connect Vcc. d. Suitable type wire should be used for different types of circuit. e. The kit should be off before change the connections. f. After completed the experiments switch off the supply of the apparatus

Government Polytechnic, Muzaffarpur Name of the Lab: Operation of D/A converter Subject Code: 1621507

1. Aim of experiment Construction of digital-to-analogue converters using different techniques,

A.1. ADC0804 A/D Converter

ADC0804 is an 8-bit CMOS successive approximation register (SAR) A/D converter. It has 20 pins and its pin configuration is given in Fig. 4.1.

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Fig. 4.1

A.2. Functional Description The block diagram of ADC0804 is presented in Fig. 4.2 Conversion begins with the arrival of a pulse at the the High-to-Low transition of the signal at the shift register is reset, and the output is set high. A read ( ) operation (with latches.

low) will clear the

input if the input is low. On or the , the SAR is initialized; the line and enable the output

The analog signal to be converted into digital is applied between VIN(+) and VIN(-). This A/D converter has been designed to accommodate fixed reference voltages of 5V to Pin 20 or 2.5 V to Pin 9, or an adjusted reference voltage at Pin 9. The reference can be set by forcing it at VREF/2 input, or can be determined by the supply voltage (Pin 20). The clock may be applied diractly or an RC circuit added as given in Fig. 4.3 to use the internal timer.

Fig. 4.3 The period of oscillations is T = 2.2 RC or f = 1/(2.2 RC).

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B. Preliminary Work B. 1. Determine f if R = 1.5 k and C = 1 nF. B. 2. With 8-bit output resolution, how many levels can be represented? B. 3. What is the step size if 5 V is used as the reference voltage (VREF), what is this ADC’s step size? (The step size is the smallest analog input voltage that will produce a digital output code of 000 0001)

C. Experimental Work C. 1. Setup the circuit given in Fig. 4.4 with R = 1.5 k and C = 1 nF.

Fig. 4.4 C. 2. Set VREF/2 = 2.5 V and measure and plot the CLK IN signal at pin 6. What are the maximum and minimum voltage values? What is the frequency of the signal at pin 6? C. 3. Determine the digital output codes for the following analog input values. (Using Start Conversion switch, get the results of several conversions in order to be sure about the correct conversion)

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Output Digital Code

Analog Input Expected (V) Binary

Measured Decimal Binary

Decimal

0.02 0.05 0.1 0.2 0.5 0.75 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

C. 5. Now set VREF/2 = 2 V at pin 6 and determine the digital output codes for the following analog input values . (Using Start Conversion switch, get the results of several Conversions in order to be sure about the correct conversion). Analog Input (V)

Output Digital Code Expecte d Binary

Measure d Decimal

Binary

Decimal

0.02 0.05 0.1 0.2 0.5 0.75 1.0 1.5 2.0 2.5 40

3.0 3.5 4.0 4.5 5.0 C. 6. Comment of the findings you obtained in this experiment.

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Government Polytechnic, Muzaffarpur Digital Electronics & M.P. Lab Subject Code: 1621507

R-2R ladder network AIM: Operation of R-2R ladder network. EQUIPMENT REQUIRED: Components 1*LF351 OPAMP 5*20KΩ 15*10KΩ 4*switch THEORY: A digital to analog converter (DAC) converts a digital signal to an analog voltage or current output. Many types of DACs are available and usually switches, resistors, and op-amps are used to implement the conversion. In Figure 1, a summing amplifer with binary weighted resistors are given.

Figure 1. DAC by opamp summing amplifer with binary weighted resistors R-2R Ladder is another type of DAC based on the opamp summing amplifier similarly as seen in Figure 2. Each bit corresponds to a switch:

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If the bit is high, the corresponding switch is connected to the inverting input of the op-amp. If the bit is low, the corresponding switch is connected to ground. bn means Bit n, hence; If bit n is set, bn=1 If bit n is clear, bn=0 For a 4-Bit R-2R Ladder, output is equal to;

For general n-Bit R-2R Ladder , output is equal to;

EXPERIMENTAL PROCEDURE: 1) Construct the circuit in Figure 1 and fill in Table 1 (use 10k resistors in parallel configurations). 2) Construct the circuit in Figure 3 and fill in Table 2.

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Figure 3. R-2R ladder circuit to be constructed

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CONCLUSION: Compare ideal and experimental results. What is the rate of the difference? Explain its reasons.

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Government Polytechnic, Muzaffarpur Digital Electronics & M.P. Lab Subject Code: 1621507 Operation of Sample and Hold circuit. Aim: To study the different types of signal sampling and its reconstruction. Apparatus Required: 1. Sampling and its reconstruction Kit - DCL 01 2. Digital Storage Oscilloscope (DSO) 3. Power supply 4. Patch cords Procedure: 1. The connections are given as per the block diagram for natural sampling 2. Connect the power supply in proper polarity to the kit and & switch it on. 3. Using the clock selector switch select 8 KHz sampling frequency and using switch SW2 select 50% duty cycle. 4. The input and output waveforms are measured using DSO. 5. The procedure above is repeated for sample & hold and flat top sampling. Tabular Column:

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Fig. 1.1 Block Diagram for Natural Sampling

Fig. 1.2 Block Diagram for Sample and Hold

Fig. 1.3 Block Diagram for Flat Top Sampling MODEL GRAPH:

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Fig 1.4 Model Graph for Signal sampling and reconstruction using sample & hold.

Result: Comparing the reconstructed output of 2nd order Low Pass Butterworth filter for all three types of sampling , it is observed that the output of the sample and hold is the better when compared to the outputs of natural sampling and the flat top sampling.

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Government Polytechnic, Muzaffarpur Digital Electronics & M.P. Lab Subject Code: 1621507 Operation of A/D converter AIM: -Study of 8-bit monolithic Analog to digital converter. APPARATUS REQUIRED: - ST2601 with power supply cord, Connecting Cords THEORY: Successive approximation ADC uses one or a few comparators, operated iteratively, to yield high accuracy conversion with far fewer components than flash conversion. A/D converter using successive approximation technique effectively performs a binary search in a digital analog look up table and using a digital to analog converter (DAC) and comparator circuit. Successive approximation converters also allow higher resolutions but tend to be slower since they usually require N cycles to produce the answer. Successive approximation ADC operates at much slower conversion rates than flash ADC. Sub ranging analog to digital converters provide an intermediate compromise between flash ADCs and successive approximation ADCs. Sub ranging analog to digital converters typically use a low resolution flash quantizer during a first or coarse pass to convert the analog input signal into the most significant bits (MSB) of its digital value. A digital to analog converter (DAC) then generates an analog version of the MSB word. The residue signal is sent through one or more fine passes to produce the lower significant bits of the input signal. The lower significant bits and the MSB word are then combined by digital error correcting circuitry to produce the desired digital output word. A switched capacitor analog to digital converter (ADC) operated according to successive approximation register technique comprises a plurality of weighted capacitors with associated switches and a local DAC. The capacitors are charged by a voltage sample of an analog signal to be converted. The voltage sample is compared with an analog signal generated by the local DAC. CIRCUIT DIAGRAM:-

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PROCEDURE:1. Connect supply to the trainer. 2. Make the connections as shown in figure. a. Connect the USB/ BOB to GND. b. Connect the DC output to Vi of Monolithic converter. c. Keep the DC potentiometer in counterclockwise direction. d. Keep the Auto /Manual switch in Auto position. 3. Switch ON the power supply. 4. Vary the DC potentiometer and observe the corresponding digital output on LEDs. 5. Now keep the Auto /Manual switch in Manual position. 6. Keep the Blank / Convert switch in Blank position 7. Vary the DC potentiometer 8. Set the switch to convert position, The LEDs will light forming a digital word which corresponds to the digital conversion of the analog voltage applied to the input. 9. Perform the same procedure with different DC voltages. 10. Now, connect the USB / BOB terminal to +5V and bipolar o/p to Vi. This gives Output voltage from +2.5V to -2.5V. 11. Keep the switch in Auto position. 12. Vary the Bipolar potentiometer from -2.5V to +2.5V, and note the corresponding digitized outputs. 13. Set the Auto / Manual switch to manuals position. 14. Keep the Blank / Convert switch to blank position. 15. Now to observe the conversion you have to throw the switch to convert position. 16. Perform the experiment with various DC inputs. RESULTS:-According to applied input signal in form of DC level it provides the digital signals in 1 and 0 forms.

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Government Polytechnic, Muzaffarpur Digital Electronics & M.P. Lab Subject Code: 1621507 Operation of Delta modulation circuit Aim: To study the characteristics of delta modulation and demodulation kit. Apparatus Required: 1. Delta modulation and demodulation Kit 2. Digital Storage Oscilloscope (DSO) 3. Power supply 4. Patch cords

Procedure: 1. The connections are given as per the block diagram. 2. Connect power supply in proper polarity to kits DCL-07 and switch it on. 3. Keep the Switch S2 in Delta position. 4. Keep the Switch S4 High. 5. Observe the various tests points in delta demodulator section and observe the reconstructed signal through 2nd order and 4th order filter . TABULATION

Block Diagram

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Fig 5.1a Block diagram for delta modulation and demodulation MODELGRAPH

RESULT Delta Modulation and Demodulation are verified in the hardware kit and its waveforms are studied.

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Government Polytechnic, Muzaffarpur Digital Electronics & M.P. Lab Subject Code: 1621507 seven segments display circuit Aim: Operation of seven segments display circuit. Apparatus: SN 7447 BCD-to-seven segment decoder.

Theory: BCD-to-seven Segment converter: A light emitting Diode (LED) is a PN junction diode. When the diode is forward biased, a current flows through the junction and the light is emitted. See Fig.1

. Fig.1 A seven segment LED display contains 7 LEDs. Each LED is called a segment and they are identified as (a, b, c, d, e, f, g) segments. See Figure 2

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Fig. 2.. Digits represented by the 7 segments

Fig. 3.. Digits represented by the 7 segments The display has 7 inputs each connected to an LED segment. All anodes of LEDs are tied together and joined to 5 volts (this type is called common anode type). A limiting resistance network must be used at the inputs to protect the 7-segment from overloading. BCD inputs are converted into 7 segment inputs (a, b, c, d, e, f, g) by using a decoder, as shown in Fig. 3.5. A decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2n output lines. The input to the decoder is a BCD code and the outputs of the systems are the seven segments a, b, c, d, e, f, and g. For further information and pin connections, consult the specification sheet for decoder and 7-segment units.

Experimental Procedure: (1) First design a combinational circuit, which would implement the decoder function for only the segment “a”, of the display. This can be done in the following steps: a) Write down the truth table with 4 inputs and 7 outputs (Table 1). b) For only the output “a”, obtain a minimum logic function. Realize this function using NAND gates and inverters only. For example if decimal 9 is to be displayed a, b, c, d, f, g must be 0 and the others must be 1 (For common anode type display units), if decimal 5 is to be displayed then a, f, g, c, d must be 0 and the others must be 1. c) Connect the output “a” of your circuit to appropriate input of 7-segment display unit. By applying BCD codes verify the displayed decimal digits for that segment for “a” of the display. d) Replace your circuit by a decoder IC 7447 for all of the seven segments. Observe the display and record the segments that will light up for invalid inputs sequence.

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Fig:4.

Table:1

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Conclusion:

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