Debussy Modelsim

Debussy 5.0 and Modelsim 5.X Windows-Based Shao-Sheng Yang 2001/08/06

Before Simulation • Copy X:\Novas\Debussy\share\PLI\modelsim_pli\WINNT\nova s.dll to X:\modelsim\win32\ • Edit X:\modelsim\modelsim.ini and add block box text

2001/08/06

2

Simulation • To add 2 Debussy system tasks to stimulation file( or call testbench file)

2001/08/06

3

In the Modelsim (1) • 1. Change working directory to directory of source code (ex: File->Change Directory, f:\temp\)

2001/08/06

4

In the Modelsim (2) • 2. Create a new library for this work (ex: Design -> Create a New Library)

2001/08/06

5

In the Modelsim (3) • Compile Source Code (ex: Design -> Compile)

2001/08/06

6

In the Modelsim (4) • Load the top module to modelsim for this work (ex: the top module is test, Design -> Load Design -> test)

2001/08/06

7

In the Modelsim (5) • View the sub-window, Wave, Structure, and Signals (ex: View -> Wave, View -> Structure, and View -> Signals)

2001/08/06

8

In the Modelsim (6) • Add selected signals to Wave-window

2001/08/06

9

In the Modelsim (7) • Before

2001/08/06

• After change display Properties (ex: Edit-> Display Properties)

10

In the Modelsim (8) • To Run, In Main window or Wave window press run –all. (In the red circle)

2001/08/06

11

In the Modelsim (9) • DON’T Finish it when the Finish Vsim is popped. Press “NO” button

2001/08/06

12

In the Modelsim (10) • Zoom in, Zoom out, or Zoom Full

2001/08/06

13

In the Debussy(1) • Call the nWave from Debussy, or type: C:\Novas\Debussy\bin\Debussy -nWave

2001/08/06

14

In the Debussy(2) • Open the data base from *.fsdb (ex:reg_bus.fsdb)

2001/08/06

15

In the Debussy(3) • Get selected signals (ex: Signal -> Get Signals)

2001/08/06

16

In the Debussy(4) • The WaveForm

2001/08/06

17

Appendix-Example // // // //

Register Bus Example1 Din address is 11_1111_1111, are Write or Read Dout address is 11_1111_1111, is Read only Written by Shao-Sheng Yang

module counter(reg_data,reg_addr,reg_wr,reg_rd,/*reg_en*/dout,load,clk,rst); inout [15:0] reg_data; input [9:0] reg_addr; input reg_wr; input reg_rd; input load; //input reg_en; output [15:0] dout; input clk,rst; wire [15:0] reg_data; reg [15:0] dout; reg [15:0] din; reg [15:0] reg_data_tmp; assign reg_data=reg_data_tmp;

2001/08/06

always @(posedge clk or posedge rst) begin if (rst) begin din<=16'b0; end else begin // To write register din from register data bus if (reg_wr==1'b1) begin case (reg_addr)//synopsys parallel_case 10'b11_1111_1111: din <= reg_data; endcase

18

end else begin din <= din; end end end always @(posedge clk or posedge rst) begin if (rst) begin reg_data_tmp<=16'b0; end else begin // TO read register din to register data bus if (reg_rd==1'b1) begin case(reg_addr) //synopsys parallel_case 10'b11_1111_1111:reg_data_tmp<=din; 10'b11_1111_1110:reg_data_tmp<=dout; default:reg_data_tmp<=16'bz; endcase end else reg_data_tmp<=16'bz; end end always @(posedge clk or posedge rst) begin if (rst) dout <= 16'b0; else if (load) dout <= din; else dout <= dout +1'b1; end endmodule

2001/08/06

19

Appendix-Testbench //Testbench for Register Bus module test; wire [15:0] reg_data; reg [9:0] reg_addr; reg [15:0] reg_data_tmp; reg reg_wr; reg reg_rd; reg load; wire [15:0] dout; reg

clk,rst;

counter U1(reg_data,reg_addr,reg_wr ,reg_rd,dout,load,clk,rst); assign reg_data=reg_data_tmp; initial

initial begin #0 rst=1'b0; clk=1'b0; load=1'b0; reg_rd=1'b0; reg_wr=1'b0; reg_addr=10'b0; #10 rst=1'b1; #12 rst=1'b0; @(negedge clk) reg_wr=1'b1; reg_data_tmp=16'ha0a0; reg_addr=10'h3ff; @(negedge clk) reg_wr=1'b0; reg_data_tmp=16'ha1a1; @(negedge clk) load=1'b1; @(negedge clk) load=1'b0; reg_data_tmp=16'hz; @(negedge clk) reg_rd=1'b1;

begin $fsdbDumpfile("reg_bus.fsdb"); //Debussy system task $fsdbDumpvars; //Debussy system task,dump variables to file .fsdb end

2001/08/06

@(negedge clk) reg_rd=1'b0; @(negedge clk) @(negedge clk) reg_addr=10'h3fe; reg_rd=1'b1; @(negedge clk) reg_rd=1'b1; @(negedge clk) reg_addr=10'h3fe; reg_rd=1'b1; @(negedge clk) reg_rd=1'b0; @(negedge clk) @(negedge clk) $finish; end always #5 clk=~clk; endmodule

20