Database Template 939
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[color=blue][b]dfi...[/color][/b] [color=blue][b]cpu...[/color][/b] [color=red][b]ram...[/color][/b] [color=blue][b]gpu...[/color][/b], [color=red]drivers...[/color] [color=blue][b]hdd..[/color][/b] [color=blue][b]optical... [/color][/b] [color=blue][b]psu...[/color][/b]
* * * * [b]genie bios settings:[/b] [color=red] fsb bus frequency............................. ldt/fsb frequency ratio....................... cpu/fsb frequency ratio....................... pci express frequency.........................
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200 5 10 100mhz
cpu vid startup value.........................
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1.350v
cpu vid control............................... cpu vid special control....................... ldt voltage control........................... chip set voltage control...................... dram voltage control..........................
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1.350v above vid * 104% 1.20v 1.50v 2.80v[/color]
[b]dram configuration settings:[/b] [color=red] dram frequency set............................ command per clock (cpc)....................... cas latency control (tcl)..................... ras# to cas# delay (trcd)..................... min ras# active time (tras)................... row precharge time (trp)...................... row cycle time (trc).......................... row refresh cyc time (trfc)................... row to row delay (trrd)....................... write recovery time (twr)..................... write to read delay (twtr).................... read to write delay (trwt).................... refresh period (tref)......................... dram bank interleave..........................
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180=ram/fsb:9/10 enable 2.0 2 5 2 7 bus clocks 10 bus clocks 02 bus clocks 02 bus clocks 02 bus clocks 03 bus clocks 3120 cycles enabled
dqs skew control.............................. dqs skew value................................ dram drive strength........................... dram data drive strength......................
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auto 0 auto auto
max async latency............................. dram response time............................ read preamble time............................ idlecycle limit............................... dynamic counter............................... r/w queue bypass.............................. bypass max.................................... 32 byte granularity........................... [/color]
[b]short description: 200x10 @ 2000mhz, 1.404 cpu voltages 2-2-5-2 @ 200mhz, 2.8v vdimm[/b]
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auto normal auto 256 cycles disable 16 x 07 x disable(4 bursts)
* * * * [b]genie bios settings:[/b] [color=red] fsb bus frequency............................. ldt/fsb frequency ratio....................... cpu/fsb frequency ratio....................... pci express frequency.........................
-
200 5 10 100mhz
cpu vid startup value.........................
-
1.350v
cpu vid control............................... cpu vid special control....................... ldt voltage control........................... chip set voltage control...................... dram voltage control..........................
-
1.350v above vid * 104% 1.20v 1.50v 2.80v[/color]
[b]dram configuration settings:[/b] [color=red] dram frequency set............................ command per clock (cpc)....................... cas latency control (tcl)..................... ras# to cas# delay (trcd)..................... min ras# active time (tras)................... row precharge time (trp)...................... row cycle time (trc).......................... row refresh cyc time (trfc)................... row to row delay (trrd)....................... write recovery time (twr)..................... write to read delay (twtr).................... read to write delay (trwt).................... refresh period (tref)......................... dram bank interleave..........................
-
180=ram/fsb:9/10 enable 2.0 2 5 2 7 bus clocks 10 bus clocks 02 bus clocks 02 bus clocks 02 bus clocks 03 bus clocks 3120 cycles enabled
dqs skew control.............................. dqs skew value................................ dram drive strength........................... dram data drive strength......................
-
auto 0 auto auto
max async latency............................. dram response time............................ read preamble time............................ idlecycle limit............................... dynamic counter............................... r/w queue bypass.............................. bypass max.................................... 32 byte granularity........................... [/color]
[b]short description: 200x10 @ 2000mhz, 1.404 cpu voltages 2-2-5-2 @ 200mhz, 2.8v vdimm[/b]
-
auto normal auto 256 cycles disable 16 x 07 x disable(4 bursts)
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