Cost Index: Gates Per Chip Chips Per Board Crosspoints Per Board

Cost Index    

Gates per chip Chips per board Crosspoints per board Number of crosspoints in the switching network  Reference network    

Crossbar network N x M N=M cost index = N2 Non-blocking Multi-stage networks 1

4 x 4 Crossbar Switch A1

A1

A2

A2

A3

A3

A4

A4 B1

B2

B3

B4

B1

B2

B3

B4

2

Crosspoint Switch 



Electromechanical  Switching speed : 1-10 ms  Minimal wear & adjustments  Ex. Miniswitches- mechanically latch, speed 8-10 ms Reed relays-mechanical motion of bars eliminated, electrical contacts made of magnetic material in a sealed glass, Displacement: 0.2 mm Switching time < 1 ms electrical / magnetic latching Electronic  Diode crosspoints, transistorised (Bipolar/FET), N2  FDM switching: FT-TR, expensive, 2N devices  TDM switching: relatively economical 3

SWITCHING 

SPACE SWITCHING Full availability  Limited availability  Grading  Multi-stage switching 







Blocking condition

TIME SWITCHING

COMBINATION SWITCHING 4

Multistage networks 

N x M ; s stages



ri switch matrices of order ni x mi at stage i



N = n 1r1

; M = msrs



ith stage  No. of outlets/switch x no. of switch matrices at ith stage = No. of inlets/ switch x no. of switch matrices at (i+1)th stage  m r = n i i i+1 ri+1  (0 ≤ i ≤ s-1 )



Type of interconnection 5

Interstage pattern configuration 

Full connection (FC)  If each matrix in stage i (i = 2,…. s-1) is connected to all the matrices in stage i -1 and i +1



Partial Connection (PC)  If each matrix in stage i (i = 2,…. s-1) is not connected to all the matrices in stage i -1 and i +1 6

FC  No. of outlets/switch at ith stage ≥ No. of switch matrices in (i+1)th stage mi ≥ ri+1 PC  No. of outlets/switch at ith stage < No. of switch matrices in (i+1)th stage mi < ri+1

7

Full Connection Multi-stage networks Matrices in adjacent stages  always connected by atleast one link ni x mi Switch matrix  crossbar network ni = ri-1 ; mi-1 = ri ( i = 2,….s )



 

0

0

0

0

n-1

m-1

n-1

m-1

0

0

0

0

n-1

m-1

n-1

m-1

1

2

s-1

s 8

Full Connection Multi-stage networks(Cont.d) 

Two stage FC network  Accessibility  full  Blocking  single link between matrices of adjacent stages



Three stage FC network  Different I/O paths available between any couple of matrices  switching capacity  Full accessibility  Non-blocking condition determined by number of second stage switch matrices



Centralized control and storage of state of terminations and interstage links  complex algorithm for rearrangeable networks 9

Partial Connection Multistage networks 

Features:  Intermediate stage switch matrix  connected to a subset of adjacent stages  Availability of high degree of parallel processing  Small matrices ( switching elements SE , 2 x 2) with autonomous processing capability



Necessity:  High speed packet switched communication networks  To carry very large amount of traffic  To change network permutation at a very high rate 

State duration of the order of few µs

10

Multistage link system  

N x N single stage with SC = K Two stages: NxK KxN N inlets outlets

‘r’

N

K links Full connectivity or full availability ‘s’ switches switches

pxs

rxq

M inlets

M = p.r N outlets N = q.s pxs

rxq 11

Route Switch      

M=N  N x N switch Let p = q = n inlets per Primary Switch & r = s = g = N/n switches in each stage No. of XPs S  2 N2/ n Switching Capacity SC  g2 = ( N/n )2 ≤ N Letting SC = N, n = √N & S = 2 N 3/2

nxg

gxn

N inlets

N outlets nxg

‘g’ switches

gxn ‘g’ switches

12

Design Example (1)    



Requirement : 200 x 200 Route switch with SC = 200 SC = N = 200 n = √N = 14.14… , to be an integer & also a factor of N Case I :  Let n = 10   No. of Primary switches = ?  No. of Secondary switches = ?  No. of XPs per PS = ?  No. of XPs per SS = ?  Total no. of XPs =  No. of concurrent paths between IT & OT = ? Case II :  Let n = 20 

13

Concentrator Design 

M inlets > N outlets  Inlets per PS = m (p)  Outlets per SS = n (q)  No. of Primary switches = M/m  No. of Secondary switches = N/n  No. of XPs per PS = mN/n  No. of XPs per SS = Mn/m  Total no. of XPs S = MN ( 1/n + 1/m )  Switching Capacity SC = MN/mn ≤ N 





n = M/m  S = MN ( m/M + 1/m )  m opt = nopt = √ M  S min = 2 N √ M

No. of concurrent paths between IT & OT = ?

EXPANDER SWITCH  M inlets < N outlets 14