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Power Saving Rotary Clock Design VManoj Kumar & DM.Vandhaana,ECE-IlI, RajaRajesxvari Engg. College

Abstract:-Rotary clock is a recently proposed clock distribution technique based on wave propagation in transmission lines. In our paper, we investigate the problem of power minimization of rotary clock designs. Specifically, we can develop a software tool based on the method of partial element equivalent circuit (PEEC) that is capable of extracting the "SPICE" net list from the layout specification of a rotary clock design. Using that tool, we can perform extensive analysis that links various design parameters of a rotary clock design to its oscillation frequency and power dissipation. Based on the results of that analysis, we then propose a power minimization algorithm. The algorithm derives a rotary clock dimension requirement and oscillating at the target frequency with the given clock load. Experimental results can demonstrate that, for target operating frequencies ranging from 0.5 to 5 GHz, rotary clock designs can achieve power savings of up to 80% in comparison with conventional clock tree implementations.

Index Terms-Clocks, partial element equivalent circuit, synchronization, transmission line resonators, travelling-wave amplifiers.

INTRODUCTION IN MOST synchronous CMOS ICs, global clock signals are transmitted from the clock source to individual registers using a network of interconnects and buffers. Electronic charges are placed on the clock network from the power grid during the charging phase and drained to the ground during the discharging phase. Consequently, the power dissipation of clock networks increase significantly with the increase of operating frequencies and chip dimensions of modern VLSI systems. The design of low power global clock distribution networks has become one of the major challenges for the IC industry. Clock distribution networks can be designed as LC oscillators since clock signals simply oscillate at a given frequency. These Oscillators store the energy in the inductors during the discharging phase and reuse it during

the

charging

phase,

potentially

achieving low-power clock distribution. In particular, the rotary clock technique proposed in one of small approaches. It relies on the principle of wave travelling in transmission lines to generate square wave clock signals. However, no design methodology has been presented to analyze and minimize the power dissipation of rotary clock design. As a result, true power saving capability of a rotary clock scheme remains unknown. In this paper, we investigate the low power synthesis of rotary clock structures. Two major contributions are presented. First, we have developed a layout extraction tool for rotary clock designs. Our tool is based on the Partial Element Equivalent Circuit (PEEC) method is highly accurate. Using our extraction tool, we are able to perform an extensive analysis that links variable parameters, e.g., interconnect width and separation, to the oscillation frequency and power dissipation of rotary clock design. Second, Based on our analysis, we propose a novel low power rotary clock design methodology. Specifically, given the target clock frequency, the clock structure dimension, and the total clock load, our scheme automatically derives a rotary design with the lowest power consumption while satisfying the design specifications. We have applied our power minimization algorithm to rotary clock designs with the range of target frequency, various dimensions, and different clock loads. Practical results

should give the average power reduction is 65% with the comparison to conventional clocking schemes. The maximum power saving is 80%. Our data also reveal the rotary clock scheme is particularly effective for the high frequency (at the range of 0.5 to 5 GHz) large dimension, and high clock load designs.

BACKGROUND Current Clocking Schemes:Extensive effects have been devoted to the design of clock distribution networks. Early clock distribution networks are implemented using tree structures made of interconnects and buffers. For modern VLSI designs, however, the combination of high target frequencies and significant physical variations makes it very difficult, if possible, for even balanced clock trees, e.g., H-trees to satisfy the strict clock skew requirements. Consequently, non tree topologies, e.g., meshes and spines. In addition, active devices such as PLLs are often added to further reduce clock skews. As a result, clock networks become highly complex, leading to large power consumptions. Conventional clocking schemes based on capacitance charging become incompetent in implementing lowpower clock distribution for future systems-on-chip (SoCs) due to the large dynamic power consumed by large clock loads . Clocking techniques based on the LC resonant oscillation have been proposed. Such

oscillators have energy recovery capabilities and therefore, can provide stable clock signals while dissipating a small amount of power.

ROTARY CLOCK:The Circuit structure of rotary clock and its operating principle can be explained by fig.l.

Specifically, a rotary ring is a double loop made of interconnects. A voltage wave can propagate in the transmission line formed by the parallel interconnects of the inner and outer loops .Since the transmission line inverts at point A, a voltage wave changes its polarity during the consecutive rotations. As result every location along the ring provides the square wave clock signal. Registers can be connected to the rotary ring by attaching their clock inputs to the interconnects. Inverter pairs connected back to back are attached to the clock ring to compensate the energy lose due to the resistivity of the interconnects so that the clock wave can be sustained indefinitely. The adjacent rings are joined together by two nodes, one in the inner loop and one in the outer loop. The lumped circuit model given in for a fraction of the transmission line. Where C, L and R are the capacitance inductance and resistance of the transmission line respectively. The

capacitances of the load registers and compensation inverters are represented by Goad_a, Cioadj>and Cg. since the clock wave travels two rotations in a clock period, the oscillation frequency F can be calculated as (V/21) Where v And I are the phase velocity and ring length, respectively. On the first order approximation, v is calculated using the differential unit-length inductance Li and capacitance as 1/(VLICI) Given a rotary ring width the height and separation of the interconnects being w, h and s respectively.

((Cload_a+Cload_b)/2)) / I Where p0 is the electron mobility. R OBL EM FORMULATION The design and optimization of low power rotary clock arrays are much more challenging than those of the conventional clock networks. The rotary array has many design parameters that need to be determined including the no. of rings, the dimension of each ring, the interconnect width, the separation between the inner and outer interconnect loops, the no. of inverted pairs and the location and size of each inverters. Moreover, the selection of these parameters must satisfy the two constraints. Specifically, different from the conventional clock networks, a

rotary clock structure does not contain a clock source. As a result, the design parameters must be selected so that the resulting rotary array oscillates at the target frequency with the given clock load. Second, since the registers are attached to the rotary clock interconnects, the size of the rotary array must match the chip area to facilitate the register placement. In addition to satisfying the previous constraints, the rotary clock array must dissipate the minimal power. PEEC-Based Extraction tool To derive an efficient algorithm, to solve a problem power saving rotary clock, it is critical to understand the relations between the various design parameters and the frequency or power dissipation of a rotary clock structure. Since the lumped circuit model proposed, it does not consider high frequency effects such as skin effect and proximity effect, is not accurate and, therefore cannot be used. This section describes a lay out extraction tool based on PEEC method. Our tool is capable of converting the geometric specification of a rotary ring into a SPICE netlist that precisely captures the circuit behavior of the ring. Consequently, we can accurately derive the oscillation frequency and power dissipation of the rotary ring using SPICE simulation. The PEEC method is proposed to derive the equivalent circuit for the design that consists of an arbitrary the no. of conductors in any shapes. Since it is based on Maxwell's eqn. The PEEC method models all electromagnetic effects and is highly

accurate. The key operation in the application of the PEEC method is to partition all conductors into filaments . with uniform current densities. The modeling of resistance, capacitance and transistors is ''straight forward. Specifically, the resistance of each filament is derived using the filament dimensions and the sheet resistance Jo illustrate the importance of developing our PEEC based extraction tool, we have compared the frequency and power dissipation estimates derived i: by stimulating the circuit net list. Specifically, the rotary clock ring and designed using a 0.18pmm technology. All rings are in square shape with the perimeter of 3200pm. The centre line separation between the inner and outer ring is 80(jm. There are a total of 40 inverted pairs evenly distributed along each clock ring. The nMOS and pMOS transistor widths are 25 and 62.5|jm respectively. The interconnect with varies from 10 to 75|jm. The lumped model over estimates the power dissipation in all cases. The average estimation deviation is 57%. The worst case estimation deviation is 19%. Consequently, our layout extraction tool is indispensible in any power analyses of rotary clock designs. Frequency And Power Analysis Of Rotary Clock Designs Next, we analyze our rotary clock designs using our PEEC based extraction tools and spice

stimulation. First we

investigate the selection of interconnect with 'w' and separation's'. Specifically, we have designed and stimulated a set of rotary rings with constant length and the capacitive loads. The constant frequency contours close to the horizontal axis represent low frequency. As a result, oscillation frequency

than 24%. The resonant clocking scheme can reduce power dissipation of both the Global and clock network. ROTARYPMIN (F,D,C) 1 (do, So, Wo, Wo)=lnitialization(F,D,Cj 2n0 = [D/do] 3 for (n = n0-1, rio+1,1) 4d = D/n 5for(W= 1.2Wo,0.2Wo.0.2Wo) 6m = [(n2+l/2)]

is a monotonic function of 'w'.

Similarly, we plot the frequency and power contours with respect to the clock load c and inverter width 'w'. Both 'c'and 'w' affects the frequency by

«

*L This section presents our heuristic algorithm that

solves the problem power saving rotary clock. Our algorithm first derives a solution that satisfies the target. It then conducts the search in the solution space to minimize the power dissipation. However, since the global clock power is often less than 30% of total clock power, the overall power saving is less

(p,s,wj=TUNE_WIRE(F,c,d,W) 8if(Pmin > P) 10

PMIN = p,

(dmin,

Wmin, Smin,

Wmin) =

(d,W,s,w) 1 1 return (dmin, Wmin, Smin, Wmin)

Algorithm for ROTARYPuim A power savings of 35% is reported. To maintain the high power efficiency,

their clock design should operate in the sinusoidal mode, however. On the other hand, the simulation results show a65% power reduction on the average with square wave clock signals generated. Admittedly, to achieve the full power reduction potential of the rotary clock, it is required to develop a multiphase circuit design methodology because rotary clock rings can only produce varying the phase clock signals. The design of such a methodology is beyond the scope of the paper, however. Conclusion: In this paper, we propose rotary clock design methodology for low power clock distribution. Specifically, we first develop a PEEC- based extraction tool so that we can simulate a given rotary clock structure using SPICE. Using our tool, we can perform extensive simulations to analyze the impacts of variations design parameters on the frequency and power dissipation of rotary clock rings. Based on the analysis result, we propose scheme achieve up to 80% power reduction on the average in comparison to the conventional clock trees. Several future research topics remain open. In particular, for simplification purposes, we introduce several assumptions, e.g., uniform interconnect dimension and uniform transmission lines, in the proposed low power rotary clock construction algorithm. Design techniques that are not restricted to such assumptions may

achieve higher power efficiency and need to be investigated. In this paper, we focus only on the design of the rotary clock arrays. !n particular, since rotary clock designs provide clock signals with varying phases due to the wave travelling principle, the key problem in the design of rotary clock-based VLSI designs is how to drive a circuit signals with a full spectrum skews. A potential solution is to use clock scheduling to tune the required skew values of all registers so that the skew are spread in wide range without introducing any timing violations. References:[1] J. Wood, T.C. Edwards, and S. lipa, "Rotary travelling-wave oscillator arrays: A new clock technology" IEEE J. solid state circuits, vol-32, no. 11, pp. 1654-1665, Nov. 2001. [2] E.G. Freidman, clock distribution networks in VLSI circuits and systems. Picataway, NJ: IEEE Press, 1995. [3] J. Pangjin and S. Sapatnekar, "Lowpower clock distribution using multiple voltages and reduced swings," IEEE Trans. Very Large Scale integr. (VLSI) systems. [4] M. Desai, R. Cvijetic, and J. Jensen, "Sizing of clock distribution for high performance CPU chips," in Proc. Des Autom. Conf., 1996, pp. 389-394.

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