Content Digital

CONTENT Chapter 1. Numeration Systems ......................................................................1 1.1. Number and Symbol .................................................................................1 1.2. Octal and Hexadesimal to Decimal Convertion .......................................16 1.3. Convertion From Decimal Numeration ....................................................17 Chapter 2. Binary Arithmatic ...........................................................................24 2.1. Numbers Versus Numeration ....................................................................24 2.2. Banary Edition ..........................................................................................24 2.3. Negative Binary Numbers.........................................................................25 2.4. Subtraction ................................................................................................28 2.5. Overflow ...................................................................................................30 2.6. Bit Grouping .............................................................................................33 Chapter 3. Logic Gates ....................................................................................35 3.1. Digital Signal and Gates ...........................................................................35 3.2. The NOT Gates .........................................................................................39 3.3. The “Buffer” Gates ...................................................................................51 3.4. Multiple-input Gates .................................................................................55 3.5. The AND Gates .........................................................................................56 3.6. The NAND Gates ......................................................................................58 3.7. The OR Gates ............................................................................................59 3.8. The NOR Gates .........................................................................................62 3.9. The Negative AND Gates .........................................................................62 3.10. The Negative OR Gates ..........................................................................63 3.11. The Exlusive-OR Gates ..........................................................................64 3.12. The Exclusive-NOR Gates ......................................................................66 3.13. TTL NAND and AND Gates ..................................................................68 3.14. TTL NOR and NOR Gates .....................................................................74 3.15. CMOS Gates Cercuitry............................................................................77 3.16. Special Output Gates ..............................................................................91 3.17. Constructing The NOT Function ............................................................95 3.18. Constructing The Buffer Function ..........................................................96 3.19. Constructing The AND Function ............................................................97 3.20. Constructing The NAND Function .........................................................97 3.21. Constructing The OR Function ...............................................................98 3.22. Constructing The NOR Function ............................................................99 3.23. Logic Signal Voltage Levels ...................................................................100 3.24. DIP Gates Packaging ..............................................................................109 Chapter 4. Boolean Algebra .............................................................................112 4.1. Introduction ...............................................................................................112 4.2. Boolean Arithmatic ...................................................................................114

Chapter 5. Multivibrator ..................................................................................117 5.1. Digital Logic With Feedback ....................................................................117 5.2. The S-R Latch ...........................................................................................118 5.3. The Gated S-R Latch ................................................................................120 5.4 The D Latch ...............................................................................................121 5.5. Edge Tregered Latches : Flip-Flops ..........................................................122 5.6. Asynchronous Flip-Flop Input ..................................................................128 Chapter 6. Counter ...........................................................................................130 6.1. Binary Count Sequence ............................................................................130 6.2. Asynhcronous Counter ..............................................................................132 6.3. Synchcronous Counter ..............................................................................140