Computer Organization May 2006

Set No. 1

Code No: RR220501

II B.Tech II Semester Regular Examinations, Apr/May 2006 COMPUTER ORGANIZATION ( Common to Computer Science & Engineering, Information Technology, Computer Science & Systems Engineering and Electronics & Computer Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. (a) How mandatory signal lines for PCI are functionally grouped [8+8]

in

(b) Explain typical desktop system using PCI configuration.

o.

2. (a) How subtraction is done on the binary numbers represented in one’s complement notation give an examples.

.c

(b) What do you mean by r’s complement.

[8+8]

ss

3. Explain common addressing modes with suitable flow diagrams. Also explain the merits and demerits of each, in detail. [16]

re

4. (a) Explain the register organization in a Power PC processor [8+8]

xp

(b) Classify interrupts on a Power PC.

(b) What is compaction

se

5. (a) Explain various schemes available for partitioning memory and the merits and demerits of each. [8+3+5]

pu

(c) Differentiate between external and internal fragmentation

m

6. (a) What is the transfer rate for 9-track magnetic tape unit whose tape speed is 120 inches per second and whose tape density is 1600 linear bits per inch? (b) Elaborate about erasable optical disk

ca

(c) Differentiate between sequential-access and direct-access devices [8+4+4]

7. (a) How the address of next microinstruction is known while executing a micro program. (b) Discuss about branch control logic in microinstruction sequencing with variable address format. [6+10] 8. A pipelined processor has two branch delay slots. An optimizing complier can fill one of these slots 85 percent of the time and can fil second slot only 20 percent of the time. What is the percentage improvement in performance achieved by this optimization? [16] ⋆⋆⋆⋆⋆ 1 of 1

Set No. 2

Code No: RR220501

II B.Tech II Semester Regular Examinations, Apr/May 2006 COMPUTER ORGANIZATION ( Common to Computer Science & Engineering, Information Technology, Computer Science & Systems Engineering and Electronics & Computer Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. Explain the expanded structure of IAS computer with a neat block diagram.

in

[16]

o.

2. (a) Multiply the following binary number

.c

i. 1110 and 0111 ii. 101110 and 101011

ss

(b) How is floating point multiplication performed? (c) Explain about excess 50 form

[6+6+4]

xp

re

3. Write programs to execute Y= (A-B) / (C+D*E) using one-address, two-address and three-address instructions. [16] 4. (a) List various R3000 pipeline stages. Also explain the function of each.

se

(b) List and describe all shift and multiply/divide instructions of MIPS R-Series processors. [8+8]

pu

5. (a) Differentiate between single versus two-level caches. (b) Elaborate on Pentium Cache Organization.

[8+8]

m

6. (a) List the hardware events that occur after an I/O device completes an I/O operation in interrupt driven I/O.

ca

(b) List and explain the interrupt modes of Intel 8259A interrupt controller. [8+8] 7. (a) Explain the principles and working of dot matrix printers. (b) Differentiate between different types of printers.

[8+8]

8. (a) Classify and explain different multiprocessors (b) Explain the organization of tightly coupled multiprocessor system with a generic block diagram. [8+8] ⋆⋆⋆⋆⋆

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Set No. 3

Code No: RR220501

II B.Tech II Semester Regular Examinations, Apr/May 2006 COMPUTER ORGANIZATION ( Common to Computer Science & Engineering, Information Technology, Computer Science & Systems Engineering and Electronics & Computer Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. (a) Differentiate between dedicated and multiplexed bus lines.

in

(b) Discuss various methods of bus arbitration.

2. (a) Explain about the arithmetic in excess - 3 code.

o.

(c) What do you mean by bus width?

.c

(b) Discuss about normalized floating point representation

[5+7+4]

[6+10]

ss

3. (a) List the instruction formats used on the PDP-11.

re

(b) Draw and explain Pentium instruction format.

4. Elaborate on different types of registers in a register organization

[8+8] [16]

xp

5. (a) Discuss the principles of associative memory.

se

(b) Explain the functioning of 4 x 4 bit associative memory array. (c) Explain the cache with two-way set-associative addressing

[6+4+6]

pu

6. (a) What is the transfer rate for 9-track magnetic tape unit whose tape speed is 120 inches per second and whose tape density is 1600 linear bits per inch?

m

(b) Elaborate about erasable optical disk (c) Differentiate between sequential-access and direct-access devices

ca

[8+4+4]

7. (a) Explain the principles and working of dot matrix printers. (b) Differentiate between different types of printers.

[8+8]

8. (a) Why special handling is required for branch instruction in a pipelined processor. Explain with examples. (b) How would you determine the number of pipeline stages in a pipelined processor [10+6] ⋆⋆⋆⋆⋆

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Set No. 4

Code No: RR220501

II B.Tech II Semester Regular Examinations, Apr/May 2006 COMPUTER ORGANIZATION ( Common to Computer Science & Engineering, Information Technology, Computer Science & Systems Engineering and Electronics & Computer Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆

(b) Elaborate the characteristics of a hypothetical machine

[6+6+4]

o.

(c) What do you mean by hardwired program?

in

1. (a) What is instruction Cycle ?

.c

2. (a) What do you mean by improper storage of floating point numbers. Explain with an example.

ss

(b) What is the range of real numbers represented in normalized floating point representation in a 6 digit register. [8+8]

re

3. Discuss about various Pentium operation types with examples.

[16]

xp

4. (a) Differentiate between large register file versus cache. (b) Discuss how compiler based register optimization is done.

se

(c) Explain various characteristics of reduced instruction set architectures. [6+6+4]

pu

5. (a) Differentiate between single versus two-level caches. (b) Elaborate on Pentium Cache Organization.

m

6. Discuss the major functions and requirements for an I/O module.

[8+8] [16]

ca

7. (a) Differentiate between micro programmed and hard wired control units with merits and demerits of each. (b) Discuss about the design considerations of micro instruction sequencing technique. [8+8] 8. (a) Differentiate between high-level and low-level parallelism (b) Discuss about Flynn’s classification of parallel processor systems. (c) Explain different MIMD interconnection topologies. ⋆⋆⋆⋆⋆

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[5+6+5]