Computer Organization & Articture No. 10 From Apcoms

Interrupts & instruction Set

Lecture 10 COA by Athar Mohsin

Interrupts • The basic hardware already introduced – the CPU, buses, the control unit, registers, clocks, I/O, and memory.

• There is one more concept that deals with how these components interact with the processor: – Interrupts are events that alter (or interrupt) the normal flow of execution in the system. – An interrupt can be triggered for a variety of reasons, including: • • • • • • • •

I/O requests Arithmetic errors (e.g., division by zero) Arithmetic underflow or overflow Hardware malfunction (e.g., memory parity error) User-defined break points (such as when debugging a program) Page faults Invalid instructions (usually resulting from pointer issues) Miscellaneous

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The interrupts • An interrupt can be initiated by the user or the system, – can be maskable (disabled or ignored) or – nonmaskable (a high priority interrupt that cannot be disabled and must be acknowledged), – can occur within or between instructions, – may be synchronous (occurs at the same place every time a program is executed) or – asynchronous (occurs unexpectedly), and – can result in the program terminating or continuing execution once the interrupt is handled.

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Instruction Set • An instruction set is a list of all instructions, that a processor can execute, Instructions include: – – – –

arithmetic such as add and subtract logic instructions such as and, or, and not data instructions such as move, input, output, load, and store control flow instructions such as goto, if, call, and return.

• opcode (Operation Code) is the portion of a machine language instruction that specifies the operation to be performed. – A complete machine language instruction contains an opcode and, the specification of one or more operands—what data the operation should act upon

• An operand is one of the inputs (arguments) of an operator. For instance, in 3 + 6 = 9 • '+' is the operator and '3' and '6' are the operands.

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Instruction Cycle • Basic function performed by a computer is execution of a program – consists of set of instructions stored in the memory – Processor executes the instructions specified in the program

• Instruction processing consists of two steps: – Processor reads – Fetches from memory one at time – Execute each instruction

• Program execution – repeating the steps over and over – Processing required for a single instruction is called “ instruction cycle” COA by Athar Mohsin

Simple example • Example of a simple operation – Add the contents of the memory at address 940 to the contents of the memory at address 941 and store the result in the next location

• If the processor contains – – – –

A single data register – AC Instructions and the data are of 16 bit long Memory is of 16 bit word The instructions are • 4 bit opcode 24=16 different opcode • 12 bits for the data = 212 = 4k locations • The partial list of opcodes from the instruction set is: – 0001 = load AC from memory – 0010 = Store AC to memory – 0101 = Add to AC from memory

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Example of Program Execution Example Add the contents of the memory at address 940 to the contents of the memory at address 941 and store the result in the next location

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0001 = load AC from memory 0010 = Store AC to memory 0101 = Add to AC from memory

1. Program Execution • PC contains 300 – the address of the first instruction – This instruction (the value 1940h) is loaded into the IR – PC is incremented (301)

301

• The process involve the use of – Memory Address Register (MAR) – Memory Buffer Register (MBR)

0001 = load AC from memory 0010 = Store AC to memory 0101 = Add to AC from memory COA by Athar Mohsin

2. Program Execution • The first nibble in the IR indicate that the AC is to be loaded – Remaining 12 bits specifies the • Address 940 from which data are to be loaded 1940h=

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0001 1001 0100 0000 0001 1001 0100 0000

Load contents to AC

0001 940 0001 = load AC from memory 0010 = Store AC to memory 0101 = Add to AC from memory

Example of Program Execution • The next instruction 5941 is fetched from the location 301 • PC is incremented 5941h=

302

0101

0101 1001 0100 0001 0101 1001 0100 0001 0001 = load AC from memory 0010 = Store AC to memory 0101 = Add to AC from memory

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Add contents to AC

Example of Program Execution • The old contents of AC and the contents of the location 941 are added • The result is stored in AC

0001 = load AC from memory 0010 = Store AC to memory 0101 = Add to AC from memory COA by Athar Mohsin

Example of Program Execution • The next instruction 2941 is fetched from location 302 – PC is incremented

• The contents of AC are stored in location 941

2941h=

0010 1001 0100 0001 0010 1001 0100 0001

Store the contents of AC at address x COA by Athar Mohsin

0001 = load AC from memory 0010 = Store AC to memory 0101 = Add to AC from memory

Instruction Processing • The fetch-decode-execute cycle is the series of steps that a computer carries out when it runs a program. – We first have to fetch an instruction from memory, and place it into the IR. – Once in the IR, it is decoded to determine what needs to be done next.

• If a memory value (operand) is involved in the operation, it is retrieved and placed into the MBR. – With everything in place, the instruction is executed. COA by Athar Mohsin

Instruction Processing •

All computers provide a way of interrupting the fetch-decodeexecute cycle.

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Interrupts occur when: – A user break (e.,g., Control+C) is issued – I/O is requested by the user or a program – A critical error occurs

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Interrupts can be caused by hardware or software. – Software interrupts are also called traps.

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Interrupt processing involves adding another step to the fetchdecode-execute cycle as shown below.

Instruction Processing • For general-purpose systems, it is common to disable all interrupts during the time in which an interrupt is being processed. – Typically, this is achieved by setting a bit in the flags register.

• Interrupts that are ignored in this case are called maskable. • Nonmaskable interrupts are those interrupts that must be processed in order to keep the system in a stable condition. COA by Athar Mohsin

Interrupts • All computers provide the mechanism by which other modules (e.g. I/O) may interrupt normal sequence of processing • Most common classes of interrupts are: – Program: generated by some condition e.g. overflow, division by zero – Timer: Generated by internal processor timer, allow Operating system to perform certain functions at regular intervals – I/O: from I/O controller – Hardware failure: generated by a failure such as power COA by Athar Mohsin

Interrupts • The mechanism by which other system modules may interrupt the normal processing of the CPU – These devices are slower than the CPU – CPU can waste vast amount of processing cycles waiting for these slow devices to perform their tasks

• Interrupts let the CPU execute its normal instruction sequence and pause to service to the external devices only when they signal (the interrupts) that they are ready for the CPU’s attention • The processor and the O/S are responsible for – recognizing an interrupt, suspending the user program, servicing the interrupt, and then resuming the user program

• Each interrupt is associated with a procedure that directs the actions of the CPU when an interrupt occurs.

– Nonmaskable interrupts are high-priority interrupts that cannot be ignored.

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Interrupts • Interrupts are processed in an interrupt cycle within the overall instruction cycle – At the end of an instruction cycle (operand storage step), check to see if any interrupts are pending

• – If there aren’t any, proceed with the next instruction • – If there are – Suspend execution of the program and save its “state” – Jump to the interrupt service routine and resume the “normal” instruction cycle – When the ISR is completed, restore the state of the program and resume its operation COA by Athar Mohsin

Interrupt and Instruction Cycle • To accommodate interrupts, in interrupt cycle is added to the instruction cycle – Processor check for the occurrence of interrupt – If no interrupt the processor proceeds to fetch cycle and fetch next instruction of the current program – In case of interrupt • It suspends execution of current program and saves the address of next instruction • Set the PC to starting address of interrupt handler routine

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Instruction Processing

• Interrupts can be caused by hardware or software. – Software interrupts are also called traps.

• Interrupt Cycle – Added to instruction cycle – Processor checks for interrupt • Indicated by an interrupt signal

– If no interrupt, fetch next instruction – If interrupt pending: • • • • • COA by Athar Mohsin

Suspend execution of current program Save context Set PC to start address of interrupt handler routine Process interrupt Restore context and continue interrupted program

Multiple interrupts • A typical system can support several to several dozen interrupts – How should the system respond if more than 1 interrupt occurs at the same time? • Systems prioritize the various interrupts • At the start of the interrupt cycle, the highest priority pending interrupt will be serviced • Remaining interrupt requests will be serviced in turn

• What if an interrupt occurs while an ISR is being executed (a result of a previous interrupt) – Ignore the second interrupt (by disabling interrupts) until the ISR completes – Recognize and service the interrupt only if it has a higher priority than the one

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Interrupts • Provided primarily as a way to improve processing efficiency? • User program performs a series of WRITE calls – Code segment 1,2 and 3 are the sequence of instructions not involving I/O

• WRITE call are to an I/O program, to perform actual I/O operation – Code segment 4 is to prepare for actual I/O operation – Code 5 to complete the operation

• Since no interrupt so the user program will stop for some time COA by Athar Mohsin

interrupt • With interrupts the processor can be executing other instructions while I/O operation in progress – When user program reaches to the system call from WRITE – The I/O program invoked and all preparation work will be done by the I/O – After this short time the control returns to the user program – I/O will keep on doing its job

• I/O module will generate an interrupt request – Processor will respond by suspending it current execution and branch the current execution COA by Athar Mohsin

Program long I/O • The user program reaches the second WRITE call before the I/O operation generated by first call is compete • When the previous I/O operation is complete the new WRITE call will be proceeds and new I/O operation starts • Advantage – Efficiency of operation – When part of I/O operation is under way it overlaps the execution of user program

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Multiple Interrupts • Disable interrupts: while an interrupt is being processed – Processor will ignore further interrupts whilst processing one interrupt – Interrupts remain pending and are checked after first interrupt has been processed – Interrupts handled in sequence as they occur • Drawback: don't give relative pri

• Define priorities – Low priority interrupts can be interrupted by higher priority interrupts – When higher priority interrupt has been processed, processor returns to previous interrupt COA by Athar Mohsin

Multiple Interrupts - Sequential

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Multiple Interrupts – Nested

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Time Sequence of Multiple Interrupts

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Instruction Formats Instruction sets are differentiated by the following: • • • • • •

Number of bits per instruction. Stack-based or register-based. Number of explicit operands per instruction. Operand location. Types of operations. Type and size of operands.

Instruction set architectures are measured according to: • • • •

Main memory space occupied by a program. Instruction complexity. Instruction length (in bits). Total number of instructions in the instruction set.

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Instruction Formats •In designing an instruction set, consideration is given to: • Instruction length. – Whether short, long, or variable.

• Number of operands. • Number of addressable registers. • Memory organization.

– Whether byte- or word addressable.

• Addressing modes.

– Choose any or all: direct, indirect or indexed.

•Byte ordering, or endianness, is another major architectural consideration. •If we have a two-byte integer, the integer may be stored so that the least significant byte is followed by the most significant byte or vice versa. – In little endian machines, the least significant byte is followed by the most significant byte. – Big endian machines store the most significant byte first (at the lower address). COA by Athar Mohsin

Instruction Formats • As an example, suppose we have the hexadecimal number 12345678. • The big endian and small endian arrangements of the bytes are shown below.

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Big endian: – Is more natural. – The sign of the number can be determined by looking at the byte at address offset 0. – Strings and integers are stored in the same order.

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Little endian: – Makes it easier to place values on non-word boundaries. – Conversion from a 16-bit integer address to a 32-bit integer address does not require any arithmetic.

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Problem • if you wished to transfer data from a big endian machine to a little endian machine? – If the machines receiving the data uses different endianness than the machine sending the data, the values can be misinterpreted. • For example, the value from Problem 3, sent as the value -511 on a big endian machine, would be read as the value 510 on a little endian machine.

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Example • The first two bytes of a 2M x 16 main memory have the following hex values: – Byte 0 is FE – Byte 1 is 01

• If these bytes hold a 16-bit two's complement integer, what is its actual decimal value if: – a. memory is big endian? – b. memory is little endian?

• Ans. – a. FE01 h = 1111 1110 0000 00012 = -51110 – b. 01FE h = 0000 0001 1111 11102 = 51010 COA by Athar Mohsin