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COLT Telecommunications NR Training

Advanced SDH

Not to be shown outside of COLT. Course ID – NR1130

Training Manual NR1130/09/99/MCC _____________________________________________________________________

History: Issue No: 1 2 3 4 5 6 7

Issue Date Date Edited 08-09-99 25-10-99 23-12-99 23-12-99

Reason for Change Draft 1st issue Addition of STM-n appendix Addition of VC-4 composition 01-06-00 01-06-00 information and general typo corrections 13-9-00 13-09-00 Addition of basic SDH topology 16-01-01 16-01-01 Addition of Appendix B 03-04-02 03-04-02 Addition of concatenation info 03-05-2002 03-05-2002 Addition of Appendix C

Author M Costin M Costin M Costin M Costin M Costin M Costin M Costin M Costin

This document is intended for training purposes only. The current controlled version of this document is available via the COLT UK Intranet. Any printed copy is Uncontrolled.

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Training Manual NR1130/09/99/MCC _____________________________________________________________________

Table of Contents 1. Introduction..................................................................................................................1 1.1. Comparison of hierarchical PDH rates....................................................................2 1.2. PDH ‘n’ Suffix.........................................................................................................2 1.3. Disadvantages of PDH networks.............................................................................3 1.4. Overview of PDH Limitations................................................................................5 2. Origins of SDH.............................................................................................................6 2.1. Features and Advantages of SDH ...........................................................................7 2.2. Basic SDH Network Topology................................................................................8 3. SDH Principles.............................................................................................................9 3.1. Overview ................................................................................................................9 3.2. STM Hierarchy and Container Bit Rates..............................................................10 3.3. Full SDH Multiplexing Structure..........................................................................11 3.4. European Preferred Multiplexing Structure..........................................................11 3.5. Graphical SDH Multiplexing Structure.................................................................12 4. SDH Structure Details...............................................................................................13 4.1. STM-1 Frame Structure........................................................................................13 4.2. SDH Concatenation...............................................................................................14 5. SDH Functional Details.............................................................................................16 5.1. Mapping of a 2 Mbit/s PDH signal into a C-12....................................................16 5.2. Mapping of a C-12 into a VC-12...........................................................................16 5.3. V5 Path Overhead (TU-12 POH)..........................................................................19 5.4. Mapping of a VC-12 into a TU-12 signal.............................................................20 5.5. TU Pointers............................................................................................................21 5.6. Multiplexing of TU-12 into a TUG-2 ...................................................................23 5.7. Mapping of a TUG-2 into a TUG-3 signal............................................................25 5.8. Mapping of a TUG-3 into a VC-4 signal...............................................................26 5.9. VC-4 Path Overhead.............................................................................................27 5.10. Mapping of a VC-4 into an STM-1 frame...........................................................29 5.11. AU Pointers.........................................................................................................30 5.12. VC-4 Justification................................................................................................32 5.13. STM-1 Section Overheads..................................................................................33 6. Appendix A - STM-n Frame Structure ...................................................................36 6.1. STM-4 Frame Structure........................................................................................36 6.2. STM-16 Frame Structure......................................................................................37 7. Appendix B - Circuit labelling and rates look up table..........................................38 8. Appendix C - The Electromagnetic Spectrum........................................................39

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Training Manual NR1130/09/99/MCC _____________________________________________________________________

1. Introduction Before 1970 most of the worlds telephony system were based on single line, voice frequency, connections over twisted copper pair. For long haul routes, Frequency Division Multiplexing (FDM) was used to combine multiple signals onto a single coaxial transmission cable for increased efficiency. Such transmission equipment was very expensive in relation to the line bandwidth and quality, and was also relatively unreliable for the standards of the day as it was based on analogue multiplexing techniques. In the early 1970’s digital transmission systems began to appear using Pulse Code Modulation (PCM). Alec Reeves of Standard telephone cables (STC) had first proposed this system of transmission in 1937. PCM enables analogue waveforms such as speech to be converted into a binary format suitable for transmission over long distances via digital systems. PCM works by sampling the analogue signal at regular intervals, assigning a value to the sample and then transmitting this value as a binary stream. This process is still in use today and forms the basis of virtually all the transmission systems that we currently use. 4 3 2 1 0

Sampler

Quantiser

Encoder

01010011

Fig 1.1 PCM Block diagram Engineers soon saw the potential to produce more effective transmission systems by combining several PCM channels together over the same copper pair. In Europe a standard was adopted where thirty-two, 64kbit/s channels were combined to produce a structure with a bit rate of 2.048 Mbit/s (usually referred to as 2 Mbit/s). As demand for telephony services grew, it soon became apparent that the standard 2 Mbit/s signal was not sufficient to cope with the demands of the growing network, and so a further level of multiplexing was devised. Four, 2 Mbit/s signals were combined together to form an 8 Mbit/s signal (actually 8.448 Mbit/s). As the need arose further levels of multiplexing structure were added to include rates of 34 Mbit/s (34.368), 140 Mbit/s (139.264) and 565 Mbit/s (564.992). These transmission speeds are called Plesiochronous Digital Hierarchy or PDH rates.

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Training Manual NR1130/09/99/MCC _____________________________________________________________________

1.1.Comparison of hierarchical PDH rates Whilst the European hierarchy was being developed a similar system was being devised in America. Although the same principal was used, a different hierarchical structure was adopted. Japan also developed a different hierarchy, which incorporated some elements of the American system: Europe Primary

2.048 Mbit/s 8.44 Mbit/s 34.368 Mbit/s 139.264 Mbit/s

North America Primary 1.544 Mbit/s 6.132 Mbit/s 44.736 Mbit/s 274.176 Mbit/s

Japan Primary

1.544 Mbit/s 7.876 Mbit/s 32.064 Mbit/s 97.728 Mbit/s

Although each of the systems works fine as a stand-alone hierarchy, it does make international inter-connection very difficult and costly. This was the major reason for the development of a new internationally agreed standard.

1.2.PDH ‘n’ Suffix The PDH rates are often referred to by an ‘n’ suffix. This suffix is also used within SDH to refer to the various different PDH input signals. The table below shows these suffixes and there associated rates.

‘n’ Suffix 0 11 12 21 22 31 32 4

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Bit rate (Kbit/s) 64 1,544 2,048 6,312 8,448 34,368 44,736 139,264

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Training Manual NR1130/09/99/MCC _____________________________________________________________________

1.3.Disadvantages of PDH networks Because of the way that PDH equipment compensates for signals that vary in clock frequency and phase, it is impossible to extract for a single 2 Mbit/s signal from within a higher order (say 140 Mbit/s) stream. Therefore when a 2 Mbit/s signal needs to be cross-connected between one transmission system and another, it must be de-multiplexed back down to its primary rate first. This forms what is referred to a multiplexer mountain. 34 Mbit/s 140 Mbit/s LTE

140 / 34

140 / 34

140 Mbit/s LTE

8 Mbit/s 34 / 8

34 / 8

2 Mbit/s 8 / 2

8 / 2

ADD DROP 2Mbit's Tributary

As we can see, the multiplexer mountain means that we need to have a lot of expensive equipment just to connect 2 Megs together. This means that: •

Valuable space is taken up in racks in node sites and more equipment means more maintenance-associated problems. Each of the equipment levels is synchronised from a different source and at a different rate. This can lead to clock 'slip' and 'contention' problems

•

This equipment must also be jumpered not only at the 2 Mbit/s level for customer interconnection, but also between the various multiplexers that make up the individual transmission system. This leads to large amounts of coax wiring, which is physically very bulky and also relatively high maintenance due to the fact that the terminating plugs work on a mechanical nature.

A diagram of this is shown overleaf.

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O L T E

O L T E

OLTE

•

An advantage of PDH is the small overhead of the system. This leads to efficient use of bandwidth. Unfortunately because of this lack of overhead in the structure, management facilities in PDH are severely limited.

•

There is no automatic storage of route information so comprehensive and accurate paper records must be kept to avoid problems. There is no ability to remotely configure equipment and the alarm monitoring is rudimentary, effectively only reporting loss of inputs.

•

Another downside of the lack of overheads, is the inability of the system to provide any performance monitoring related data. If problems occur on a link it must be disconnected first to enable testing to take place. This would need to be done out of hours, with the permission of the customers using the link.

•

Protection of the transmission paths is generally only available using 1+1 protection at the higher PDH levels i.e.140 Mbit/s and above, leaving customer 2 Mbit/s circuit vulnerable to failure.

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1.4.Overview of PDH Limitations •

Interconnection between national (European/North American/Japanese) systems very difficult.

•

PDH 'multiplexer mountain' is costly and inflexible.

•

All hierarchy levels are clocked individually, so slips possible.

•

Protection of paths is at higher rates only.

•

Management is very limited.

•

Relatively prone to faults (by today's standards).

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Training Manual NR1130/09/99/MCC _____________________________________________________________________

2. Origins of SDH As can be seen from the previous chapter PDH is a workable but flawed system. At its conception it used the best available technology and was a giant leap forward in transmission, but with the advent of silicon chips and integrated microprocessors, customer demand soon provided the need to introduce a new and better system. This new system needed to solve the existing limitations of PDH, but also provide for applications of the future. The first of the working systems to be introduced was the SYNTRAN (Synchronous Transmission) system from Bellcore. This did not live up to expectations and was soon replaced with SONET (Synchronous Optical Network). Initially SONET could only carry the ANSI (American National Standards Institute) bit rates i.e. 1.5, 6, 45 Mbit/s. Since the aim of the project was to provide easier international interconnection, SONET was modified to carry the European standard bit rates of 2, 8, 34 & 140 Mbit/s. In 1989 CCITT (Consultative Committee International for Telephone and Telegraph), now ITU-T (International Telecommunications Union - Telecommunication's standardisation section) published recommendations G704, G.707, G.708 and G.709 which covered the standards for SDH. These were adopted in North America by ANSI (SONET is now thought of as a subset of SDH), making SDH a truly global standard.

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2.1.Features and Advantages of SDH •

SDH permits the mixing of existing European (ETSI) and North American (ANSI) PDH bit rates.

•

SDH is apparently synchronous. All SDH equipment is based on the use of a single master reference clock source.

•

Compatible with the majority of existing PDH bit rates

•

SDH provides for much simpler extraction/insertion, of a lower order bit rate from a higher order aggregate stream, without the need to de-multiplex in stages.

•

SDH provides cross-connection of any low order stream to any other low order stream without the need to de-multiplex in stages.

•

SDH allows for integrated management and performance monitoring using a centralised network control.

•

SDH provides for a standard optical interface thus allowing the inter-working of different manufacturers equipment's.

•

SDH provides for future higher order rates by a simple BYTE interleaving process.

•

SDH standards have been prepared for future applications such as Asynchronous Transfer Mode (ATM), High Definition Television (HDTV) and Metropolitan Area Networks (MAN).

•

Increase in system reliability due to reduction of necessary equipment/jumpering.

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Training Manual NR1130/09/99/MCC _____________________________________________________________________

2.2.Basic SDH Network Topology SDH networks are usually deployed in rings. This has the advantage of giving protection to the data, by providing an alternate route for it to travel over in the event of equipment or network failure. Each side of the ring (known as A and B, or sometimes, East and West), consists of an individual transmit and receive fibre. These fibres will take diverse physical paths to the distant end equipment to minimise the risk of both routes failing at the same time. The SDH equipment can detect when there is a problem and will automatically switch to the alternate route.

B

A

B

A

TX

RX

TX

RX

RX

TX

RX

TX

Customer A

B

A

Customer B

Customer A

A

B

Customer B

"Fibre break on the Ring Customer B Switches"

"Ring Normal"

To speed up switching times, the SDH multiplexers transmit on both routes simultaneously, but only elect to receive on one side. This means that only the receiving end needs to switch (the transmitting end stays the same), thus reducing the impact of a fault on the customers' data. To further improve switching times, each network element will switch independently of its neighbours (Uni-directional). This means that if a single fibre is broken, only one site needs to switch. Automatic restoration to a chosen path (revertive switching), is provided for within the switching set up, but is not used by COLT, as this would just cause another "Hit" on the customers' data.

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Training Manual NR1130/09/99/MCC _____________________________________________________________________

3. SDH Principles 3.1.Overview The SDH standard defines a number of 'Containers' each corresponding to an existing PDH bit rate. Information from the incoming PDH signal is mapped into the relevant container. This is achieved using a bit stuffing procedure similar to that used in a PDH multiplexer. Each container then has some control information known as the 'Path Overhead' (POH) added to it. The path overhead bytes allow the system operator to achieve end to end path monitoring of areas such as error indication, alarm indication and performance monitoring data. Together the container and the path overhead form a 'Virtual Container' (VC). In an SDH network, all equipment is synchronised from a single master clock. The timing of the PDH signals entering the SDH network and being mapped into the VC's may vary slightly in frequency and/or phase from the SDH master clock. Additional stuffing bits are either added, or used as data bits, to align the different clock rates in a process called Justification. Groups of four VC frames make up an SDH multiframe. Due to clock phase differences, the start of the multiframe may not coincide with the start of the four VC frames and as a result, the location of individual virtual containers within the multiframe may vary. Identification of the start of the four VC's is achieved by adding a 'Pointer' that identifies the start of the VC within the multiframe. The VC and its relevant pointer together form a 'Tributary Unit' (TU). Tributary units are then multiplexed together in stages (Tributary User Group 2 (TUG-2) - Tributary User Group 3 (TUG-3) - Virtual Container 4 (VC-4)), to form an Administrative Unit 4 (AU-4). Additional stuffing, pointers and overheads are added during this procedure. This AU-4 in effect contains 63 x 2 Mbit/s channels and all the control information that is required. Finally, Section Overheads (SOH) are added to the AU-4. These SOH's contain the control bytes for the STM-1 section comprising of framing, section performance monitoring, maintenance and operational control information. An AU-4 plus its SOH's together form an STM-1 transport frame.

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3.2.STM Hierarchy and Container Bit Rates The first hierarchy level for SDH is set at 155,520 kbit/s/s. This is known as a Synchronous Transport Module 1 (STM-1). Higher levels are simply multiples of the first level, which are denoted by the number after the ‘-‘ At present the SDH hierarchy is as follows: • • • •

STM-1: STM-4: STM-16: STM-64:

155,520 kbit/s. 622,080 kbit/s. 2,488,320 kbit/s. 9,953,280 kbit/s.

(155 Mbit/s) (620 Mbit/s) (2.5 Gbit/s) (10 Gbit/s)

SDH allows for various PDH input rates to be mapped into containers as shown below: • • • • •

Container C11: Container C12: Container C2: Container C3: Container C4:

1544 kbit/s 2048 kbit/s 6312 kbit/s 49,536 kbit/s 139,264 kbit/s

(1.5 Mbit/s) (2 Mbit/s) (6 Mbit/s) (45 & 34 Mbit/s) (140 Mbit/s)

As can be seen from this chart, the only PDH rate that is not directly supported by SDH is 8 Mbit/s. This is not a popular bit rate in Europe and can be achieved by inverse multiplexing techniques if required although only on a manufacturer specific basis. Note: Containers are expressed, as (for instance), 'Container - One - Two', not 'Container Twelve' etc.

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3.3.Full SDH Multiplexing Structure The diagram shows the complete SDH multiplexing structure. PDH signals enter on the right into the relevant container and progress across to the left through the various processes. The route via VC-3 and AU-3 (shown with dotted lines) are for SONET applications (does not include 140 Mbit/s payloads), and are not applicable in Europe.

S T M -n

xN

AUG

x1

A U -4

V C -4

C -4

1 3 9 2 6 4 k b it /s

C -3

4 4 7 3 6 k b it/s 3 4 3 6 8 k b it/s

x3 x3

x1

T U G -3

T U -3

V C -3

x7 A U -3

V C -3

x7

T U G -2

P o in te r P r o c e s s in g

x1

T U -2

V C -2

C -2

6 3 1 2 k b it/s

T U -1 2

V C -1 2

C -1 2

2 0 4 8 k b it/s

T U -1 1

V C -1 1

C -1 1

1 5 4 4 k b it/s

x3

M u ltip le x in g

x4

A lig n in g M a p p in g

3.4.European Preferred Multiplexing Structure The above diagram shows the European structure for a 2 Mbit/s circuit. The relative bit rate and process is shown for each stage

Adds SO H (7 2 b y te s )

S T M -n 155520000

T ra n s p a re n t

xN

AUG

x1

150912000

Adds AU P o in t e r (9 b y te s )

M u ltip le x e s 3 T U G 3 's to fo rm a V C - 4 w it h 2 c o lu m n s o f fix e d s tu f fin g and a V C -4 p a th o v e rh e a d (2 7 b y te s )

A U -4

V C -4

150912000

150336000

P o in te r P r o c e s s in g

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M u ltip le x e s 7 T U G 2 's t o fo rm a T U G - 3 w it h 2 c o lu m n s o f fix e d s tu ffin g (1 8 b y te s )

x3

T U G -3

x7

49536000

M a p p in g

M u lt ip le x e s 3 T U - 1 2 's to fo rm a T U G -2

x3

T U G -2 6912000

A dds TU P o in t e r (1 b y te )

A d d s P a th O v e rh e a d , J u s tific a tio n a n d f ix e d S t u ff in g (3 b y te s )

T U -1 2

V C -1 2

C -1 2

2304000

2240000

2048000

A lig n in g

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B it s

M u ltip le x in g

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3.5.Graphical SDH Multiplexing Structure STM -1 Stream

SOH VC-4

AU Pointers SOH

AU Pointers

VC-4

VC-4 + AU Pointers = AUG / AU

3 x TUG-3's + POH = VC-4

P O H

TUG-3 #1

TUG-3 #2

TUG-3 #3

7 x TUG-2's = TUG-3 A

A

B

B

C

D

E

F

G

c

A

B

C

D

D

E

F

G

E

A

B

c

D

E

F

G

3 x TU-12's = TUG-2 TU Pointer

T U 1 2

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V5 Path overhead

V C 1 2

F

Stuffing and Justification bits

C 1 2

PDH Bitstream

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G

Training Manual NR1130/09/99/MCC _____________________________________________________________________

4. SDH Structure Details The following page's detail the process followed by a 2 Mbit/s PDH input signal until it becomes part of an STM-1 frame. It details the individual stages and should be used with reference to the preceding SDH structure diagrams

4.1.STM-1 Frame Structure The STM-1 transport frame has a duration of 125µs. It contains 2430 bytes of information. Each byte contains 8 data bits (i.e. a 64kbit/s channel). The number of frames per second is 1 second / 125µs = 8000 Frames per second. Therefore the rate transmitted to line is: 8 bits x 2430 bytes x 8000 per second = 155,520,000 bits/s or 155 Mbit/s. As each frame consists of 2430 bytes, this would prove very difficult to show as a diagram on a page. To get round this, we show the frame chopped up into 9 segments, stacked on top of each other as shown in the diagram below. The bits start at the top left with byte number one and are read from left to right and top to bottom. They are arranged as 270 columns across and 9 rows down. Therefore byte 270 is the byte in column 270, row 1. Byte 271 is in column 1, row 2 and byte 2430 is located at column 270, row 9 etc. 270 Columns (bytes) 1

9 10

270

1

RSOH 9 R o w s

3 4 5

AU PTR's

P O H

VC-4Payload

MSOH

9

Further explanations of the areas within the STM-1 frame are given later.

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4.2.SDH Concatenation The SDH frame can be thought of as an articulated lorry. The data to be transported is placed in the VC-4 'Container'. This is then hitched to the SOH 'Cab unit' that 'drives' the data to its destination. The maximum carrying capacity of the vehicle is determined by the size of the 'container'. Therefore although the SDH signal is 155 Mbit/s in size, the largest single circuit that can be transmitted at any one time by the customer is limited to the size of the VC-4 i.e. 140 Mbit/s.

140 M/bits Payload

VC-4 Payload SOH

155 M/bits SDH Frame

When using higher rates of SDH (STM-4, STM-16 etc), multiple 'containers' and 'cabs' are added one after another, to form a bigger vehicle. The customer is still limited to a single circuit size of 140 Mbit/s however, because each individual 'container' is the same size (140 Mbit/s). They can however transmit multiple 140 Mbit/s circuits simultaneously. The diagram below represents the standard STM-4 structure

VC-4 Payload SOH

SOH

SOH

VC-4 Payload

VC-4 Payload

VC-4 Payload

SOH

This limitation of 140 Mbit/s per individual circuit is not a particularly efficient way of managing bandwidth and a method of combining 'containers' together has been developed which is called 'Concatenation'. The diagram below represents an STM-4 concatenated structure (VC-4-4C).

VC-4 Payload SOH

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Training Manual NR1130/09/99/MCC _____________________________________________________________________ Concatenated paths are commonly defined as VC-4-xC circuits (where x is size of the concatenation), as shown below: •

STM-4 concatenation (written as VC-4-4c), provides a single circuit with a bit rate of approximately 600M (actually 599.04 Mbit/s)

•

STM-16 concatenation (written as VC-4-16c), provides a single circuit with a bit rate of approximately 2.2G (actually 2.2396160 Gbit/s)

•

STM-64 concatenation (written as VC-4-64c), provides a single circuit with a bit rate of approximately 10G (actually 9.584640 Gbit/s)

•

STM-256 concatenation (written as VC-4-256c), provides a single circuit with a bit rate of approximately 38G (actually 38.338560 Gbit/s)

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5. SDH Functional Details 5.1.Mapping of a 2 Mbit/s PDH signal into a C-12. The 2 Mbit/s PDH input signal is mapped into a Container 12 (C-12). The input frame consists of 32 bytes of information and this fits directly into the C-12 as shown. 32 Data Bytes

5.2.Mapping of a C-12 into a VC-12. The mapping of a C-12 into a VC-12 is not done on an individual C-12 basis. The mapping process includes the addition of fixed stuffing, overhead bytes and justification. This process takes place over 4 C-12's. These four C-12's plus stuffing and overheads make up a VC-12 Multiframe: Frame number One has two bytes of fixed stuffing added to it. One byte is added at the start and one byte at the end. It then has one byte of overhead control information added to the start. This byte of over head is called the V5 byte and is known as the Path OverHead (POH). The function of V5 is explained in detail later on. F r a m e 1

V5 R R R R R R R R 32 Data Bytes

V5 - Path Overhead R - Fixed stuff bits

R R R R R R R R

Frame number Two has two bytes of fixed stuffing added to it. One byte is added at the start and one byte at the end. It then has one byte of overhead control information added to the start. This control byte in frame 2 is the Lower Order Path Trace or J2 byte. J2 is used to check continuity of a 2 Mbit/s path. It is currently not supported by manufacturers.

F r a m e 2

J2 C1 C2 R R R R R R 32 Data Bytes

J2 - Lower Order Path trace C - Justification control R - Fixed stuff bits

R R R R R R R R

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Training Manual NR1130/09/99/MCC _____________________________________________________________________ Frame number Three has two bytes of fixed stuffing added to it. One byte is added at the start and one byte at the end. It then has one byte of overhead control information added to the start. This control byte N2, in frame 3 is called the Network Operator or Tandem Control byte. N2 is used to transmit performance-monitoring information where the circuit spans differing vendors networks (i.e. Colt to BT).

F r a m e 3

N2 C1 C2 R R R R R R 32 Data Bytes

N2 - Network Operator byte C - Justification control R - Fixed stuff bits

R R R R R R R R

Frame number Four has one byte of fixed stuffing added to the end. It also has one byte of variable stuffing added to the start. It then has one byte of overhead control information added to the start. This control byte in frame 4 is called K4. Bits 1 to 4 of K4 are used for 2 Mbit/s Automatic Protection Switching or APS. APS is used to automatically switch a single 2 Mbit/s circuit to its alternate path if a fault condition occurs.

F r a m e 4

K4 C1 C2 R R R R R S1

K4 - APS (bits 1-4) K4 - Reserved (bits 5-7)

S2 D D D D D D D

K4 - Spare (bit 8) C - Justification control S - Justification bits R - Fixed stuff bits D - Data bits

31 Data Bytes R R R R R R R R

S1 and S2 in frame 4 provide the justification opportunity. Justification is the process that compensates for clock frequency differences between the incoming PDH signal and the SDH master clock. Under ideal conditions S1 is used for stuffing and S2 is used for data. S2 can be used to provide extra stuffing if the PDH signal is slow. S1 can be used to provide extra data bits if the PDH signal is fast. The C1 and C2 bits in frames 2,3 and 4 of the multiframe control S1 and S2 respectively. Because each individual frame may or may not need justification, majority rule determines the use of S1 and S2. An incoming PDH 2 Mbit/s signal has a maximum permitted clock deviation of 50 parts per million (ppm). This means the PDH signal should waver by no more than 100 bits in either direction, giving a spread of 200 bits. SDH provides for 1 bit of justification (either stuffing or data), every VC-12 multiframe. As there are 2000 multiframes per second this gives a compensation spread of 2000 bits which is more than adequate compared to the 200 bits permitted by PDH.

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Training Manual NR1130/09/99/MCC _____________________________________________________________________ The diagram below shows the complete VC-12 multiframe:

Virtual Container - 12 V5 R R R R R R R R 32 Data Bytes

D R S C

-

Data bits Fixed stuff bits Justification bits Justification control

R R R R R R R R J2 C1 C2 R R R R R R 32 Data Bytes R R R R R R R R N2 C1 C2 R R R R R R

V5 - Path Overhead J2 - Lower Order Path trace N2 - Network Operator byte K4 - APS (bits 1-4) K4 - Reserved (bits 5-7) K4 - Spare (bit 8)

32 Data Bytes R R R R R R R R K4 C1 C2 R R R R R S1 S2 D D D D D D D 31 Data Bytes R R R R R R R R

The VC-12 multiframe contains a total of 140 bytes and duration of 500µs.

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5.3.V5 Path Overhead (TU-12 POH) The V5 byte is constructed as shown below:

RFI BIP-2

Signal Label

1 2 3 4 5 6 FEBE

7

8 FERF

BIP-2 - Bit Interleaved Parity-2 FEBE - Far End Bit Error (result of BIP2) RFI - Remote Fail Indication LO Signal Label - Low Order Signal Lable FERF - Far End Receiver Fail

•

BIP-2 is Bit Interleaved Parity Check-2. This looks at the data in the C-12. It counts all of the binary one's that it sees in the odd positions (i.e. bits 1,3,5,7 etc). If this count is an even number it puts a binary 0 in bit 1 of V5. If this count is an odd number it puts a binary 1 in bit 1 of V5. It then counts all of the binary one's that it sees in the even positions of the C-12 (i.e. bits 2,4,6,8 etc). If this count is an even number it puts a binary 0 in bit 2 of V5. If this count is an odd number it puts a binary 1 in bit 2 of V5. This BIP-2 is then recalculated at the distant end. If the count is different, then some bit corruption has occurred.

•

FEBE is Far End Bit errors. This bit is set correspondingly to the result of the BIP-2 check. If errors are received at the distant end then there needs to be a mechanism for informing the sender of the problem. If bit 3 of the V5 is a binary 0 then BIP-2 was ok. If bit 3 of the V5 is a binary 1 then BIP-2 was bad and the transmitting end will raise an alarm. FEBE alarm is also known as Remote Error Indication (REI). The term 'Far End Bit errors' tends to imply that the fault is at the remote end. It could actually be from many different places in the route, so the name has been changed to make it less ambiguous.

•

RFI is Remote Failure Indicator. If a Loss of Pointer and/or AIS all 1's in V1/V2) is detected in the receive path, a binary 1 is sent back in bit 4 of V5. In effect a loss of TU-12 frame alignment alarm. This alarm is also known as RAI or Remote Alarm Indication.

•

LO Sig. Label is Lower order Signal Label. This is used to indicate the type of VC payload. It comprises of bits 5, 6 and 7 of V5, but only 2 are actually needed. 000 - indicates the port is unequipped. 010 - indicates that it is asynchronously mapped i.e. normal, in service. On some manufacturers equipment this determines if alarms are raised when a 2 Mbit/s port is physically disconnected.

•

FERF is Far End Receiver Fail. Bit 8 in V5 is set to binary 1 if the distant end has detected certain TU path alarms. This alarm is also known as RDI or Remote Defect Alarm.

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Training Manual NR1130/09/99/MCC _____________________________________________________________________

5.4.Mapping of a VC-12 into a TU-12 signal. The V5 byte must be seen by the distant end for it to detect the start of the multiframe, (similar to the use of the multiframe alignment word in PDH), and hence the start of the 2 Mbit/s signal. There must be some mechanism therefore to ensure that the distant end can detect V5. This is achieved by adding four overhead bytes to the multiframe, which together form a calculated byte count to the start of V5. This is called a pointer value and is known as the TU Pointer. There are four pointer bytes called V1, V2, V3 and V4. Only V1 and V2 are actually needed to calculate the location of V5.

Tributary Unit - 12 Virtual Container - 12 V1

D - Data bits R - Fixed stuff bits S - Justification bits C - Justification control

V5 - Path Overhead J2 - Lower Order Path trace N2 - Network Operator byte K4 - APS (bits 1-4) K4 - Reserved (bits 5-7) K4 - Spare (bit 8)

F r a m e 4

F r a m e 1

K4 C1 C2 R R R R R S1 S2 D D D D D D D 31 Data Bytes R R R R R R R R V5 R R R R R R R R

V2 V5

32 Data Bytes R R R R R R R R V3

F r a m e 2

144 Bytes

J2 C1 C2 R R R R R R 32 Data Bytes R R R R R R R R V4

F r a m e 3

F r a m e 4

C1 C2

N2 R R R R R R

32 Data Bytes R R R R R R R R K4 C1 C2 R R R R R S1

V1 - VC pointer 1 V2 - VC pointer 2

S2 D D D D D D D

V3 - Reserved V4 - Reserved

31 Data Bytes R R R R R R R R

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Training Manual NR1130/09/99/MCC _____________________________________________________________________

5.5.TU Pointers V1 and V2 bytes in the TU-12 together form the pointer to the start of V5. The value of V1 and V2 is a count of the number of bytes from the end of V2 to the start of the V5 byte. This count does not include V1, V2, V3 or V4. Because V5 can actually start anywhere within the TU multiframe, this pointer value ranges from 0 to 139. An example is shown below:

Tributary Unit - 12 Pointer Value

State of H4 byte V1

XXXXXX00

104 VC-12 139 0

V2 V5

XXXXXX01

VC-12 34 V3

XXXXXX10

144 Bytes

35 VC-12 69 V4

XXXXXX11

70 VC-12 103 V1 - VC pointer 1 V2 - VC pointer 2 V3 - VC pointer 3 (action) V4 - Reserved

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Training Manual NR1130/09/99/MCC _____________________________________________________________________ When the 2 Mbit/s port is first cross-connected on the multiplexer and an end to end path is created, a value for the initial pointer will be generated, and placed in the V1 and V2 bytes. If a fault causes a break in the transmission path it could result in a change of V5 position. This change needs to be transmitted to the distant end. If this is the case a new pointer value will be generated. The old pointer value is then incremented/decremented in steps, by a value of one each time, until it matches the new value required. V1 and V2 bytes are shown below:

V1 byte

1

2

3

4

5

V2 byte

6

7

8

1

2

3

4

5

6

7

8

N N N N S S

I

D

I

D

I

D

I

D

I

D

10 bit pointer value

NNNN SS I D

- New Data Flag - TU type ('10' for a TU-12) - Pointer Value Increment bit - Pointer Value Decrement bit

•

New Data Flag - the normal value of the new data flag is '0110. If a change of pointer value is needed, these bits will change to 1001, indicating to the distant end that the 10-bit pointer value has been changed.

•

TU Type - these two bits are set to '10' to indicate that the multiframe is carrying a TU-12 (2 Mbit/s) payload. A value of 00 indicates a TU-2 (6 Mbit/s) payload. A value of 11 indicates a TU-11 (1.5 Mbit/s) payload.

•

I and D bits are used to increment and decrement the existing pointer value, by inverting the bits as necessary.

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Training Manual NR1130/09/99/MCC _____________________________________________________________________

5.6.Multiplexing of TU-12 into a TUG-2 As can be seen from the previous section, each VC-12 consists of 144 bytes of information. Each frame has 36 bytes. These 36 bytes fill up exactly 4 columns of the STM-1 frame. 3 separate TU-12's are directly mapped together to form a TUG-2. Under ideal conditions the 3 TU-12's will fit exactly into 12 columns of the STM-1 frame as shown below:

TUG-2 = 12 Columns

VC ptr

VC ptr

VC ptr

SOH

AU Ptr

STM-1 Payload

SOH

TU-12 4 Columns

If the timing of a VC causes it to slip with respect to the timing of the TUG, the pointer is adjusted to indicate the new alignment The location of the pointer is fixed within the TUG-2 regardless of the position of the VC. A conceptual view of this is shown overleaf.

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Training Manual NR1130/09/99/MCC _____________________________________________________________________

TUG-2 = 12 Columns

VC ptr

VC ptr

VC ptr

SOH

AU Ptr

STM-1 Payload

SOH

TU-12 4 Columns

This diagram shows that although the VC pointer bytes are fixed within the TUG-2 structure, the VC-12 can span more than one STM-1 frame if necessary.

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Training Manual NR1130/09/99/MCC _____________________________________________________________________

5.7.Mapping of a TUG-2 into a TUG-3 signal. The mapping of TUG-2's into TUG-3's uses fixed byte interleaving and is shown below. The inclusion of the TUG-3 level is primarily to provide a structure for direct 34Mbit/s and 45Mbit/s input rates. A

B

C

TU-12

TUG-2

A

A B

A B

C

A B

C

A B

C

A B

C

A B

C

A B

C

(1)

A B

C

A B

C

A B

C

(2)

A B

C

A B

C

A B

C

A B

A B

C

C

(3)

B C

C

(7)

NPI 1

TUG-3

2

1 3

4

5

6

Stuffing 1

3 2

5 4

7 6

7

2

1 3

4

5

6

7

2

1 3

4

5

6

2

1 3

4

5

7

6

7

2

1 3

4

5

6

3

4

5

7

9

6

84

8

Each TUG-3 consists of 86 columns of information

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7 86

85

The 'Null Pointer Indicator' (NPI), is used to distinguish between TUG-3's which carry TUG-2's (2megs), and TUG-3's which carry VC-3 (34/45 Mbit/s) payloads. The NPI consists of the first 3 bytes of the first column of each TUG-3. The remaining bytes of this column and the entire second column are stuffing.

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Training Manual NR1130/09/99/MCC _____________________________________________________________________

5.8.Mapping of a TUG-3 into a VC-4 signal. SDH provides for fixed mapping from TUG-3 into a VC-4 container as shown in the diagram.

TUG-3

TUG-3 A

TUG-3 B

1

86

1

TUG-3 C

86

1

86

Stuffing POH

VC-4

A

P O H

A B

A B

C

1

3 2

5 4

C 7

6

A B

A B

C

C

9

A B

B C

C 259

8

261 260

The three TUG-3's are byte interleaved to form the VC-4 payload. At this point two columns of fixed stuffing are added and the 'VC-4 Path Overhead' is added to the start. These bytes together form the VC-4, which is 261 columns long.

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Training Manual NR1130/09/99/MCC _____________________________________________________________________

5.9.VC-4 Path Overhead. The VC-4 Path Overhead consists of one whole column of nine bytes as shown below. It forms the start of the VC-4 payload area. The POH contains control and status messages (similar to the V5 byte) at the higher order.

J1

Higher Order Path Trace

B3

Bit Interleaved Parity (BIP-8)

C2

Higher Order Signal Label (Composition)

G1

Higher Order Path Status

F2

Path User Channel (Payload dependent)

H4

Multiframe position indicator

Z3

Path User Channel (Payload dependent)

K3

Automatic Protection Switching

N1

Tandem Connection Monitoring

The function of the bytes is as follows: •

J1 - Higher Order Path trace. This byte is used to provide a fixed length user configurable string, which can be used to verify network topology connections. It is not supported by all manufactures.

•

B3 - Bit Interleaved Parity Check (BIP-8). This byte provides an error monitoring function for the VC-4 payload. It checks every bit in the VC-4 payload (not the POH). It looks at every 'bit1' in the payload and counts the number of binary 1's. If this number is even, a binary 0 is placed in the first bit of the BIP-8 byte. If the result of the count is an odd number of binary 1's, a binary 1 is placed in the first bit of the BIP-8 byte. This sequence is then repeated for all of the bit 2's in the payload, with the corresponding result being placed in the second bit of the BIP-8 byte. This continues with bit 3's in the third bit, bit 4's in the forth bit, etc until the entire VC-4 payload is checked.

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Training Manual NR1130/09/99/MCC _____________________________________________________________________ •

C2 - Higher Order Signal Label. (Container Composition). This byte indicates the composition of the VC-4 payload. A value of 0000 0010 indicates the VC-4 is carrying TUG structured data i.e. TUG-3’s. A value of 0001 0010 indicates the VC4 is carrying a C-4 i.e. a customers 140 Mbit/s PDH signal.

•

G1 - Higher Order Path Status. This byte is used to transmit path status information back to the distant end. It consists of 'RFI' and 'RDI' bits.

1

2

3 RFI

4

5 RDI

6

7

8

Spare

The RFI bits are used to report back to the distant end, the results of the BIP-8 check. This field has four bits with a total of eight values. If the BIP-8 check failed on the 'bit 1' count a value of 0001 is used. If it failed on the 'bit 2' check a value of 0010 is used. 'Bit 3', 0011 etc. This alarm is also known as HO FEBE or High Order Far End Bit Errors. The RDI field is used to indicate to the distant end that the multiplexer has an alarm condition (such as received path AIS in H1/H2, or loss of signal). In effect a loss of VC-4 frame alignment alarm. A binary 1 in this field indicates an alarm condition; a binary 0 indicates normality. This alarm is also known as HO FERF or High Order Far End Receiver Failure. The remaining three bits are spare. •

F2 -Path User Channel. This byte provides for a user communication channel. It is not currently used within Colt.

•

H4 - Multiframe Indicator. In VC mapping this byte indicates which frame of the multiframe is being transmitted (1 to 4).

•

Z3 -Path User Channel. This byte provides for a user communication channel. It is not currently used within Colt.

•

K3 -Automatic protection Switching (APS). Bits 1 to 4 provide for automatic protection switching control with VC-4 payloads. Bits 5 to 8 are spare.

•

N1 - Tandem Connection Monitoring. N1 is used to supply performancemonitoring data between the ends of a circuit that spans differing vendors (i.e. a Colt to BT circuit).

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Training Manual NR1130/09/99/MCC _____________________________________________________________________

5.10.Mapping of a VC-4 into an STM-1 frame. An AU pointer is added to the VC-4 to form an AU-4 or Administrative Unit -4. This pointer shows the phase alignment of the VC-4 with respect to the STM-1 frame. The AU pointers are in a fixed position within the STM-1 frame and are used to show the location of the first byte of the VC-4 POH, and also to provide a justification opportunity for VC-4 (140Mbit/s) payloads. The AU-4 is then mapped directly into an AUG or Administrative Unit Group, which then has the Section Overheads or SOH, added to it. These section overheads provide STM-1 framing, section performance monitoring and other maintenance functions pertaining to the section path. The VC-4 payload, plus AU pointers and Section Overheads, together form the complete STM-1 transport frame. 261 Columns (bytes) 10

270

J1 B3 C2

9

G1

VC-4 Frame

VC-4Payload

F2 H4 Z3

R o w s

K3 Z5

9 Columns (bytes)

261 Columns (bytes) 10

270

J1 B3 C2

9

G1

AU-4 Frame

AU PTR's

VC-4Payload

F2 H4 Z3

R o w s

K3 Z5

270 Columns (bytes) 1

9 10

1

RSOH

4

B3 C2

9

G1

3

STM-1 Frame

270

J1

AU PTR's

5

F2

VC-4Payload

H4

MSOH 9

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Z3

R o w s

K3 Z5

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Training Manual NR1130/09/99/MCC _____________________________________________________________________

5.11.AU Pointers. Because SDH can accept PCM signals at 140 Mbit/s directly into a VC-4 container there needs to be a mechanism to compensate for clock discrepancies between the SDH and PDH networks. The principles governing AU/VC-4 justification are identical to those of the lower order VC-12 signals. This justification process means that the VC-4 payload can move within the STM-1 frame format; therefore pointers are required to indicate the start of the VC-4. The AU pointer bytes are part of the STM-1 section overheads and comprise of H1 and H2 as pointer indicators and H3 as the negative justification opportunity. The H bytes are in multiples of three (to take into account AU-3 SONET mapping), but only the first byte of both the H1 and H2 bytes are used at VC-4 and the second and third bytes set to a null pointer indicator (NPI), a fixed bit pattern. The pointer value is the offset between the end of the H3 byte and the start of the VC-4 POH i.e. from the end of H3 to the start of the J1 byte. Because J1 can be anywhere (in-groups of three to take into account AU-3 SONET mapping), within the STM-1 payload area this AU pointer value can range from 0 to 782. The multiplexer will attempt to place the VC-4 frame at pointer value 522. This will fit the VC-4 directly into the STM-1 frame. There are occasions where due to justification processes the VC-4 will span across STM-1 frames as shown below. 522

MSOH 782 H1

H1

H1

H2

H2

H2

H3

H3

H3

0

-

-

-

-

1

J1 RSOH

P O H

VC-4 Payload

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Training Manual NR1130/09/99/MCC _____________________________________________________________________ When the VC-4 payload is placed in the AU-4 a value for the initial pointer will be calculated and placed in the H1 and H2 bytes. If a fault causes a break in the transmission path, it could result in a change of position of the J1 byte. This change needs to be transmitted to the distant end. If this is the case a new pointer value will be generated. The old pointer value is then incremented/decremented in steps, by a value of one each time, until it matches the new value required. Each single step in the pointer value represents a change of three bytes from the existing pointer value The AU pointer is shown below.

H1

• • • •

NPI

NPI

H2

1's

1's

H3

H3

H3

The first byte of H1 and H2 are used to hold the AU pointer value The remaining two bytes of H1 hold a Null Pointer Indicator of 1001SS11 (where SS is unspecified). The remaining two bytes of H2 hold all one's H3 provides either stuffing or data bits for justification.

The first byte of H1 and H2 are shown in detail below:

First H1 byte

1

2

3

4

First H2 byte

5

6

7

8

1

2

3

4

5

6

7

8

N N N N S

S

I

D

I

D

I

D

I

D

I

D

10 bit pointer value

NNNN SS I D

- New Data Flag - Null Pointer Indicator - Pointer Value Increment bit - Pointer Value Decrement bit

•

New Data Flag - the normal value of the new data flag is '0110. If a change of pointer value is needed, these bits will change to 1001, indicating to the distant end that the 10-bit pointer value has been changed.

•

Null Pointer Indicator.

•

I and D bits are used to increment and decrement the existing pointer value, by inverting the bits as necessary.

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Training Manual NR1130/09/99/MCC _____________________________________________________________________

5.12.VC-4 Justification As SDH caters for customer input rates of 140Mbit/s directly some form of justification is needed at the VC-4 level. This is achieved by using the 3 bytes of H3 and the next 3 bytes immediately following H3. The justification takes place in frame number 3, of a 4 frame multiframe. Justification control is via a buffer system (as opposed to the control bits (C1, C2) in VC-12 justification). The incoming data is fed into a buffer. This buffer has two threshold levels. A 'low fill' level for slow rates and a 'high fill' threshold for fast data. When these thresholds are met, the H3 bytes and the 3 bytes immediately following are set accordingly. If the customer data is being received at a faster rate than normal, the 3 bytes of H3 are used for customer data. This is known as negative justification.

J1 MSOH

Negative justification (Customer data runing fast).

H1

H1

H1

H2

H2

H2

D

D

D

RSOH

If the customer data is being received at a slower rate than normal, the 3 bytes immediately following H3 are used for padding. This is known as Positive justification.

J1 MSOH

Positive justification (Customer data runing slow).

H1

H1

H1

H2

H2

H2

H3

H3

H3

S

S

S

RSOH

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Training Manual NR1130/09/99/MCC _____________________________________________________________________

5.13.STM-1 Section Overheads The STM-1 Section Overhead (SOH) consists of nine columns by nine rows as shown below. It forms the start of the STM-1 frame. The SOH contains control and status messages (similar to the V5 and VC-4 POH) at the transmission section level. The STM-1 section overhead is divided up into two parts. •

The first is the Regenerator Section Overhead (RSOH).

•

The second is the Multiplexer Section Overhead (MSOH).

R S O H AU-4 Pointer and Justification Opportunity

M S O H

A1

A1

A1

A2

A2

A2

J0

B1

E1

F1

D1

D2

D3

H1

H1

H1

H2

B2

B2

B2

K1

K2

D4

D5

D6

D7

D8

D9

D10

D11

D12

S1

Z1

Z1

Z2

H2

Z2

H2

M1

H3

H3

H3

E2

A1, A2 - Framing bytes (A1=11110110, A2=00101000) B1 - Bit Interleaved Parity 8 (BIP-8) B2 - Bit Interleaved Parity 24 (BIP-24) J0 - Section Path Trace D1-D12 - Data Control Channel E1, E2 - Engineering Order Wire channel F1 - Maintenance Channel H1, H2, H3 - AU Pointers/Justification opportunity K1, K2 - Automatic Protection Switching S1 - Synchronisation Status Monitor Z1, Z2 - Spare M1 - Multiplexer Section REI (FEBE)

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Training Manual NR1130/09/99/MCC _____________________________________________________________________ • A1 & A2 - STM-1 Frame Alignment. These 6 bytes are used for STM-1 frame alignment. They are the first bytes transmitted. The A1 bytes have a value of F6 (hex) or binary 11110110. The A2 bytes have a value of 28 (hex) or binary 00101000. Frame alignment takes place over three STM-1 frames. •

J0 - STM-1 Section Path Trace. This byte is used to provide a fixed length user configurable string, which can be used to verify network topology connections. It is not supported by all manufactures.

•

B1 - Byte Interleaved Parity Check 8 (BIP-8). This byte provides an error monitoring function for the entire STM-1 frame after scrambling (2B1Q). It checks every bit in the STM-1 frame. It looks at every 'bit1' in the frame and counts the number of binary 1's. If this number is even, a binary 0 is placed in the first bit of the BIP-8 byte. If the result of the count is an odd number of binary 1's, a binary 1 is placed in the first bit of the BIP-8 byte. The sequence is then repeated for all of the bit 2's in the frame, with the corresponding result being placed in the second bit of the BIP-8 byte. This continues with bit 3's in the third bit, bit 4's in the forth bit, etc until the entire STM-1 frame has been checked.

•

E1 - Engineering Order Wire. This byte is used to provide a 64 kbit/s voice channel, within the regenerator section, for use in maintenance applications.

•

F1 – Maintenance Channel. This byte is used to convey back to the distant end a count of any errors detected by the BIP-8 error check in byte B1.

•

D1 to D3 - Data Communications Channel (DCC). These 3 bytes provide a 192 kbit/s data channel for the use of network management systems.

•

B2 - Byte Interleaved Parity Check 24 (BIP-24). These 3 bytes provide an error monitoring function for the STM-1 frame (excluding the RSOH), before scrambling. The frame is divided up into 3 byte chunks. Each chunk is then parity checked in the same manner as the BIP-8 check. The bit1 results are placed in the bit one's of the relevant BIP-24 byte. The bit2 results are placed in the bit two's of the relevant BIP24 byte etc etc. A comparison between the BIP-8 and BIP-24 checks reveal if there were any scrambling errors (2B1Q).

•

K1 - Automatic protection Switching (APS). This byte is used to perform automatic protection switching of the multiplexer section (MSP switching).

•

K2 - Automatic protection Switching (APS). This byte is used to convey a Multiplex Section Remote Defect Indication or MS RDI (formerly MS FERF).

•

D4 to D12 - Data Communications Channel (DCC). These 9 bytes provide a 576 kbit/s data channel for the use of network management systems.

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Training Manual NR1130/09/99/MCC _____________________________________________________________________ • S1 - Synchronisation Status Message. Bits 5, 6, 7 and 8 of the S1 byte provide a quality indication of the received clock synchronisation signal. 0000 - indicates a quality unknown message. 0010 - indicates a G.811 Primary reference clock with an error rate of greater than 1x10-11 per day. 1011 - indicates a G.813 Internally generated reference clock. 1111 - indicates a 'Do not use for Synchronisation' message. •

Z1, Z2 - Reserved. These four bytes are spare and reserved for future use.

•

M1 - Multiplex Section Remote Defect Indicator (MS RDI). This byte is used to convey back to the distant end a count of any errors detected by the BIP-24 error check. A value of 00000000 indicates zero errors. A value of 00011000 indicates an error count of 24 etc. This was formerly known as MS FEBE.

•

E2 - Engineering Order Wire. This byte is used to provide a 64 kbit/s voice channel, within the multiplexer section, for use in maintenance applications.

•

X - Reserved. These bytes are reserved for national use.

All unmarked bytes are reserved for future international standardisation.

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Training Manual NR1130/09/99/MCC _____________________________________________________________________

6. Appendix A - STM-n Frame Structure There is a common misconception that an STM-n signal is formed by byte interleaving 'n' number of STM-1 streams directly together. In fact it is not the streams that are multiplexed, but the AUG's within them. The individual section overheads, of the original STM-1 streams, are removed; the AUG's are then interleaved together and a new section overhead for the STM-n signal is calculated.

6.1.STM-4 Frame Structure. The STM-4 frame comprises of 9720 bytes. This can be shown as a structure of 1080 columns by 9 rows as shown below. 1

1

261

9

AU PTR's

1

1

AUG #1

1

261

1

9

9

1

AUG #2

AU PTR's

261

AU PTR's

1

1

AUG #3

261

9

AU PTR's

AUG #4

1080

36 37

1234123412341234

1

SOH 12341234

SOH 9

4 X9

4 X 261

The payload area consists of the four, byte interleaved, VC-4's streams. The original AU pointers are byte interleaved and added along with a recalculated section overhead to the front of the payload. The recalculated SOH contains the original framing (A1&A2), and B2 (BIP-24) bytes stripped from each of the individual STM-1 streams. The remainder of the SOH is created from fresh. The section overheads occupy columns 1 to 36. The STM-4 payload occupies columns 37 to 1080 1

36

1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 C1 Z

B1 D1

Z Z X X X X X X X X F1 X X X X X X X X X X X D3

E1 D2 AU POINTERS

B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 K1 D4 D5 D7 D8

K2 D6 D9

D10

D12

D11

9 S1 Z1 Z1 Z1 Z1 Z1 Z1 Z1 Z1 Z1 Z1 Z1 Z2 Z2 Z2 Z2 Z2 Z2 Z2 Z2 Z2 Z2 Z2 Z2 E2 X

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Training Manual NR1130/09/99/MCC _____________________________________________________________________

6.2.STM-16 Frame Structure. The STM-16 frame comprises of 38880 bytes. This can be shown as a structure of 4320 columns by 9 rows as shown below. The payload area consists of the sixteen, byte interleaved, VC-4's streams. The original AU pointers are byte interleaved and added along with a recalculated section overhead to the front of the payload.

1

1

261

1

9

1

AUG #1

AU PTR's

1

261

1

9

9

1

AUG #2

AU PTR's

261

AUG #16

AU PTR's

4320

144 145

12345678910111213141516

1

SOH 12345678…..16 1234…16 12

SOH 9

16 X 9

16 X 261

The recalculated SOH contains the original framing (A1&A2), and B2 (BIP-24) bytes stripped from each of the individual STM-1 streams. The remainder of the SOH is created from fresh. The section overheads occupy columns 1 to 144. The STM-16 payload occupies columns 145 to 4320.

1

4

7

10

13

16 19

22

25 28

31

34

37

40

43

46

49

52

55

58

61

64

67

70

73

76

79

82

85

88

91

94

. Z F1 X D3 97

1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 C1

B1 D1

E1 D2

. Z X

. Z X

. X X

. X X

. 144 X X X X

X

X

X

X

X

AU POINTERS B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 K1 D4 D5 D7 D8

K2 D6 D9

D10

D12

D11

9 S1 Z1 Z1 Z1 Z1 Z1 Z1 Z1 Z1 Z1 Z1 Z1 Z1 Z1 Z1 Z1 Z2 Z2 Z2 Z2 Z2 Z2 Z2 Z2 Z2 Z2 Z2 Z2 Z2 Z2 Z2 Z2 E2

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Training Manual NR1130/09/99/MCC _____________________________________________________________________

7. Appendix B - Circuit labelling and rates look up table PDH/SDH Multiplexing Rates Circuit Bandwidth (Bits/Second) 64k 1.5M 2M 6M 8M 34M 45M 140M 155M 622M 2.5G 10G 40G

COLT Label E0 E1 E2 E3 T3 E4 E5 E6 E7 E8 E9

European Label (ITU-T) E0 E1 E2 E3 E4 STM-1 STM-4 STM-16 STM-64 STM-256

American Label (ANSI) DS0 T1 (DS1) T2 (DS2) T3 (DS3) OC-3 OC-12 OC-48 OC-192 OC-768

64 kBit/s Equivalents (VGE's) 1 24 30 90 120 480 672 1,890 1,890 7,560 30,240 120,960 483,840

2 Mbit/s Equivalents 1 2 4 21 21 63 63 252 1,008 4,032 16,128

Actual Bandwidth (Bits/Second) 64,000 1,544,000 2,048,000 6,176,000 8,448,000 34,368,000 44,736,000 139,920,000 155,520,000 622,080,000 2,488,320,000 9,953,280,000 39,813,120,000

Wave Division Multiplexing Rates Voice Number of wavelengths Channels (λ) (VGE) 8λ x STM-64 967,680 16λ x STM-64 1,935,360 32λ x STM-64 3,870,720 120λ x STM-64 14,515,200

Equivalent Bandwidth (Bits/Second) 79,626,240,000 159,252,480,000 318,504,960,000 1,194,393,600,000

80G 160G 320G 1.2T

Note. WDM wavelengths can be any bit rate. The table above is an example of current maximum transmission capacity. The theoretical maximum transmission capacity of a fiber is approximately 25T bits per second. (25,000,000,000,000)

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Training Manual NR1130/09/99/MCC _____________________________________________________________________

8. Appendix C - The Electromagnetic Spectrum Electromagnetic Spectrum Visible Light Cosmic radiation

T radiation

UV radiation

Communications radiation

IR radiation

X ray radiation

Frequency (Hz)

1020

Microwave, Radar

1018

1016

1014

1012

Wavelength (m)

1010

(1 THz)

250 THz

TV

VHF

SW

108

106

(1 GHz)

(1 MHz)

10 -12

10 -9

10 -6

10 -3

10 -0

102

(1 pm)

(1 nm)

(1 um)

(1 mm)

(1 m)

(100 m)

Fiber Transmission wavelength range

Visible Light

0.4

0.5

0.6

0.7 670

0.8 780

0.9

1.0

1.1

1.2

850

1.3

1.4

1300

1.5

1.6 1550

um

1625 nm

Attenuation coefficiant of silica fibers 10 1st window

2nd window

3rd window

Attenuation/dB

Multimode Fiber Singlemode Fiber IR absorbtion

1

Rayleigh scattering

0.1

800

1000

1200

1400

1600

Wavelength/nm

Fiber optic transmission makes use of three optical windows (850, 1300, 1550 nm), where the attenuation characteristics of silica fibers are the lowest. 670nm light is used for visible fault location, with 780 nm and 1625 nm lasers used for shorthaul and long haul applications respectivly.

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