Ch2 The Well

Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition By R. Jacob Baker, Copyright Wiley-IEEE n-well Flip chip

Chip

p-type epi layer (p-)

on its side and enlarge p-type substrate (p+)

MOSFETs are not shown. n-well p-substrate

Usually, we will not show the epitaxial layer. Many processes don't use the epi layer.

Figure 2.1 The top (layout) and side (cross-sectional) view of a die.

Substrate connection

Resistor leads

n-well Shows parasitic diode p-substrate Figure 2.2 The n-well can be used as a resistor.

Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition

A

A

B

For cross section, cut along dotted line

(a) Unprocessed wafer A

B

p-type (b) Cross-sectional view of (a) A

B

B

Oxide

p-type

p-type

(c) Grow oxide (glass or SiO2) on wafer. A

Photoresist Oxide

B

(d) Deposit photoresist A

B Mask Photoresist Oxide

Top view Side view p-type (e) Mask made resulting from layout.

(f) Placement of the mask over the wafer.

Ultraviolet light Mask (reticle) Photoresist Oxide

p-type

Photoresist Oxide

p-type (h) Developing exposed photoresist.

(g) Exposing photoresist. Photoresist Oxide

p-type (i) Etching oxide to expose wafer.

Oxide

p-type (j) Removal of photoresist.

Figure 2.3 Generic sequence of events used in photo patterning.

Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition By R. Jacob Baker, Copyright Wiley-IEEE

SiO 2 x Si

Top of the wafer before oxidation

x ox

Top of the wafer after oxidation

p-substrate Figure 2.4 How growing oxide consumes silicon.

Diffusion of donor atoms Resist

p-type

Start of diffusion into the wafer

(a) Diffusion of donor atoms Resist n-well p-type (b) After diffusion p-type n-well (d) Angled view of n-well p-type (c) After resist removal Figure 2.5 Formation of the n-well.

Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition By R. Jacob Baker, Copyright Wiley-IEEE

10

Cross section shown below 10 n-well

p-substrate Figure 2.6 Layout and cross-sectional view of a 10 by 10 (drawn) n-well.

Width

Width Spacing Cross section shown below

Design rules: width of the n-well must be at least 6 while spacing should be at least 9. n-well

n-well p-substrate

Parasitic npn bipolar transistor Figure 2.7 Sample design rules for the n-well.

Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition By R. Jacob Baker, Copyright Wiley-IEEE

W L

B t

A

Layout view W

L

A

B

Figure 2.8 Calculation of the resistance of a rectangular block of material.

B

Layout (top view) 2

B

3

1 (a)

(b) A A

Figure 2.9 (a) Calculating the resistance of a corner section and (b) layout to avoid corners.

Metal

FOX

n+

Metal FOX

n+ n-well

p+ field implant

n+ field implant

FOX

n+ active implant

p-substrate

Figure 2.10 Cross-sectional view of n-well showing field implant. The field implantation is sometimes called the "channel stop implant."

Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition By R. Jacob Baker, Copyright Wiley-IEEE

electron

Ec

Eg Ev hole Figure 2.11 An electron moving to the conduction band, leaving behind a hole in the valence band.

Ec

Ec

Ec

Ei

Ei

Ei

Ev

E fp Ev

Ev

(a) Intrinsic silicon

(c) n-type silicon

(b) p-type silicon

Ec q ⋅ V bi Ef

Ec Ev

p-type

n-type

Ev (d) A pn-junction diode Figure 2.12 The Fermi energy levels in various structures.

E fn

Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition By R. Jacob Baker, Copyright Wiley-IEEE

Anode, A

Cathode, K

VD n-type

p-type + + Depletion + region + + + + Two plates of a capacitor

Figure 2.13 Depletion region formation in a pn junction.

Vd n-well Sidewall capacitance

Bottom capacitance

p-substrate Figure 2.14 A pn junction on the bottom and sides of the junction.

C j , diode depletion capacitance C j0 , zero-bias depletion capacitance 1.12 pF

0

V D , diode voltage

Figure 2.15 Diode depletion capacitance against diode reverse voltage.

Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition By R. Jacob Baker, Copyright Wiley-IEEE Storage or diffusion capacitance

Metal contact p-type

n-type

Minority carriers Figure 2.16 Charge distribution in a forward-biased diode.

R

V F − 0.7 R

I

VF

I

Diode current Diode voltage

0.7

VR V R − 0.7 R

t1

time

t2 t3

VR

Figure 2.17 Diode reverse recovery test circuit.

1k

V IN

+10

ID

VD

10

Figure 2.18 Circuit used in Ex. 2.4 to demonstrate simulation of a diode's reverse recovery time.

Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition By R. Jacob Baker, Copyright Wiley-IEEE

Table 2.1 SPICE parameters related to diode.

Name

SPICE

IS

IS

Saturation current

RS

RS

Series resistance

n

N

Emission coefficient

Vbd

BV

Breakdown voltage

Ibd

IBV

Current which flows during Vbd

Cj0

CJ0

Zero-bias pn junction capacitance

Vbi

VJ

Built-in potential

m

M

Grading coefficient

τT

TT

Carrier transit time

Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition By R. Jacob Baker, Copyright Wiley-IEEE V IN ts

RC time is

≈ 1k ⋅ 1p = 1 ns I D (mA) VD I D (mA) Figure 2.19 The simulation results for Ex. 2.4.

(a)

Pulse in

Pulse out R determined by the sheet resistance of the n-well

n-well p-type Substrate tied to the lowest potential in the circuit, in this case ground C determined by the depletion capacitance of the n-well R Input Output (b) C Substrate connection

Figure 2.20 (a) Parasitic resistance and capacitance of the n-well and (b) schematic symbol.

Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition By R. Jacob Baker, Copyright Wiley-IEEE

Input pulse in

R

out C

input pulse

0 to V pulse

0.9V pulse 0.5V pulse 0.1V pulse

V pulse Output pulse 0

0

time

Delay time

t d = 0.7RC

Rise time

t r = 2.2RC

Figure 2.21 Rise and delay times in an RC circuit.

R square A

in

R square B C square

R square C C square

R square C square

out

C square

Figure 2.22 Calculating the delay through a distributed RC delay.

in

out

22 ns

time

*** Figure 2.23 CMOS: Circuit Design, Layout, and Simulation *** .control destroy all run plot vin vout .endc .tran 100p 100n O1 Vin 0 Vout 0 TRC Rload Vout 0 1G Vin vin 0 DC 0 pulse 0 1 5n 0 .model TRC ltra R=5k C=5f len=50 .end

Figure 2.23 SPICE simulations showing the delay through an n-well resistor.

Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition By R. Jacob Baker, Copyright Wiley-IEEE

n-well

(a) n-well process p-substrate

p-well

(b) p-well process n-substrate

p-well

n-well

(c) Twin-well process

p- or n-substrate (lightly doped)

p-well

n-well2

n-well1

(d) Triple-well process using p-substrate

p-substrate (lightly doped)

Figure 2.24 The different possible wells used in a bulk CMOS process.

Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition By R. Jacob Baker, Copyright Wiley-IEEE

1.2 n-well 1.4

1.3 n-well

n-well

1.1

p-well Figure 2.25 Layouts showing the MOSIS design rules for the n-well.

p-well

deep n-well p-substrate

Figure 2.26 SEM image showing the cross-section of a CMOS memory chip.

Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition By R. Jacob Baker, Copyright Wiley-IEEE

Cross-section

Cross-section

Figure 2.27 Layout used in problem 2.1.

Figure 2.28 Layout of an n-well resistor using a serpentine pattern.

Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition By R. Jacob Baker, Copyright Wiley-IEEE

v out 1V

v in 1 mV

10 k n-well Substrate

Figure 2.29 Treating the diode as a capacitor. See Problem 2.7.