Ccg

CENTAL CLOCK GENERATOR)

CENTRAL CLOCK GENERATOR • In order to switch and transmit digital information the sequence of operations must be synchronous throughout the equipment involved. • This requires a clock supply with a high level of reliability, precision and consistency for the exchanges in the digital network. • In EWSD exchanges, this function is performed by the central clock generator-A (CCG(A))

LTG DLU

SN

LTG LTG CCG (A)1

MB (1)

(CDEX, if provided) CCG (A)0

MB (0)

Coordination processor

POSITION OF THE CCG(A) IN EWSD

CENTRAL CLOCK GENERATOR In view of its vital role in the exchange, the CCG(A) is always duplicated • Only master CCG(A) supplies the connected equipment (MB,CP &CDEX, if provided) with the synchronization clock. • The slave CCG, however, controlled by the master CCG, operates in phase synchronism. • This ensures that in the event of a malfunction or failure affecting the master CCG, the slave can be given the role of the master immediately

CENTRAL CLOCK GENERATOR • Clock distribution within the exchange also proceeds on a master/slave basis. • Each equipment unit shown in the Fig. generates fresh synchronization pulses, which it synchronizes with the output pulses of the equipment preceding it, in order to then synchronize the equipment following it. • The clock pulses generated in each equipment unit synchronize the information exchange on three levels: within the equipment unit, from one equipment unit to another, and from one exchange to another.

SYNCHRONOUS, HIERARCHICAL DIGITAL ETWORK Standard frequency system EXCH. A

EXCH. C

EXCHANGE C DIU

Network layer 0

EXCH. D

Network layer 1

Clock of PCM link

Network layer n

CCG 0/1

PCM 30 from Exch. A DIU PCM 30 from Exch. D

PCM LINKS

EXCH. B

External reference frequency

Clock of PCM link

FUNCTIONS OF CCG MODULES OF CCG are as under

∀ • MODULE XXA

(CCGXXA),

∀ •

MODULE B

(CCGB)

∀ •

MODULE D

(CCGD).

• SYNCHRONOUS OPERATION : •

MODULE CCGXXA GENERATES THE REF. CLOCK (FO1) FOR MODULE CCGB AND SYNCHRONIZES IT TO ONE OF THE TWO EXTL. REF. FREQ. FED IN AT ITS INPUT. • THE MODULES CCGB0 AND CCGD0 AMPLIFY THE OUTPUT CLOCK (SYCLK0) AND TRANSFER IT TO THE FOLLOWING EQUIPMENT: • - SYCLK0 TO THE MB-0 AND MB-1 • - SYCLK0 TO THE COORDINATION PROCESSOR (CP113), - SYCLK0 TO TWO CDEXS, IF PROVIDED.

fR0 fR3

CCG XXA0

CCG(A)0 SYCLK0 MB(B)0, MB(B)1 fO1 CCGB0 SYCLK0 CP113 fO2 SYCLK0 CDEX0, CDEX1 SYCLK0 Reserve CCG D0 CCG(A)1 C CGD1

fR2 fR1

CCG XXA1

fO2 fO1

CCG B1

SYCLK0 MB(B)0,MB(B)1 SYCLK0 Reserve Reserve MB(B)0, MB(B)1

Reserve CDEX0, CDEX1 CP MB(B)0, MB(B)1

CCG(A) FOR SYNCHRONOUS OPERATION

PLESIOCHRONOUS OPERATION Here CCGs operate without extl. ref. frequency

fR40

CCG XXA0

CCG(A)0 SYCLK0 MB(B)0, MB(B)1 fO1 CCGB0 SYCLK0 CP113 fO2 SYCLK0 CDEX0, CDEX1 SYCLK0 Reserve CCG D0 CCG(A)1 C CGD1

CCG XXA1

fO2 fO1

CCG B1

SYCLK0 MB(B)0,MB(B)1 SYCLK0 Reserve Reserve MB(B)0, MB(B)1

Reserve CDEX0, CDEX1 CP MB(B)0, MB(B)1

CCG(A) FOR PLESIOCHRONOUS OPERATION

SYNCHRONOUS OPERATION WITH TWO EXTERNAL REF. FREQUENCIES The precision of the CCG output clocks here depending on the tolerance of fR, is as follows : In national synchronous networks with international digital traffic and synchronization of the master exchanges by Cs standards: |∆fR|/fR<10-11 In national synchronous networks without international digital traffic and synchronization by plesiochronously operated CCGs in the master exchanges: |∆fR|/fR< 10-8 to 10-9;

RACK FOR CCG(A) FUSE PANEL F:MB/CCG(B) F:MB/CCG(B)

SYSTEM PANEL CONTROL / CLOCK DISTRIBUTORS EXTL

F:MB/CCG(B) F:MB/CCG(B)

Rack for MB, CCG(A), SYPC and CDEXs

MODULE FRAMES FOR CCG

MBU:SGC MBU:LTG

D C C

T/ R C 3

T/ R C 2

T/ R C 1

MBU:LTG

T/ R C 0

M D M

I O P C

C G / M U X

M D M

T/ R C 0

Module frame for MB(B) and CCG

T/ R C 1

CCG(A)

T/ R C 2

T/ R C 3

(F:MB/CCG(B))

C C G D

C C G B

C C G X X A

D C C

MODULE FRAMES FOR CCG

D C C

I O C : S Y P C

C O M : S Y P C

T/ R R M M : S E Y A P C 0

T/ R M S Y P C 1

T X A : S Y P C

C D E X 0

C D E X 1

C D E X 2

C D E X 3

C D E X 4

C D E X 5

C D E X 6

C D E X 7

C D E X 8

C D E X 9

MODULE FRAME A FOR SYSTEM PANEL CONTROL AND CLOCK DISTRIBUTORS EXTERNAL, (F:SYPC(A))

D C C

DLU

LTG

LCLK, LFS*)

GCG

CLK0’, FMB0’

BDCG0 LTG

LCLK, LFS*)

BDCG1

fR1 fR2 ST1

GCG

CLK1’, FMB1’

CCNC

CLK0’, FMB0’

MUXMA0 MUXMB0 MUXMA1 MUXMB1

CCG (A)1

MB(B)1

CDEX1

CG/MUX1

ST2 CDEX2

S N 1

S N 0

CLK1’, FMB1’ CLK1, FMB1

SYCLK0 ST9 CDEX9

MST1

MST0

ST0

SYCLK0

CDEX0 SYCLK0

CCG (A)0

fR3 fR0

SYCLK0 IOP:TA0

MB(B)0

SYCLK 0 SYCLK1

CG/MUX0

CLK0, FMB0 S GCB

CP

IOP:TA1

Clock distribution in exchanges

S GCB

CLOCKS GENERATED/ USED IN EXCHs -The synchronization clock (SYCLK) at a rated frequency of 8 kHz (corresponding to a period of 125 µs) and a pulse duty ratio of 1:1 -The exchange clock (CLK) at a rated frequency of 8,192 kHz (corresponding to a period of 122 ns) and a pulse duty ratio of 1:1. -The frame mark bit (FMB) at 2,000 pulses per second with a pulse length of 122 ns. -The line clock (LCLK) for PCM30 multiplex lines at a rated frequency of 2,048 kHz (corresponding to a period of 488ns) and a pulse duty ratio of 1:1. -The line frame signal (LFS) for PCM30 multiplex lines to 4,000 pulses per second with a pulse length of 488 ns.

CLOCK SYNCHRONIZATION IN CCG (A) There are two inputs available on each of the central clock generators 0 and 1 for the purpose of feeding in external reference frequencies . The input options are as follows: - Analog pilot frequencies via the associated carrier frequency terminating units Standard values of 300 or 308 kHz - Digital control clocks via the associated digital interface units, Standard values of 2,048 kHz (for PCM30) or 1,544 kHz) - Standard frequencies, for master exchanges, direct from the atomic frequency standard (e.g. Cs standards), Standard values of 5 or 10 MHz.

CLOCK SYNCHRONIZATION IN CCG (A)

• Depending on the CCGXXA switch setting one of the two fRs is used for CCG synchronization • The selected IMs, corresponding to the fRs connected, are specified by the 2-character code XX in the module designation CCGXXA. technologies. The possible values of X and their meaning are listed below: - X=0 for free running (no fR) - X=1 for fR = 300 kHz and 2,048 kHz, - X=2 for fR = 5 MHz and 10 MHz, and - X=3 for fR = 308 kHz & 1,544 kHz (for PCM24).

CLOCK SYNCHRONIZATION IN CCG(A) fR0

CCG(A)0

fR0

CCG(A)0

CCG(A)1

fR2

CCG(A)1

fR0

CCG(A)0

fR0

CCG(A)0

fR3

fR2 fR1

(a) Four different fR values

fR1 (b)Three different fR values

CCG(A)1

CCG(A)1

fR1 (c) Two different fR values

(d) for one fR

Connection options for the external reference frequencies to the CCG(A)

MML-COMMAND FOR CCG MAINTENANCE. STAT CCG CONF CCG DISP CCG

-STAT CCG; CCG-0 ACT

CCG-1 STB

MML-COMMAND FOR CCG MTCE. •

DISP CCG;

STATUS AND ERROR INFORMATION : • •

• • • • • • • • • • • • • •

CCG-0

CCG-1

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REF. FREQUENCIES AT CCGXXA : CCGXXA-MODULE CCGXXA-PROCESSOR : CCGB-MODULE : CCGB-PROCESSOR : INTERFACE CCGXXA/CCGB : CCGB MS-STATUS : CCGB CLOCK DISTRIBUTOR : OPERATIONAL STATUS : REFERENCE FREQUENCY 0 : REFERENCE FREQUENCY 1 : USED REFERENCE FREQUENCY : STATUS FREQUENCY STORAGE : SYNCHRONIZATION STATUS :

PRESENT FAULT FREE FAULT FREE FAULT FREE FAULT FREE FAULT FREE MASTER ENABLE ACT GOOD GOOD 0 NORMAL SYNCHRON 4

PRESENT FAULT FREE FAULT FREE FAULT FREE FAULT FREE FAULT FREE SLAVE ENABLE STB GOOD GOOD 1 NORMAL SYNCHRON 4

DIAGNOSIS AND TESTS • DIAGNOSIS • It is not possible for operating personnel to start a CCG diagnosis. The diagnostic functions for CCG are carried out during configuration from MBL (or UNA) to STB. During this state transi-tion, the first part of the CCG-ROUT-TEST is triggered, which performs a general check of CCG functions and the CCG's internal fault indicators . •

TESTS

• It is not possible for the operating personnel to perform an on line test of the CCG. This would be superfluous, since a test of this kind is already performed by the CP, with the internal fault indicators, the inservice supervision and the daily ROUT-TEST

CENTRAL CONTROL GENERATOR

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