Cad Tools For Signal Integrity Analysis Of Mixed-signal Asics

“CAD Tools for Signal Integrity Analysis of Mixed-Signal ICs"

Nishath Verghese Cadence Design Systems

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Outline • Introduction to signal integrity – Definitions – How failures happen

• Noise Solutions for Analog functionality • Noise Solutions for Digital functionality

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What is signal integrity? Design with signal integrity implies preservation of the intended behavior of a circuit in the presence of noise

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What is noise? Physical noise sources •

Thermal noise. Open-circuit mean-square voltage is:

Vn2 = 4kTBR • •

Flicker or 1/f noise. In MOS devices, due to interface traps. Shot noise. For a pn junction, the mean-square noise current is:

in2 = 2qBI These sources are random; that is, they cannot be predicted at any time even if the past values are known. C

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What is noise? Man-made (or environmental) noise sources • • •

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Are deterministic although a stochastic model may be appropriate in some cases. Can be orders of magnitude larger than physical noise sources. For CMOS digital circuits, noise is any deviation in the analog voltage from the nominal supply or ground rails when the node should represent a stable logic ‘0’ or ‘1’ value.

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Where does noise come from? • A mixed-signal l IC is a very noisy place – Logic signals switching from Gnd->Vdd, Vdd->Gnd couple to other quiet or switching nets through unintended “couplings” • Analog always vulnerable • Noise immunity used to win out over noisiness for digital circuits • What are these “couplings”?

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Why are noise problems getting worse? Louder talkers •

Interconnect scaling – More levels of interconnect packed closer together. – Metal thickness remains constant because of resistance – In scaling from 1.8 um to 0.9 um pitch, line-to-line capacitance increases from 46% to 68% of full-loaded self-capacitance.

• •

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Faster clock frequencies and slew times Higher current density demands

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Why are noise problems getting worse? More talkers and listeners • •

SOC requirement of mixing analog/RF and digital together on the same chip. Design scaling – More talkers and listeners packed closer together.

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Why are noise problems getting worse? More ”noise-sensitive” listeners • •

Lower supply voltages => Lower noise margin for analog circuits Performance requirements are pushing designs toward the use of more “highgain” digital circuits, which are more sensitive to noise.

Dynamic node

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Mixed-signal system noise issues Digital Noise Coupling

Channel Noise

IF L.O.

Device Noise RF Filter

ADC BaseBand IF Filter

LNA

ProcADC essing

Digital Noise Coupling

Phase Noise RF L.O.

IF L.O.

Mixed Signal Wireless IC C

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d a t a o u t

Noise impact on analog functionality Output buffers

Simultaneous switching of the output buffers creates substrate noise that corrupts the A2D conversion

ERR MSB COR COMP

LSB MUX

ADC

LSB COMP

ADC

ADC

8 bit Video A2D Converter

Expected Actual response response C

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ADC Codes

RES STRING

Samples

Noise impact on digital functionality 1

0

1

Noise propagates

0

Coupling through FETs

0 0

Power-supply and substrate coupling Non-full-rail signalling

1 Interconnect coupling

Logic signal of interest has settled down when coupling interactions disturb the voltage representing the logic value. C

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Noise impact on digital timing 1

0

1

0 At the same time consider simultaneous switching effects.

Noise can make you go faster or slower. Noise effects are the same, just against switching rather than static signals. C

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Key point • As circuit designs (or device designers), we focus primarily on the devices • Noise issues force us to really put the focus on the wires, the substrate, and the entire electrical environment of the chip (package, etc) in addition to the devices

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Outline • Introduction to signal integrity – Definitions – How failures happen

• Noise Solutions for Analog functionality • Noise Solutions for Digital functionality

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How noise couples to analog circuitry Due to physical isolation of analog circuitry, noise couples mostly through common substrate • From the digital power supply • From switching source-drain nodes • From Impact ionization in the MOSFET channel

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Sources of Substrate Noise • Currents from device junctions and channel • Supply currents injected into the substrate through substrate contacts

Package

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Factors Influencing Substrate Noise Problems • • • • • • • • •

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Process choice (twin well vs. triple well) Doping profile (substrate resistivity) Floorplan Location of contacts To predict substrate noise, all factors need to Location of noise injectors be considered Package Impedance Power/GND distribution Switching activity Noise margin of sensitive circuitry

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Triple well process

p well n well p substrate

Also trench isolation and SOI.

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Effects of Substrate Noise on Devices • Body effect – Substrate noise modulates the threshold voltage of devices – e.g. NMOS transistors Vth = Vt0 + γ ( 2Φf + V SB - 2Φf ) VSB - source to body voltage Φf - Fermi level Vt0 - zero bias threshold voltage – Drain voltage and drain currents of device vary linearly and as the square of the threshold voltage, respectively – Spikes in VSB result in spikes in drain voltage and current – In general analog circuits are much more sensitive to this effect than digital circuits

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Techniques for minimizing substrate interaction

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Techniques to Mitigate Substrate Noise: Effective Use of Guard Rings Guard rings Noisy Supply

Zpd

digital

analog

Zpa

+ -

Zs

substrate

noise coupling

• Guard rings can increase substrate noise •For example if Zs < Zpd adding guard rings increases noise at the analog circuit •Inject substrate noise if tied to a noisy supply C

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Modeling Substrate Noise

Digital

Analog

Package

Substrate C

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Components of Substrate Noise Analysis: Extracting the Substrate • Extraction of a large substrate (e.g. Cadence SeismIC)

ρ1 ρ2 ρ3 • •

Substrate approximated with layers of uniform resistivity Several approximations are made to facilitate faster extraction time - resistivity

ρ’ ≅

1 qunn0

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un - mobility of majority carriers n0 - equilibrium concentration of majority carriers

Substrate extraction ∂ 1 ε (∇ • E ) + ∇ • E = 0 ρ ∂t

Ignores magnetic field

Two approaches to solving this: • Differential form: finite difference • Integral form: boundary element

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Finite difference Substrate is broken into a number of rectangular volumes, resulting in a mesh circuit consisting of nodes interconnected by branches of resistors and capacitors in parallel. May also discretize into more “abnormally” shaped volumes.

Capacitors can be ignored up to several GHz (dielectric relaxation time). Very discretization dependent. Extension of PEEC models to substrate.

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Boundary element • Resistance-only case • Source and observation point as ports on the surface of the substrate • 3D problem reduced to 2D

φ (r ) = ∫ J (r ′)G (r , r ′)da S

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Components of Substrate Noise Analysis: Extracting wells, interconnect Devices

Interconnect

Well contact

Well

Substrate • •

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Accurate analysis requires extraction of wells, contacts, well taps For additional accuracy interconnect extraction can also be considered

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Components of Substrate Noise Analysis: SPICE Simulation •small circuits •perform substrate extraction •output reduced substrate network model for SPICE •user defines experiments and circuit performance metrics AVDD •Useful for characterizing digital cells for injected currents AVDD

Simulate output of AGC IF Rs

Simulate output of AGC IF

Rs

Re

Substrate C

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Cp

Re

Rp

...

Cp

Rp

...

Components of Substrate Noise Analysis: Fast Noise Simulation • Noise simulation requires knowledge of injected currents at devices • Perform analytical simulation including all injected currents • Identify noise contributors

VSS

Current Injectors Guard Ring Substrate Contact

...

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VDD Well Tap

Components of Substrate Noise Analysis: Sensitivity Analysis • Identify major contributors • Identify strategies for isolating the “listener” or quieting the “talkers” – Move/remove guard rings – Add guard rings – Tie guard rings to a different supply

• Identify effect of changing effective package inductance – Add/remove parallel inductance for each supply C

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Noise Sensitivity Analysis • Noise analysis : Y.v=i Admittance matrix

Noise currents injected into substrate

Substrate node voltages

• Noise sensitivity analysis : Y . dv/dp = di/dp -d Y/dp .v Sensitivities of voltages, currents and admittances to parameter, p

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Example:Impact of Shielding • For critical device, c and its shielding resistance, r Y. dvc/dr = -d Y/dr .vc • For added guard ring, change in noise, ∆vc= dvc/dr .∆r where ∆r is the change in shielding resistance n1

n2

n3

r

c C

Substrate contacts Copyright 2000 Cadence Design Systems

Added Guard ring

high medium low

What is needed for substrate noise analysis? • Physical Design Information (GDSII) • Layout Extracted Netlist (SPICE) / Cell-Based P&R Data (DEF) • Dynamic switching information (Spectre, PowerMill output) OR Static /Dynamic switching information (VCD) • Substrate current library view • Package Netlist (SPICE) C

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Outline • Introduction to signal integrity – Definitions – How failures happen

• Noise Solutions for Analog functionality • Noise Solutions for Digital functionality

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Noise solutions for digital functionality • Major issues facing cell-based digital functionality – Crosstalk – IR drop – Impact timing, functionality and yield

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Crosstalk Solutions • Dynamic simulation not possible on a large-scale • Rule-based approaches help but – very hard to generalize to different circuit topologies and different technologies – tend to worst-case things a lot – never guaranteed to catch everything!

• Static crosstalk analysis the only viable solution (e.g., Cadence CeltIC) C

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Static Crosstalk Analysis • Calculate worst-case noise from multiple aggressors for every net – use multi-port interconnect macromodels – requires additional cell-library characterization (noise view)

• Check for functional failure – requires noise failure metric

• Calculate impact on timing C

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Net Complexes • For each (primary) net, build a complex of (secondary) nets with significant coupling to the primary net. • Introduces some “redundancy” Net complex 1 Net complex 2

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Multiport Macromodels i1 v1

• Multiport models can take the form of admittance, impedance, hybrid, or scattering parameters • Admittance has the advantage of being compatible with SPICE-like simulators

i = Yv v = Zi C

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• Multiport reduction techniques– – – –

Block Arnoldi Block Lanczos Block Symmetric Lanczos PRIMA

Checking Functional Failures Principle: Functional failures due to noise are fundamentally due to a latch falsely changing state. Principle: To verify functionality, it is sufficient to show that every restoring logic gate when acted upon by a noise stimulus is never “biased” such that its sensitivity to purely dc noise is greater than one.

0 -> 1

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Noise stability Cload v out

vsource VDC

∂vout ∂VDC

VDC

∂vout ∂vin (t ) = (t ) • ∂vin ∂VDC =0 1

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VDC = 0

Noise-on-Delay • Difficult to model due to fight between aggressor and victim • Victim/Aggressor alignment has major impact Crosstalk Induced Delay Uncertainty

Log #Nets

5 4 3 2 1

Delay Delta (ps)

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700

600

500

400

300

200

100

-50

-150

-250

-350

-450

-550

-650

-750

0

Noise-on-Timing • Noise effects on delay depend on – slews of aggressor – timing windows of aggressors

• Timing windows and slews depend on noise-on-delay Start

Xtalk SDF

TW

STA End C

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What is needed for crosstalk analysis? • Extracted coupled distributed interconnect parasitics • Static timing information – Static logic constraints – Timing windows – Slews

• Noise library view

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IR-Drop • What is the power supply IR drop? Vdd

∆V = IR

R

Vdd - ∆ V

I

R Vss

• Resistance in power grid causes a reduced supply voltage at the delivery point C

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Impact of IR Drop Delay variation

• Reduces noise margin • Slows down the circuit – IR drop in power grip will create variations in delay across the chip – Performance of a chip roughly varies by 7-9% when vdd is varied by 10% – Affects clock skew in the clock network

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Supply voltage variation

VTH Delay versus Supply Voltage

Example: Consider 500MHz design in 0.18um technology with 1.8V power supply →10% voltage drop (180mV) causes 7% performance degradation (35MHz) ≈ 20MHz /100mV degradation !!

Analyzing IR drop • Estimate current drawn • Extract parasitic of the power supply network • Solves for the supply voltage at each cell (Sparse matrix) Vdd Pad

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Vdd

Electromigration • Flow of the current through narrow segments of wires • Possible effects: – Open circuit due to metal void – Short circuit due to metal buildup – Circuit malfunction because cells do not get enough current

• Sensitive to average or RMS current and damage is cumulative • More prone to DC current than AC current

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Cell-based Power Analysis • Static Power Calculator – Estimates average power with or without logic simulations

• Dynamic Power Simulator – Shows dynamic power effect at gate level – Can perform average or detailed mode depending on cell characterization data

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What is needed for IR drop analysis? • Physical Design Information (LEF/DEF) • Static /Dynamic switching information (VCD) • Power library view

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IR Drop Analysis Hot Spots (e.g., Cadence’s PA Workbench)

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Substrate Noise Analysis in the Design Flow Functional Design and Verification

Chip Floor Planning & Assembly Substrate Noise Analysis

Digital Block Implementation

Analog Block Implementation Substrate Noise Analysis

Full Chip Physical Verification , Extraction & Analysis Substrate Noise Analysis

Test & Debug Substrate Noise Analysis C

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Crosstalk Analysis in the Design Flow RTL

Physical Synthesis

Crosstalk Analysis

ECOs (DEF/Verilog) Placement

Routing

RC Extraction

SPEF

Crosstalk Analysis

Static Timing

LVS/DRC

Tape Out

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Delay Deltas (SDF)

Summary • Signal integrity is now a significant problem for UDSM designs (0.18µm or below) • Noise can cause functional failures, timing problems, increased costs and lower yields • Cadence’s SI solutions help UDSM SOC designers achieve functional first pass silicon with the desired performance, cost and yield

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References •

• • •

•

•

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D. K. Su, M. J. Loinaz, S. Masui, and B. A. Wooley, “Experimental Results and Modeling Techniques for Substrate Noise in Mixed-Signal Integrated Circuits,” IEEE J. Solid-State Circuits, Vol. 28, No. 4, pp.420-430, April, 1993 R. Gharpurey and R.G. Meyer, “Analysis and Simulation of Substrate Coupling in Integrated Circuits,” IEEE Journal of Circuit Theory, vol. 23, pp.381-394, 1995. N. K. Verghese, T. J. Schmerbeck, and D. J. Allstot, “Simulation Techniques and Solutions for Mixed-Signal Coupling in Integrated Circuits,” Kluwer Academic Publishers, 1995. I.L. Wemple and A.T. Yang, “ Integrated Circuit Substrate Coupling Models Based on VoronoiTesselated Substrate Macromodels,” IEEE Trans. On Computer Aided Design, pp.1459-1469, Dec. 1995. T. Blalack, J. Lau, F. Clement and B. Wooley, “Experimental Results and Modeling of Noise Coupling in a Lightly Doped Substrate,” IEEE International Electron Device Meeting, pp. 623-626, December 1996. E. Charbon, P. Miliozzi, L. P. Carloni, A. Ferrari, and A. Sangiovanni-Vincentelli, “Modeling Digital Substrate Noise Injection in Mixed-Signal ICs,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 18, No. 3, pp. 301-310, March, 1999.

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References • • •

•

•

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K. Shepard and V. Narayanan, “Noise in Deep Submicron Digital Design,” Proceedings of the IEEE International Conference on Computer-Aided Design, 1996, pp. 524-531. H. Chen and D. Ling, “Power Supply Noise Analysis Methodology for Deep-Submicron VLSI Chip Design,” Proceedings of the 37th Design Automation Conference, pp. 638-642, June, 1997. A. Dharchoudhury, R. Panda, D. Blaauw, and R. Vaidyanathan, “Design and Analysis of Power Distribution Networks in PowerPC Microprocessors,” Proceedings of the 38th Design Automation Conference, pp. 738-743, June, 1998. G. Steele, D. Overhauser, S. Rochel, S. Z. Hussain, “Full-Chip Verification Methods for DSM Power Distribution Systems,” Proceedings of the 38th Design Automation Conference, pp. 744-749, June, 1998. A. Deutsch, et al, “Modelling and characterization of long on-chip interconnections for highperformance microprocessors,” IBM Journal of Research and Development, Bol 39, No. 5, pp. 547567, 1995.

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