Bus Functional Model

Bus Function Model library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity bus1 is Port ( data : inout std_logic_vector(4 downto 0); refresh:in std_logic; add: inout std_logic_vector(1 downto 0); out1 : inout std_logic_vector(2 downto 0); out2 : inout std_logic_vector(2 downto 0); out3 : inout std_logic_vector(2 downto 0); out4 : inout std_logic_vector(2 downto 0); out0 : out std_logic_vector(2 downto 0); wr : in std_logic; re : in std_logic); end bus1; architecture Behavioral of bus1 is begin process(add,re,wr,refresh) begin if refresh='1' then data<="UUUUU"; out1<="UUU"; out2<="UUU"; out3<="UUU"; out4<="UUU"; out0<="UUU";

elsif wr='1' then add <= data(4 downto 3); case add is when "00" => out1<= data(2 downto 0);

out2<="ZZZ"; out3<="ZZZ"; out4<="ZZZ"; when "01" => out2<= data(2 downto 0); out1<="ZZZ"; out3<="ZZZ"; out4<="ZZZ"; when "10" => out3<= data(2 downto 0); out2<="ZZZ"; out1<="ZZZ"; out4<="ZZZ"; when others => out4<= data(2 downto 0); out2<="ZZZ"; out3<="ZZZ"; out1<="ZZZ"; end case; elsif re='1' then case add is when "00" => out0<= out1; when "01" => out0<= out2; when "10" => out0<= out3; when others => out0<= out4; end case; else out0<="000"; end if; end process;

end Behavioral;

Write operation

Read operation