Buck_converters For Portable Application

Magnetic Buck Converters for Portable Applications Frank De Stasi Mathew Jacob

1

Outline 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12.

Why use Switching Regulators? Common Device/Converter Specifications Buck Converter Analysis CCM/DCM modes Selection of L and C Synchronous Buck Converters Conduction and Switching Losses Efficiency improvement using PWM/PFM/LDO modes Control Approaches Current Mode Models and Compensation Guidelines Transient Measurement Techniques Layout Guidelines 2 © 2003 National Semiconductor Corporation

Efficiency Ig

Io

Power supply Vg + –

+ Vo

µP/DSP core

_

output DC power Po Vo I o η= = = input DC power Pg Vg I g

3 © 2003 National Semiconductor Corporation

Linear voltage regulator as power supply Series pass transistor

Iload

Q

+ Vg

+ –

C

Load

Vo –

+

-

Vref

Bandgap reference

• Simple, low noise, small footprint area • Output voltage lower than the battery voltage • High efficiency only if Vo is close to Vg 4 © 2003 National Semiconductor Corporation

Linear regulator power model Rs

Ig

Io +

Vg

+ –

Vo

Bias current IQ

–

I g = Io + IQ Efficiency:

Vo I o Vo I o ?= = Vg I g Vg ( I o + I Q )

Vo ?< Linear regulator efficiency cannot be greater Vg than the ratio of the output and the input voltage 5 © 2003 National Semiconductor Corporation

SMPS efficiency as a function of load 100 90

Example: • Vg = 3.6 V • Vo = 1.5 V • 0 < Io < 300 mA

Buck regulator

80

Efficiency [%]

70 60 50 40 . 30

Linear regulator

20 10 0 0.1

1

10

100

1000

Io [mA]

6 © 2003 National Semiconductor Corporation

Buck (step-down) switching power converter Ig

1

Low-pass LC filter

L

Io

+ Vg

+

2

+ –

vs (t)

C

v(t)

–

vs(t)

–

Vg

fs = 1/Ts = switching frequency

D' Ts

DTs

0 0 Switch position:

DTs 1

Load

Ts 2

t 1

D = switch duty cycle 7 © 2003 National Semiconductor Corporation

Buck converter ideal static characteristic vs(t)

Vg

〈vs〉 = DVg

area = DTsVg

0

0

V

DTs

Ts

t Conversion ratio:

Vg

0

Vo =D Vg 0

1

D

switch duty cycle

8 © 2003 National Semiconductor Corporation

Switch-Mode Power Supplies • Step-up, step-down and inverting configurations available • Switching converters are ideally 100% efficient • Real efficiency can be close to 100%; depends on operating conditions and implementation – Losses and efficiency will be discussed

• Converters generate switching noise • Discrete filter components (L, C) are required • Higher switching frequency => smaller L, C – Component selection will be discussed

• Duty cycle is the control variable • Closed-loop output voltage control is usually applied – Dynamic models and control will be discussed 9 © 2003 National Semiconductor Corporation

Impact of efficiency: a system example uP/DSP core mode % of time in this mode Load current Io [mA] Linear regulator

Total linear reg average Ig [mA] SMPS

Total SMPS average Ig [mA]

Efficiency [%] Battery current Ig [mA] Average Ig in this mode [mA]

Stand-by 90.0 0.1

Wait 4.0 1.0

Run1 3.0 10.0

Run2 2.5 100.0

FullRun 0.5 300.0

34.7 0.12 0.11

40.9 1.02 0.04

41.6 10.02 0.30

41.7 100.02 2.50

41.7 300.02 1.50

29.1 0.14 0.13

78.4 0.53 0.02

93.7 4.45 0.13

93.0 44.82 1.12

87.7 142.60 0.71

4.45 Efficiency [%] Battery current Ig [mA] Average Ig in this mode [mA] 2.12

Example: • Vg = 3.6 V • Vo = 1.5 V • 0 < Io < 300 mA 10 © 2003 National Semiconductor Corporation

Advantages of using SMPS over Linear regulators • SMPS results in significantly lower average battery current • High efficiency over a wide range of loads and output voltages is achieved with a SMPS • SMPS with low quiescent current modes provide longer battery life for mobile systems that spend most of their time in “stand-by”

11 © 2003 National Semiconductor Corporation

Buck regulators in the system Battery

Power distribution: Vg = 2.8-5.5 V PS

PS

3.6 V

Buck SMPS regulators

PS 2.5 V 1.5 V

Display PS

Audio

2.7-5.5 V

Interface

D/A

I/O

A/D

Baseband digital

PS

Antenna

1-3.6 V

µP/DSP core

PA LO

LNA

Analog/RF

2.5 V PS

Charger

2.5 V PS

2.5 V PS

Buck regulators are often used as switch-mode power supplies for baseband digital core and the RF power amplifier (PA) 12 © 2003 National Semiconductor Corporation

Device/Converter Specifications • Static voltage regulation – DC output voltage precision, i.e., % variation with respect to the nominal value over: • input voltage range (“line regulation”) • output load range (“load regulation”) • temperature

• Dynamic voltage regulation – “Load transient response,” including peak output voltage variation and settling time for a step load transient – “Line transient response,” including output voltage variation and settling time for a step input voltage transient 13 © 2003 National Semiconductor Corporation

Device/Converter Specifications • Overvoltage protection – prevents the output voltage from rising above a specified limit

• Undervoltage shutdown – turns the device off if the input (battery) voltage drops below a specified threshold

• Current limiting (overload protection) – limits the load current

• Thermal shutdown – turns the device off if the temperature exceeds a specified threshold

14 © 2003 National Semiconductor Corporation

Device/Converter Specifications • Frequency synchronization – allows synchronization of the switching frequency to an external system clock

• Soft start – controlled output voltage increase during startup

• Shut-down and operating-mode control – enables a system controller to shut-down the device, or to select an operating mode(PWM,PFM,LDO)

• Adjustment of the output voltage using – a resistive voltage divider, – external analog control voltage, or – digital (pin-select) control 15 © 2003 National Semiconductor Corporation

Buck converter analysis iL (t)

1

L + vL (t) –

2

+ –

Vg

+ iC(t)

C

R

v(t) –

iL(t)

L

L + vL(t) –

Vg

+ –

C

+

iC(t) R

v(t)

+ v L(t) – Vg

+ –

iL(t)

C

+ iC(t) R

–

–

Switch in position 1

v(t)

Switch in position 2 16 © 2003 National Semiconductor Corporation

Switch in position 1 iL (t) Inductor voltage:

L + vL(t) –

vL = Vg − v(t )

Vg

+ –

C

+

iC(t) R

v(t)

Small-ripple approximation:

–

vL ≈ Vg − V Knowing the voltage, we can solve for the current from: Solve for the slope:

diL vL Vg − V = ≈ dt L L

diL vL = L dt

Therefore, the inductor current increases in time with an essentially constant slope. 17 © 2003 National Semiconductor Corporation

Switch in position 2 L Inductor voltage:

+ vL (t) –

vL = −v (t )

Vg

+ –

iL (t)

+

iC(t)

C

R

v(t)

Small-ripple approximation:

–

vL ≈ −V Knowing the voltage, we can solve for the current from: Solve for the slope:

diL vL = L dt

diL vL V = ≈− dt L L

Therefore, the inductor current decreases in time with an essentially constant slope. 18 © 2003 National Semiconductor Corporation

Inductor voltage and current waveforms vL(t)

Vg – V DTs

D'Ts

t

–V Switch position: iL(t)

1

2

1

iL(DTs)

∆iL

I iL(0)

0

DTs

Ts

t 19

© 2003 National Semiconductor Corporation

Average voltage across the inductor equals zero vL(t)

Vg – V

Total area λ t

DTs –V

vL =

Ts

1 vL dt = D (Vg − V ) + (1 − D )(−V ) = 0 ∫ Ts 0 V = DVg

The DC output voltage is directly proportional to the input voltage and the switch duty cycle 20 © 2003 National Semiconductor Corporation

Average inductor current equals the output current iL (t)

1

L

IO

+ vL(t) – Vg

+ –

+

i C(t)

2

C

R

v(t) –

v (t ) V iC (t ) = iL (t ) − ≈ iL (t ) − = iL (t ) − I o R R We know that the average capacitor current equals zero Ts

iC

1 = ∫ iC dt = iL − I o = 0 Ts 0

iL = I o

In steady state, the average inductor current equals the load current 21 © 2003 National Semiconductor Corporation

Light-load operation: CCM and DCM iL (t )

high I o

without zero cross detect

t

low I o

Inductor current reverses polarity at light loads

iL (t )

high I o

with zero cross detect

t

low I o

Inductor current drops to zero before the end of the cycle: “Discontinuous conduction mode” (DCM) 22 © 2003 National Semiconductor Corporation

Implementing Zero-cross detect iL(t)

S1

L

Io

+ vL(t) – Vg + –

iC(t)

C

+ v(t)

S2

–

S2 is turned OFF

S2 control logic

S2

• With the zero-crossing comparator the switch S2 operates as a diode, resulting in DCM and improved efficiency at light loads • All switchers in the LM26XX family have this feature 23 © 2003 National Semiconductor Corporation

CCM vs. DCM • In DCM, the inductor current is always positive • At light loads, in DCM, the duty cycle is significantly lower than in CCM • CCM operation at light loads is undesirable because the reversal of the inductor current polarity contributes to conduction losses, while it does not contribute to the output load current • With a diode rectifier, DCM operation occurs automatically because of the diode characteristic • With a synchronous rectifier, DCM operation at light loads can be accomplished by turning off the NMOS switch at the zero-crossing of the inductor current

24 © 2003 National Semiconductor Corporation

DCM/CCM boundary • Boundary between constant-frequency CCM and constant-frequency DCM depends on the circuit parameters and the load • At the CCM/DCM boundary the inductor current ripple equals the output load current:

Vg − V V I o = ∆iL = = ICCM / DCM 2 Lf s Vg • If Io > ICCM/DCM, the buck converter operates in CCM • If Io < ICCM/DCM, the buck converter operates in DCM

25 © 2003 National Semiconductor Corporation

Static characteristic in DCM V D2 = Vg D 2 + 2 Lf s I o Vg

2 VL fs I o D= Vg (Vg − V )

• As the load Io in DCM decreases, the duty cycle D must decrease to keep the output V in regulation • Minimum possible on-time tp,min of the PMOS limits the minimum load current Io,min in constantfrequency PWM mode for which the output stays in regulation: If the output load current is reduced beyond Io,min the output voltage will start to rise and over voltage protection will activate.

I o ,min =

Vg − V Vg V

2L

t 2p ,min f s 26 © 2003 National Semiconductor Corporation

Determination of the inductor current ripple magnitude iL(t)

iL(DTs)

∆iL

I iL(0)

0

Ts

DTs

(change in iL) = (slope)x(length of subinterval) Current ripple magnitude

∆iL =

Vg − V 2 Lf s

D

2∆iL =

t

Vg − V L

DTs

Basic inductance selection eq.

L=

Vg − V 2∆iL f s

D 27

© 2003 National Semiconductor Corporation

iC(t) Total charge q

Output capacitor voltage ripple 1 Ts q = C ( 2∆v ) q = ∆iL 2 2 ∆i t ∆iL T /2 (neglecting esr) ( 2 ∆v ) ≈ D'T 4Cf s ∆iL ( 2 ∆v ) ≈ [2D − 1 + 8ResrCf s ] 4Cf s ∆v L

0

s

DTs

vC(t) V

s

∆v

(including esr)

t

The peak to peak output voltage ripple is the larger of the two values in the equations above.The equations can be used as capacitance selection equations if a target peak to peak output voltage ripple is known. 28 © 2003 National Semiconductor Corporation

Practice problem: selection of L and C • LM2612 is used to generate the output voltage of V = 1.5V at the max. DC output current of Io = 300 mA • The input voltage is between Vg = 2.8V and Vg = 5.5V • Select L and C so that: – the worst-case peak current ripple is ∆iL = 120 mA, and – the worst-case peak-to-peak output voltage ripple is 2∆v = 5 mV

29 © 2003 National Semiconductor Corporation

Inductor selection Vg − V V V 1 V 1 −  L= D= = 2∆iL f s 2∆iL f s Vg 2∆iL f s  Vg  Vg − V

• LM2612 datasheet: Switching frequency is between fsmin = 468 kHz and fsmax = 732 kHz

V 1 L≥ 2∆iL f s min

 1 − V  V g max 

  = 9.7 µH  

A 10µH inductor is chosen in the datasheet 30 © 2003 National Semiconductor Corporation

Output filter capacitor selection

1 ∆iL C= 4 f s ( 2 ∆v ) 1 ∆iL max C≥ = 12.8µF 4 f s min (2∆v) A 22µF ceramic capacitor is chosen in the datasheet. A 10µF capacitor can also be used with slightly higher output ripple, in case the load transient requirements are not demanding. 31 © 2003 National Semiconductor Corporation

Input current waveform iL (t)

1

+ vL (t) –

ig (t ) Vg

+ –

L +

iC(t)

2

C

R

v(t)

Cg – ig (t)

t

• Input current is pulsating, with large switching-noise component • Input filter (“decoupling”) capacitor is mandatory • to reduce the input voltage noise and ensure proper operation of the device • to prevent propagation of the switching noise to other system components 32 © 2003 National Semiconductor Corporation

Capacitor ripple currents 2∆iL Ripple Current Ratio = =r IO

(Vg − Vo) D r= L fs min IO

L = 10 µH

Vg = 3.6 V

Irms Input Capacitor = IO

Irms Output Capacitor = IO

Vo = 1.8 V

Io = 200 mA

r2 D(1 − D + ) 12 r 12

fs min = 468 kHz Io = 400 mA

r = 0.962

r = 0.481

Irms Input Capacitor = 107 mA

Irms Input Capacitor = 204 mA

Irms Output Capacitor = 56 mA

Irms Output Capacitor = 56 mA 33 © 2003 National Semiconductor Corporation

Capacitors : How small can I go ? Output Capacitor Input Capacitor

When reducing the value of output capacitors ensure proper gain and phase margins and evaluate line/load transient performance and whether it meets requirements. 34 © 2003 National Semiconductor Corporation

Switch realization with a synchronous rectifier

“Synchronous Buck”

NMOS: synchronous rectifier PMOS

PMOS: main switch

Vg

+ –

vp

iL(t)

ip(t)

Io

+ + v (t) – L

in(t) NMOS

vn

vsw(t) –

drivers

L

C

+ iC(t) v(t) –

n p

Switch control signals

Dead times are used to prevent short-circuit current through PMOS/NMOS

p n td1 td2 “dead” times

35 © 2003 National Semiconductor Corporation

Switch currents Average and RMS values

I p = i p (t ) ≈ DI o

i p (t )

I p ,rms =

i 2p (t ) ≈ D I o

t in (t )

I n = in (t ) ≈ (1 − D) I o t

I n,rms =

in2 (t ) ≈ 1 − D I o

Switch on-resistance and forward voltage drops result in switch conduction losses 36 © 2003 National Semiconductor Corporation

Conduction-loss models _

+

vON body diode

Ron,p

i p(t) + vSG

vp

ON

_

vn

ON

_

vGS

OFF

vON

+

OFF

vON

vON

NMOS: On-resistance Ron,n

+ in(t)

VD

RD _

i n(t)

_

PMOS: On-resistance Ron,p _

Ron,n

i n(t)

i p(t)

vON

+

_

+ vON body diode

_

L

in(t) +

Diode: Forward voltage drop VD in series with on-resistance RD

iL(t)

ideal L

RL winding + resistance

vL

i L(t) _

Winding resistance RL 37 © 2003 National Semiconductor Corporation

+

Buck circuit when the PMOS is ON Ron,p vON

+ + –

ideal L

RL

ip (t) _

winding + resistance

vL

iL(t) _

Io + V

Vg

_

v L = Vg − ( Ron , p + RL )iL − v ≈ Vg − ( Ron , p + RL ) I o − V

iL ≈ I o

38 © 2003 National Semiconductor Corporation

Buck circuit when the NMOS is ON ideal L

RL winding + resistance Vg

Io

_ +

R on,n

+ –

vL

iL (t)

V _

v L = −( Ron, n + RL )iL − v ≈ −( Ron , n + RL ) I o − V

ig = 0 39 © 2003 National Semiconductor Corporation

Steady-state model with conduction losses Inductor volt-second balance:

vL = 0

V = DVg − ( DRon , p + (1 − D )Ron , n + RL ) I o

Input current: I g = i g = DI o

V + Io ( Ron , n + RL ) Duty cycle considering losses D = Vg + Io ( Ron , n − Ron , p ) Equivalent steady-state circuit model with conduction losses: DRon,p + (1-D)Ron,n + RL

Ig

Io +

Vg

+ –

DIo

+ DV g –

R

V – 40

© 2003 National Semiconductor Corporation

Switching losses • Switching losses are proportional to the switching frequency • Switching loss mechanisms: – Charging/discharging of capacitance at MOSFET gates and switch node – Inductive switching transitions – Body-diode reverse recovery – Oscillator and other misc. controller losses – Inductor eddy-current and core losses

41 © 2003 National Semiconductor Corporation

Improving light-load efficiency • In PWM mode, light-load efficiency is reduced because a significant portion of switching losses does not scale with load • In PWM mode, the oscillator and the power switches are always switching at high switching frequency • Low-power modes are based on the idea of reducing the switching frequency in proportion to the load • If the switching frequency is proportional to load, high efficiency can be maintained over a very wide range of loads 42 © 2003 National Semiconductor Corporation

Switching frequency in PFM mode tp = Ipeak iL I o = iL

tp

tn

tn =

LI peak Vg − Vo LI peak Vo

Ts

1 I o = I peak (t p + t n ) f s 2

2Vo I o  Vo fs = 2 1 − LI peak  Vg

   

In PFM, the switching frequency is directly proportional to the load current 43 © 2003 National Semiconductor Corporation

Output voltage ripple in PFM Ipeak iL I o = iL

tp

( 2∆v ) ≈

I peak 2C

tn

Ts

(t p + t n ) =

2 LI peak

Vg

2C Vo (Vg − Vo )

The output voltage ripple is typically higher in PFM than in constant-frequency PWM mode 44 © 2003 National Semiconductor Corporation

PWM/PFM Combination 100% 90% 80%

Efficiency

70% 60% 50% 40% 30% 20%

Vin = 3.6V 10% 0% 0.1

1

10

100

1000

Iout in mA

LM2618 PFM

LM2618 PWM

• High efficiency over very wide range of loads • Low IQ

45

© 2003 National Semiconductor Corporation

Discussion of Operating Modes

PWM

PFM

LDO • • • •

LDO: linear regulator Low-noise Very low IQ Simple controller

• Best efficiency at moderate to heavy load • Constant-frequency, low switching noise • Synchronization to external clock possible • Relatively high IQ and poor lightload efficiency

• • • •

High efficiency over very wide load range Very low IQ Simple controller Increased output voltage ripple 46 © 2003 National Semiconductor Corporation

PWM/LDO Combination

PWM

Example: LM2608

LDO

PFM

• High efficiency (moderate-to-heavy load) • Low noise: • Constant-frequency operation • No switching noise at very light loads (LDO) • Very low IQ 47 © 2003 National Semiconductor Corporation

PWM/PFM Combination

Examples: LM2612/LM2614

PWM

LDO

PFM

• High efficiency over very wide range of loads • Low IQ 48 © 2003 National Semiconductor Corporation

Selection Guide

49 © 2003 National Semiconductor Corporation

Control approaches in constant-frequency PWM mode

• Voltage-mode control – The switch duty cycle is controlled based on output voltage sensing

• Current-mode control – The switch duty cycle is controlled based on output voltage and switch current sensing

50 © 2003 National Semiconductor Corporation

Voltage-Mode Control Architecture Power input

iL(t) +

vg (t) + –

Io Load

L

+

+ vL(t) –

iC(t)

C

vsw(t)

v(t) –

– Gate drivers p

Feedback connection

n

Dead-time

Compensator Pulse-width modulator

p(t)

vc

Voltage reference Vref

vc(t)

dTs Ts

t

v

G c (s)

t

Controller chip 51 © 2003 National Semiconductor Corporation

Current-Mode Control Architecture Power input

L

ip(t)

+ vL(t) – + C vsw(t)

vg(t) + –

Io Load

iL(t)

+

iC(t)

v(t)

–

–

Gate drivers p

Feedback connection

n Rsip (t)

Dead-time

Current-mode modulator p(t)

Compensator vc

Voltage reference Vref

v c(t)

dTs Ts

t

v

Gc(s)

t

Controller chip 52 © 2003 National Semiconductor Corporation

Current-mode summary • Advantages of current-mode control – Simpler, approximately single-pole responses – Inherent rejection of line disturbances – Built-in over-current protection

• LM26XX family is based on current-mode architecture • LM2608/12/18 feature internal compensation • LM2614/19 require external compensation 53 © 2003 National Semiconductor Corporation

Important definitions Cross-over frequency fc is the frequency where the magnitude response of the loop gain drops to 1, i.e. 0 dB T ( jwc ) = 1 → 0 dB Phase margin PM is the difference between the phase of the loop gain at the cross-over frequency and -180o

PM = phase [T ( jwc )] + 180o Gain margin GM (in dB) is the negative of the loop-gain magnitude response (in dB) at the frequency fm where the phase of the loop gain equals -180o

GM = −20 log T ( jwm ) , phase [T ( jwm )] = −180o 54 © 2003 National Semiconductor Corporation

Example of finding phase and gain margins 1

10.

100.

1000.

10000.

100 50 0

GM

-50 -100

PM

-150

10.

f c ≈ 10 KHz

100.

PM = 71o

1000.

10000.

100000.

GM = 24 dB 55 © 2003 National Semiconductor Corporation

Current Mode Power Stage Model L Vˆo Ro gm

Vˆc

ESR

R

C

Vˆo gm ⋅ ( Ro // R ) ⋅ (1 + s ⋅ ESR ⋅ C ) ≈ Vˆc (1 + s ⋅ ( Ro // R ) ⋅ C ) ⋅ (1 + s ⋅ L ) Ro 56 © 2003 National Semiconductor Corporation

Closed Loop Regulator Model L

Vˆo ESR

Ro

gm

R3 ⋅ C 4 ≈ ( Ro // R) ⋅ C

IF:

1 ≥ Fc 2 ⋅π ⋅ ESR ⋅ C

R

C

1 Vˆc

Ao

L 2 ⋅π ⋅ Ro

Vref

+ -

Rp R3 Loop Gain ≈

Fc ≈

C4

≥ Fc

gm ⋅ R o // R 2 ⋅ π ⋅ Rp ⋅ C 4

( g m ⋅ Ro // R ⋅ Ao) ⋅ (1 + s ⋅ ESR ⋅ C ) ⋅ (1 + s ⋅ R 3 ⋅ C 4 ) L (1 + s ⋅ Ro // R ⋅ C ) ⋅ (1 + s ⋅ ) ⋅ (1 + s ⋅ Rp ⋅ C 4 ⋅ Ao) Ro 57 © 2003 National Semiconductor Corporation

Compensation Example Objective: To compensate a LM2614 to get a stable system R = 10 Ω Load resistance C = 10 µF Output capacitor ESR = 10 mΩ ESR of output capacitor L = 10 µH Inductor

The load pole =

1 = 4.8 kHz 2 ⋅ π ⋅ ( R // Ro) ⋅ C

The high frequency pole = The ESR zero =

Ro = 80 kHz 2 ⋅π ⋅ L

1 = 1.6 MHz (high enough to ignore ) 2 ⋅ π ⋅ ESR ⋅ C

Ro = 5 Ω Small signal output resistance gm = 1 mho Transconductance of power stage Rp = ( R1 // R2) + 5 kΩ R1,R2 are external feedback resistor dividers,5 kO is internal

Rp = 33 kΩ Ao = 10000

Open loop gain of error amplifier

58 © 2003 National Semiconductor Corporation

Compensation Example We now need to choose the values of R3 and C4 to give a stable regulator response. If we set the zero frequency of R3 and C4 equal to the load pole frequency, and we choose a loop gain crossover frequency, Fc, much lower than the high frequency pole, then we can assume that the loop gain has a first order response. By choosing Fc = 30 kHz, the 80 kHz pole will contribute only 20 degrees of phase lag at Fc. This should give us a phase margin of about 90-tan-1(30/80) = 90-20 = 70 degrees. C4 =

gm ⋅ ( Ro // R ) = 536 pF ≈ 680 pF 2 ⋅ π ⋅ Fc ⋅ Rp

R3 =

( Ro // R ) ⋅ C = 49 k Ω ≈ 47 k Ω C4

This should give a stable regulator. Of course the real circuit should be checked under all conditions to ensure a stable system. This is only one of the methods to stabilize a regulator. Any other small signal methods that apply to feedback systems, will work here as well.

59 © 2003 National Semiconductor Corporation

Compensation guidelines Typically we like to choose a crossover frequency as high as possible. This gives a regulator with a fast transient response. However, if Fc is too close to the high frequency pole, of the power stage, the phase margin will be degraded. If we chose a Fc in the previous example of 75 kHz, then the phase margin would only be 47 degrees. Given the fact that these equations are only approximate, the phase margin of the real circuit will probably be smaller. This will give a “ringy” transient response. Lower crossover frequencies give a slower regulator, but tend to be more stable, and more “on-the-safeside”. The size of the output capacitor is also a compromise. Smaller gives more under/overshoot during a load transient and slightly higher output voltage ripple. However, with regulators that are internally compensated, smaller values of output capacitor will tend to increase Fc and therefore decrease phase margin. Large values of output capacitor will give small under/over-shoot and ripple, but are physically larger. Parts such as the LM2614, with external compensation, are much more flexible with regards to output capacitor value. In any case, it is always best to stay within the range given in the datasheet. 60 © 2003 National Semiconductor Corporation

Line Transient Measurements +15V

1000µ F

220pF(C) 10µ F 50KΩ

Pulse Generator Output

50KΩ

0.5µ H (L)

LM12CL 30Ω

DUT

10µF

50Ω

-15V

1000µ F

Adjust L and C to minimise overshoots 600mV

30µ s

61 © 2003 National Semiconductor Corporation

DUT

IRF 510

Function Generator Output

Constant Load

Pulse Load

Load Transient Measurements

50Ω

62 © 2003 National Semiconductor Corporation

Layout guidelines • Electrical guidelines – component placement and length of traces – width of traces – curling of critical current loops – routing of sensitive traces – ground pins and ground plane – voltage regulator placement on the system board

• Mechanical guidelines

63 © 2003 National Semiconductor Corporation

Critical current loops in a buck regulator Ig

L

1

Io

+ Vg

+ –

+

2

vs (t) –

C

v(t)

Load

–

The critical current loops carry large currents with significant switching ripples 64 © 2003 National Semiconductor Corporation

Component placement and length of traces

Loop 1 Loop 2

• The two critical loops carry large switching currents and act as antennas that radiate switching noise • Place C1, chip, L, and C2 as close as possible, to minimize the area of the two critical current loops 65 © 2003 National Semiconductor Corporation

Routing of sensitive traces

Route noise sensitive traces, such as the voltage feedback path, away from the critical current loops with noisy traces between power components

66 © 2003 National Semiconductor Corporation

Ground pins and ground plane Connect the chip ground pins and the filter capacitor ground pins using a large component-side fill Connect this area to the ground plane using several vias This approach prevents large switching currents from circulating through the ground plane, and reduces ground bounce to the chip 67 © 2003 National Semiconductor Corporation

Voltage regulator placement

sensitive analog/RF

Place switching regulator away from sensitive analog/RF subsystems

68 © 2003 National Semiconductor Corporation

References and Acknowledgements

• R.W.Erickson, D.Maksimovic, Fundamentals of Power Electronics, 2nd Edition, Kluwer Academic Publishers, 2000, ISBN 0-7923-7270-0 • LM26XX Data Sheets, National Semiconductor Corporation – LM2608,LM2612,LM2614,LM2618,LM2619

• Dragan Maksimovic, Associate Professor, ECE Dept, University of Colorado, Boulder, CO

69 © 2003 National Semiconductor Corporation

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