Bowers

Energy Efficiency: Electronics and Photonics

John Bowers Director, Institute for Energy Efficiency Professor of Electrical and Computer Engineering [email protected]

www.iee.ucsb.edu

IEE Electronics/Photonics Group •  •  •  •  •  •  •  •  •  • 

Banerjee Blumenthal Bowers Coldren Madhow Mishra Rodwell Rodoplu Theogarajan Yue

CMOS thermal management Efficient Optical networks Low power silicon photonics Low power transceivers Wireless networks High efficiency wireless transmitters High efficiency circuits Wireless networks Low power VLSI design High frequency CMOS communication circuits

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Power Requirements for Entertainment and Communication have Risen Exponentially

After Gladish, ECOC 2008

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The solution to the heat problem is multiple cores with a Terabit optical bus

Innovating Global Energy Solutions

   

Number
of
Bits
per
Task


 

Task Switching costs more per task when every bit must be switched More efficient to switch on boundaries of task As bit rate increases, energy per task will hit Moores law limit Photonic switching has different scaling behavior

1024
 1021
 Circuit
 1018
 1015
 Fast
Circuit
 1012
 109
 Burst
 106
 103
 Packet
 102


Increased
Bit
Rate
per
 Wavelength


Photonics
Switches
on
Task
Boundaries


Electronic
Switches
must
switch
every
bit


Energy
per
Task


 

>1000
x


Photonic
Switching
Limit


Bits
per
Task


Innovating After Blumenthal (2009) Global Energy Solutions

Many electronic servers and switches require significant power (1 MW for some routers) After Tucker (2008)

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Low Power, High Capacity MEMS Optical Switching

Eliminating OEO conversion, and switching optically eliminates about 1W per Gbit/s of information transmission. For a 1 Tbit/s switch, that is a savings of 10 kW per node. MEMS: Circuit switching Silicon Photonics: Packets

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From: Jerry Bautista, Intel (OIDA Interconnects Forum 8

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IBM Cell processor Communication

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Kash, IBM, OIDA Forum on Silicon Photonics

IBM Integration Concept • 

• 

• 

• 

3D layer stacking will be prevalent in the 22nm timeframe Intra-chip optics can take advantage of this technology Photonics layer (with supporting electrical circuits) more easily integrated with high performance logic and memory layers Layers can be separately optimized for performance and yield Optical Off-chip Interconnects

Processor System Stack BEOL vertical electrical interconnects

Processor Plane w/ local memory cache Memory Plane Memory Plane Memory Plane Photonic Network Interconnect Plane (includes optical devices, electronic drivers & amplifiers and electronic control network)

Global Source:Innovating J. Kash, IBM OIDAEnergy Forum Solutions on Silicon Photonics

IBM Possible On-Chip Optical Network Architecture

P

P G

P G

Cell Core G

(on processor plane)

Gateway (on processor and photonic plane)

P

P G

P

P G

P G

Electrical Control Network G

Deflection Switch

P G

Photonic Network

G

InnovatingOIDA Global Energy Solutions Forum on Silicon Photonics February 22, 2007

Silicon Doesn’t Emit Light: What do you do for an emitter? Luxtera: High level of integration, but lasers added one by one. Flip-chip bonded lasers wavelength 1550nm passive alignment non-modulated = low cost/reliable

Fiber cable plugs here

Ceramic Package

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Reduce IC Power Consumption Increase Efficiency: Silicon Photonics • Problems:

• Increase Interconnect Capacity. • Reduce power consumption of electrical interconnects • Solution: Optical interconnects • Problem: Silicon emits heat, not light. • Past Solution: Make photonics on InP or GaAs • Problem: Fabs are old tech. Devices expensive • Solution: Hybrid silicon lasers, photodetectors, amplifiers, modulators on Silicon in CMOS facility

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Hybrid Silicon Devices 6”

4” 2” 2 cm These wafers have patterned optical waveguides on SOI Innovating Energy Solutions with 2 micron GaInAsP layerGlobal on top.

Future: A Terabit Optical Chip Optical Fiber

Multiplexer

25 modulators at 40Gb/s

25 hybrid lasers Collaboration with Intel (Paniccia et al.) 15

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The Future •  Lower power interconnects using photonic on chip and off chip connections. •  Photonics made in CMOS fabrication lines. •  Hybrid integration of CMOS and Photonics.

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Innovating Global Energy Solutions UC Santa Barbara

Integrated optical buffer with on-chip silica delay •  First integrated optical random access memory (ORAM) was demonstrated at 40 Gb/s with 40-byte packets for up to 64 ns of delay •  Autonomous contention resolution between two 40-byte packet streams •  Two concatenated buffers •  Two buffered inputs

Silica chip delay

back-to-back

delay loop

5 circulations

2x2 optical switch

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