Book Iii

Real-Time Simulation Models of

Power Electronics & Drives Department of Electrical Engineering Indian Institute of Science Bangalore 560012 Jayalakshmi Kedarisetti Dinesh Gopinath Mridula Jain December 2, 2006

Contents 1 Real-Time Simulation Of Dynamic Systems 1.1 Introduction . . . . . . . . . . . . . . . . . . 1.2 Integration Methods . . . . . . . . . . . . . 1.3 Simulating An RLC Circuit . . . . . . . . . 1.4 Implementation . . . . . . . . . . . . . . . . 1.5 FPGA Design Files . . . . . . . . . . . . . . 1.6 Conclusion . . . . . . . . . . . . . . . . . . .

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3 3 4 8 9 9 11

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13 13 13 14 15 16 17 17 17 21 22 22 23 24 24 28 29 29 30 31 31 35

3 Real-Time Simulation of Separately Excited DC Machine 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Open Loop Control of DC Machine . . . . . . . . . . . . . . .

37 37 37

2 Real-Time Simulation Of SMPC 2.1 Introduction . . . . . . . . . . . 2.2 Basic Principle of Operation . . 2.3 Buck Converter . . . . . . . . . 2.3.1 Power Circuit Design . 2.3.2 Implementation . . . . . 2.3.3 Normalized Equations . 2.3.4 FPGA Design Files . . . 2.3.5 Waveforms . . . . . . . . 2.4 Boost Converter . . . . . . . . . 2.4.1 Power Circuit Design . 2.4.2 Implementation . . . . . 2.4.3 Normalized Equations . 2.4.4 FPGA Design Files . . . 2.4.5 Waveforms . . . . . . . . 2.5 Buck-Boost Converter . . . . . 2.5.1 Power Circuit Design . . 2.5.2 Implementation . . . . . 2.5.3 Normalized Equations . 2.5.4 FPGA Design Files . . . 2.5.5 Waveforms . . . . . . . . 2.6 Conclusion . . . . . . . . . . . .

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ii

CONTENTS

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38 39 41 42 42 43 43 43 43 44 44 44 44 46 46 48 48 48 49

4 Real-Time Simulation of Induction Machine 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . 4.2 Basic Principle of Operation . . . . . . . . . . . . . . 4.3 Modelling of Induction Machine using Space Phasors 4.4 Implementation . . . . . . . . . . . . . . . . . . . . . 4.5 Normalized Equations . . . . . . . . . . . . . . . . . 4.6 FPGA Design Files . . . . . . . . . . . . . . . . . . . 4.7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . 4.8 Conclusion . . . . . . . . . . . . . . . . . . . . . . . .

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51 51 51 53 55 57 57 57 68

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69 69 69 71 72 72 74 76 77 77 81

3.3 3.4

3.5

3.6 3.7 3.8

3.2.1 Implementation . . . . . . . . . 3.2.2 FPGA Design Files . . . . . . . Closed Loop Control of DC Machine . Transfer Functions Of The Subsystems 3.4.1 DC Motor and Load . . . . . . 3.4.2 Chopper . . . . . . . . . . . . . 3.4.3 Current and Speed Controllers . 3.4.4 Current Feedback . . . . . . . . 3.4.5 Speed Feedback . . . . . . . . . Simulation of DC Motor Drive . . . . . 3.5.1 DC Motor Equations . . . . . . 3.5.2 Speed-Feedback Filter . . . . . 3.5.3 Current-Feedback Filter . . . . 3.5.4 Speed Controller . . . . . . . . 3.5.5 Current Controller . . . . . . . 3.5.6 Chopper . . . . . . . . . . . . . Implementation . . . . . . . . . . . . . FPGA Design Files . . . . . . . . . . . Conclusion . . . . . . . . . . . . . . . .

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5 V/F Control of Induction Motor Drive 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Basic Principle of V/F operation . . . . . . . . . . . . . . 5.3 Sine-Triangle Modulation . . . . . . . . . . . . . . . . . . . 5.4 Implementation of V/F Sine-Triangle Modulator in FPGA 5.4.1 Generation of V/F sine waves . . . . . . . . . . . . 5.4.2 Carrier Generation . . . . . . . . . . . . . . . . . . 5.4.3 Generation of PWM . . . . . . . . . . . . . . . . . 5.4.4 Slow Start of Induction Motor . . . . . . . . . . . . 5.5 Open-loop V/F Control of IM - Real-time Simulation . . . 5.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . .

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CONTENTS

6 Real-Time Simulation Of Switched Reluctance Motor 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 Basic Principle of Operation . . . . . . . . . . . . . . . . 6.3 Inductance Gradient (L vs θ) . . . . . . . . . . . . . . . 6.4 Flux-Linkage Characterstics . . . . . . . . . . . . . . . . 6.5 Torque Characterstics . . . . . . . . . . . . . . . . . . . 6.6 Position Sensor . . . . . . . . . . . . . . . . . . . . . . . 6.7 Control Strategy . . . . . . . . . . . . . . . . . . . . . . 6.8 Implementation . . . . . . . . . . . . . . . . . . . . . . . 6.9 Normalized Equations . . . . . . . . . . . . . . . . . . . 6.10 FPGA Design Files . . . . . . . . . . . . . . . . . . . . . 6.11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 6.12 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . .

iii

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83 83 83 85 86 87 91 92 95 97 97 97 106

7 Control and Real-Time Simulation of Matrix Converters 7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Basic Principle of Operation . . . . . . . . . . . . . . . . . . 7.3 Direct and Indirect Matrix Converters . . . . . . . . . . . . 7.3.1 Direct Matrix Conversion . . . . . . . . . . . . . . . 7.3.2 Indirect Matrix Conversion . . . . . . . . . . . . . . . 7.4 Modulation of Matrix Converters . . . . . . . . . . . . . . . 7.4.1 Indirect Converter Modulation . . . . . . . . . . . . . 7.4.2 Direct Converter Modulation . . . . . . . . . . . . . 7.5 Implementation of Modulators in FPGA . . . . . . . . . . . 7.5.1 Output Modulator . . . . . . . . . . . . . . . . . . . 7.6 Modelling of Direct and Indirect Matrix Converters . . . . . 7.6.1 Indirect Converter . . . . . . . . . . . . . . . . . . . 7.6.2 Direct Converter . . . . . . . . . . . . . . . . . . . . 7.7 Real-Time Simulation . . . . . . . . . . . . . . . . . . . . . . 7.8 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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107 107 107 109 109 110 112 112 117 118 119 122 124 126 127 131

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iv

CONTENTS

List of Figures 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8

Triggering Timing. . . . . . . . . . . . . Zero Order Integrator (Euler’s method). First Order Integrator . . . . . . . . . . Second Order Integrator . . . . . . . . . Series RLC Circuit. . . . . . . . . . . . . FPGA Design File for RLC Circuit . . . FPGA Design File for Euler’s Integration Transient Wave forms of RLC Circuit . .

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4 5 6 7 8 10 11 11

2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 2.15 2.16

Basic Switching Converter . . . . . . . . . . . . . . . . . Buck Converter . . . . . . . . . . . . . . . . . . . . . . . FPGA Design File of Buck Converter . . . . . . . . . . . FPGA Design File of Buck Converter . . . . . . . . . . . Buck Converter Off-line Simulation Waveforms . . . . . . Buck Converter Real-Time Simulation Waveforms . . . . Boost converter . . . . . . . . . . . . . . . . . . . . . . . FPGA Design File of Boost Converter . . . . . . . . . . FPGA Design File of Boost Converter . . . . . . . . . . Boost Converter Off-Line Simulation Waveforms . . . . . Boost Converter Real-Time Simulation Waveforms . . . . Buck-Boost Converter . . . . . . . . . . . . . . . . . . . FPGA Design File of Buck-Boost Converter . . . . . . . FPGA Design File of Buck-Boost Converter . . . . . . . Buck-Boost Converter Off-Line Simulation Waveforms . . Buck-Boost Converter Real-Time Simulation Waveforms

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13 14 18 19 20 20 21 25 26 27 27 28 32 33 34 34

3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8

DC Motor Model. . . . . . . . . . . . . Generalized Machine Model. . . . . . . FPGA Design File for DC Machine . . Modelling of DC Machine . . . . . . . Block Diagram of the DC Motor Drive Filter . . . . . . . . . . . . . . . . . . . PI-Controller . . . . . . . . . . . . . . Saturation . . . . . . . . . . . . . . . .

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vi

LIST OF FIGURES

3.9 DC Motor Drive with Speed and Current Feedback . . . . . . 3.10 DC Motor Drive with Speed and Current Feedback . . . . . .

50 50

4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 4.14

Equivalent Circuit . . . . . . . . . . . . . . . . . . . Twophase equivalent of a 3-phase induction motor . . FPGA Design File for isa . . . . . . . . . . . . . . . . FPGA Design File for isb . . . . . . . . . . . . . . . . FPGA Design File for isra . . . . . . . . . . . . . . . . FPGA Design File for isrb . . . . . . . . . . . . . . . . FPGA Design File for ωm . . . . . . . . . . . . . . . FPGA Design File for Eulers Integration . . . . . . . Vsa*k and Vsb*k waveforms where k=1/(1.5*sqrt(2)) Vsa and Vsb waveforms . . . . . . . . . . . . . . . . isa ,isb , isra and isrb waveforms . . . . . . . . . . . . . . isa ,isb , isra and isrb waveforms . . . . . . . . . . . . . . ωm and Mg ∗ 0.2/16 waveforms . . . . . . . . . . . . ωm and Mg ∗ 0.2 waveforms . . . . . . . . . . . . . .

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52 53 59 60 61 62 63 64 65 65 66 66 67 67

5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12 5.13 5.14 5.15 5.16

Torque-Speed Characteristics of Induction Motor . V/F relation including low frequency voltage boost Sine-Triangle PWM . . . . . . . . . . . . . . . . . . Three Phase VSI . . . . . . . . . . . . . . . . . . . Theta Address Generation Scheme . . . . . . . . . p.u Sine wave . . . . . . . . . . . . . . . . . . . . . Generation of Three-phase V/F Sine waves . . . . . Carrier Generation Scheme in FPGA . . . . . . . . Sine Wave and Triangular Carrier . . . . . . . . . . PWM Generation for U-phase . . . . . . . . . . . . PWM Signals for U and V phases . . . . . . . . . . Slow Starting Logic . . . . . . . . . . . . . . . . . . Slow Starting V/F Sine Wave Reference . . . . . . VSI Model Implementation in FPGA . . . . . . . . Interconnection of Different Modules for v/f Drive. Real-Time Simulation Waveforms . . . . . . . . . .

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70 70 71 72 74 74 74 75 76 76 77 78 78 79 80 80

6.1 6.2 6.3 6.4 6.5 6.5 6.5 6.6 6.7 6.8

Cross-section of and 8/6 pole 4-phase SR Motor . . . . . Idealised Inductance Profile of the Four Different Phases Flux-linkage Characterstics . . . . . . . . . . . . . . . . . Torque Characterstics . . . . . . . . . . . . . . . . . . . (a) Inductance Profiles of the Four Stator Phases . . . . (b) Position Signals for Forward Rotation . . . . . . . . . (c) Position Signals for Reverse Rotation . . . . . . . . . Low Speed Control Strategy . . . . . . . . . . . . . . . . Control Strategy at High Speed . . . . . . . . . . . . . . FPGA Design File for Speed to Position Conversion . . .

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84 85 87 88 91 91 91 95 95 98

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LIST OF FIGURES

vii

6.9 6.10 6.11 6.12 6.13 6.14 6.15 6.16 6.17 6.18 6.19

FPGA Design File for Sector Selection . . . . . . . . . . . . . FPGA Design File for Generation of Position Signals . . . . . (a) FPGA Design File for Generation of Enable Signals . . . . (b) FPGA Design File for Generation of Enable Signals . . . . High Speed (Forward) and Full Load (Forward) Waveforms . . Low Speed (Forward) and Full Load (Forward) Waveforms . . Starting Speed (Forward) and Full Load (Forward) Waveforms High Speed (Reverse) and Full Load (Forward) . . . . . . . . High Speed (Reverse) and Full Load (Reverse) . . . . . . . . . High Speed (Forward) and Full Load (Reverse) . . . . . . . . High Speed and Half Load . . . . . . . . . . . . . . . . . . . .

99 100 101 102 103 103 103 104 104 104 105

7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 7.18 7.19 7.20 7.21 7.22 7.23 7.24 7.25 7.26 7.27 7.28 7.29

Matrix Converter Topology . . . . . . . . . . . . Indirect Matrix Converter Topology . . . . . . . . Input Converter and the Current Space Phasors . Sector Definition . . . . . . . . . . . . . . . . . . Modulation Functions and Raw Switch Signals . . VSI and Space vectors . . . . . . . . . . . . . . . Switch Signal Generation for VSI : Sector 1 . . . Input Modulator Implementation in FPGA . . . . Structure of Input Modulator . . . . . . . . . . . Output Modulator Implementation in FPGA . . . Reference angle Generation . . . . . . . . . . . . Calculation of Duty Ratios . . . . . . . . . . . . Calculation of Modulating Functions . . . . . . . Duty Ratios dα and dβ . . . . . . . . . . . . . . . PWM signals for S1 and S2 of Input Converter . . PWM signals for Su and Sv of Output Converter PWM signals for Sau and Sbu of Direct Converter DC link voltage : Indirect Matrix Converter . . . Structure of Output Modulator . . . . . . . . . . Indirect Converter Model . . . . . . . . . . . . . . Output Line Voltage: Indirect Matrix Converter . Output Phase Voltage : Indirect Matrix Converter Direct Matrix Converter Model . . . . . . . . . . Line-Line Voltage : Direct Matrix Converter . . . Phase Voltage: Direct Matrix Converter . . . . . Input Converter Model in FPGA . . . . . . . . . DC link voltage : Real-time simulation . . . . . . Output Phase Voltage : Real-time simulation . . Real-time Simulation Results . . . . . . . . . . .

108 110 112 113 114 115 116 118 119 119 120 121 122 122 123 123 124 125 125 126 126 127 127 128 128 129 130 130 131

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viii

LIST OF FIGURES

List of Tables 1.1 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 PU Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9 9

2.1 2.2 2.3 2.4 2.5 2.6 2.7

Parameters of the Buck converter . . . . Base Values for the Buck converter . . . Per Unit Values . . . . . . . . . . . . . . Parameters of the Boost converter . . . . Base Values for the Boost converter . . . Parameters of the Buck-Boost converter Base Values for Buck-Boost converter . .

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16 16 16 23 23 30 30

3.1 3.2 3.3 3.4

Details of the DC Motor Parameters . . . . . . . PU Values . . . . . . . . Parameters . . . . . . .

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39 39 39 49

4.1 4.2 4.3 4.4 4.5

Details of the Induction Motor . . . . Parameters of the Induction Motor . Base Values . . . . . . . . . . . . . . PU Values . . . . . . . . . . . . . . . Equations for implementing in Digital

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55 56 56 56 58

6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9

. . . . . . . . . . . . . Torque . . . . . . . . . Torque (contd..) . . . . Switch Control Signals θ1 . . . . . . . . . . . . θ2 . . . . . . . . . . . . Details of the Switched Base Values . . . . . . PU Values . . . . . . .

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88 89 90 92 94 94 96 96 96

7.1 Switch Signals . . . . . . . . . . . . . . . . . . . . . . . . . . .

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2

LIST OF TABLES

Chapter 1

Real-Time Simulation Of Dynamic Systems 1.1

Introduction

Any system can be represented by a mathematical model. Dynamic systems are represented by differential equations or difference equations. Simulation of dynamic systems require the solving of these differential/difference equations. In off-line simulation tools, the solution is carried out in a non-real time manner. For example, if it is required to study the response of a system for a few seconds, it may take minutes or even hours to complete the simulation. This depends on the complexity and simulation parameters. This is because the actual time involved in the calculation of the variables is more. On the other hand in Real-Time Simulation, the results are produced almost instantly. This is possible if the system model is implemented by an electronic circuit. Historically, analog computers were used to solve differential equations. But analog circuits are less flexible in simulating complex systems. Real-time simulation can be done with digital circuits or microprocessors also. Here, the systems equations need to be translated to difference-equations. However, conventional microprocessors and Digital Signal Processors (DSPs) suffer from an inherent bottleneck in performing calculations. They process the data in a sequential manner. So, there is a limit to the minimum simulation step time that is possible for a fixed clock frequency. This limitation can be overcome by paralleling processors. Such a scheme is scalable and very useful for simulating very large dynamic systems with several variables. For real-time simulation of comparatively less-complex systems, a less costly alternative is required. An FPGA is a suitable platform for implementing such systems. The basic advantage of an FPGA is that it can be programmed to process data in parallel. Thus the implementation of system equations on an FPGA results in very short execution time. The system model is realized as a combination of sequential and combinational logic elements. This digital circuit is then programmed in to the FPGA. The minimum time required to calculate the present state

4

Real-Time Simulation Of Dynamic Systems Calculate State Variables CSV Update State Variables USV ∆τ

Figure 1.1: Triggering Timing. variables from previous state variables is the sum of propogation delay of all logical elements and setup and hold times of sequential elements. A clock signal drives the digital circuit. During each clock cycle, the present states of the system are calculated. These calculations are split into two stages as shown in Fig. 1.1. In the first stage the present states of the system are calculated using the previous states of the system. In the second stage the values are updated.

1.2

Integration Methods

The dynamic systems may be represented generally in the form of ODE dyi = ei (xj , yk , t), dt

i, j, k = 1, . . . , n

(1.1)

where xj (t) are the independent forcing functions, yk (t) are the state variables and t the time as variable of integration. The procedure for solving a system of equations simply involves applying the one-step technique for every equation at each step before proceeding to the next step. There are several integration methods [1] to solve the differential equations (1.1). These methods differ in complexity. Each integration method can be implemented by digital logic elements in FPGA. Because of its simplicity, euler’s algorithm is widely used. A. Backwards Euler’s Method In this method, the time axis is subdivided into several intervals. In each interval, ei is approximated by a constant representing the average of ei in that interval. A new value of yi is predicted using the slope (equal to the first derivative at the previous value) to extrapolate linearly over the step size ∆t. yi (n) = yi (n − 1) + ei (n − 1) ∗ ∆t (1.2)

In digital logic circuit, Euler’s method is represented as shown in Fig. 1.2.

1.2 Integration Methods

5

e n−1 Multiplier ∆τ

D−Flipflop

ADDER

yn

USV yn−1

D−Flipflop CSV

Figure 1.2: Zero Order Integrator (Euler’s method). D-Flipflop is used for delaying the input until the next clock pulse is given. With the rising edge of the clock pulse CSV, yi (n − 1) is latched. Error function ei (n − 1) which is dependent on the previous state variables yi (n − 1) is calculated and given as input to the integration block. Inputs to the ADDER block are yi (n − 1), ei (n − 1) ∗ ∆t as in the eq. (1.2). State variables are updated with the rising edge of the clock USV. B. Heun’s Method The curve ei is approximated as a straight line within the interval (n − 1)∆t to n∆t. The area under this straight line is an estimate of the integral of ei between the limits (n − 1)∆t and n∆t. So yi (n) = yi (n − 1) + ∆t

ei (n − 1) + ei (n) 2

(1.3)

Implementation of the Heun’s method with logical elements is similar to Eulers method except the input ei (n − 1) is replaced by the average of ei (n − 1) and ei (n). With the given previous state variable yi (n − 1), ei (n − 1) is calculated. As said before, FPGA is a parallel device. so ei (n − 1) has to be latched (Latch) for calculating the average of error functions. Multiplexer (MUX) selects either ei (n − 1) or average of error functions depending upon the clock ‘Avg’. So Heun’s method requires two clock cycles to calculate the present state variables Fig. 1.3. The dotted line shows division of the on period CSV into two halfs. Obviously, heun’s method of integration appropriates more number of logic elements when compare to Eulers method.

6

Real-Time Simulation Of Dynamic Systems

ADDER 2

D−Flipflop e n−1

Latch

err

MUX Avg

err Multiplier ∆τ yn−1

ADDER

D−Flipflop

yn

USV

MUX

yn−1 yn−pred

Avg

D−Flipflop CSV D−Flipflop Avg (a)

yn−1

CSV e n−1

Latch

yn−pred

Avg yn

USV

∆τ (b)

Figure 1.3: (a) First Order Integrator (Heun’s Method) (b) Triggering Timing.

1.2 Integration Methods

7

__ 1 2

e n−1

err

MUX K1 / K2

err Multiplier ∆τ yn−1

ADDER

D−Flipflop

yn

USV yn−1

MUX

yn−pred

Avg

D−Flipflop CSV D−Flipflop K1 / K2 (a)

yn−1

CSV e n−1

K1 / K2

yn

USV

∆τ (b)

Figure 1.4: (a) Second Order Runge-Kutta Method (b) Triggering Timing. C. Second-Order Runge-Kutta Method

where

yi (n) = yi (n − 1) + k2 ∗ ∆t
k1 = ei yi (n − 1), t(n − 1)  1 1  k2 = ei yi (n − 1) + k1 ∆t, t(n − 1) + ∆t 2 2

(1.4)

This is the improved polygon method. This method also requires two clock cycles to calculate the present state variables fig. 1.4. Eventhough there are different integration methods to solve (1.1), the only difference would be the formulation of subroutine to compute the slopes. The higher order techniques are always the methods of preference [1]. However, other factors such as programming costs and the accuracy requirements of the problem must also be considered when choosing a solution technique.

8

Real-Time Simulation Of Dynamic Systems

Ra

L

+

i Vg

C

Vc

_ Vg = 100 V; Ra = 10 Ω ; L = 20 mH; C = 4 µ H

Figure 1.5: Series RLC Circuit.

1.3

Simulating An RLC Circuit

An electrical series RLC circuit is shown in Fig 1.5. A transient current and voltages are established in the circuit when the switch is suddenly closed. Equations that describe the transient behavior of the circuit 1.5 are Vg = Ri + L i=C

di + vc dt

dvc dt

(1.5a) (1.5b)

Equations (1.5) are a pair of first-order linear differential equations that can be solved using any above mentioned numerical methods. The equations are first normalized with the help of arbitrary values Vb , Rb . i

R i L d ib vc Vg = + + Vb Rb ib Rb dt Vb vc d i Vb = CRb ib dt

(1.6a) (1.6b)

where ib = Vb /Rb . With the following abbrevations, i R vc L Vg = Vg∗ , = i∗ , = R∗ , = vc∗ , = τLR , CRb = τCR , Vb ib Rb Vb Rb a nondimensional equation results     ∗    di∗ ∗ −R −1 i 1  τLR dt        Vg∗ = +  dvc∗  τCR 1 0 vc∗ 0 dt

(1.7)

These first order linear differential equations can be solved using any numerical methods as mentioned in section 1.2.

1.4 Implementation

1.4

9

Implementation

A. Parameters : The Table. 1.1 gives the base values for voltage, current and the values of other quantities. Input Voltage (Va ) Ra , L, C

100V 10Ω, 20mH, 4µF

Voltage (Vb )

100V

Current (Ib )

10A

R∗

V ∗ /I ∗ = 1

τLR

L/Rb = 2e−3

τCR

CRb = 40e−6

Step time (∆T )

25.6µ

Table 1.1: Parameters

pu value

Equivalent digital Value

Equivalent decimal value

2 pu

7F F FH

32767d

1 pu

3F F FH

16383d

0 pu

000H

0d

-1 pu(16bit)

C000H

49152d

-2 pu(16bit)

8000H

32768d

Table 1.2: PU Values

B. PU System Followed : The Table 1.2 shows the digital equivalent for the pu values. The bit length of the digital word is not limited in an FPGA. Inorder to incorporate the signed arithmetic, the digital equivalent for a negative pu value is chosen as the 1’s compliment of digital equivalent of its corresponding positive pu value.

1.5

FPGA Design Files

FPGA Design files of RLC Circuit are placed in ‘fpga program files’ folder. Fig. 1.6 and Fig. 1.7 are the FPGA design files to implements the equations given in (1.7). The output waveforms are shown in Fig. 1.8

Figure 1.6: FPGA Design File for RLC Circuit

10 Real-Time Simulation Of Dynamic Systems

1.6 Conclusion

Figure 1.7: FPGA Design File for Euler’s Integration

Figure 1.8: RLC Circuit (Eulers Integration). (1) Input Voltage (2) Inductor Current (3) Capacitor Voltage

1.6

Conclusion

In this chapter, different integration methods are explained. Simple RLC circuit has been implemented in FPGA based controller.

11

12

Real-Time Simulation Of Dynamic Systems

Chapter 2

Real-Time Simulation Of SMPC 2.1

Introduction

DC-to-DC converters convert electrical power provided from a source at a certain dc voltage to electrical power at a different dc voltage. Linear regulators are most common converters used for this purpose. They are simple to analyze and design, also provide very high quality output voltage. But the major drawback of linear regulators is their poor efficiency[11]. The losses in such converters appear as heat in the series and shunt elements. The linear regulators are therefore used only for low power levels. For the applications, where the efficiency is very important, linear regulators are not suitable. In such applications, switched mode power converters are standard. Switched mode power converters use power electronics semiconductor devices which operate in ON and OFF states. Because there is a small power loss (ideally zero) in those states (very small voltage across a switch in the ON state and zero current through a switch in OFF state), switching converters can achieve high energy conversion efficiency.

2.2

Basic Principle of Operation

The basic circuit for SMPC is shown in Figure 2.1. on + Vg −

off

Vo(t) R

Figure 2.1: Basic Switching Converter

14

Real-Time Simulation Of SMPC

The average value of output voltage depends upon the position of switch. The ON position connects the source Vg to the output. In the OFF position, output is totally isolated from the input. The switch is operated at a switching period of Ts For a fraction [dTs ] of the switching period, the switch is kept ON. For the rest of the time [(1 − d)TS ], switch is kept OFF. The fraction d is defined as duty ratio of the switch[12]. The average output voltage can be calculated in terms of d and is found to be: Z TS Z Ton Z Ts Ton 1 1 1 0 dt = Vg Vg dt + Vo = = Vg d (2.1) Vo dt = Ts 0 Ts 0 Ts Ton Ts

2.3

Buck Converter

Buck converter is also known as step-down converter. As the name implies, a step down converter produces a lower output voltage than the dc input voltage. Figure 2.2 shows the circuit diagram of a Buck Converter with a resistive load and a low pass filter. L

on

Vg

+

off

iL Vc

−

C

R

Figure 2.2: Buck Converter The dynamic equations and output equations of the buck converter are obtained as follows. During ON time: di = Vg − Vc dt dvc Vc C = il − dt r L

(2.2a) (2.2b)

During OFF time: di = −Vc dt Vc dvc = il − C dt r L

(2.3a) (2.3b)

2.3 Buck Converter

15

Combining equations 2.2 and 2.3 , following equations are obtained di = Vg (d) − Vc dt Vc dvc = il − C dt r L

(2.4a) (2.4b)

vo = v c

(2.5)

Vo = dVg

(2.6)

Ig = dIo

(2.7)

The above equations describe the complete modelling of the buck converter. The Eqn 2.4 is the dynamic equation of the converter. Eqn 2.6 and Eqn 2.7 give the relation between input-output voltage and current respectively.

2.3.1

Power Circuit Design

A. Design of Inductor : In each sub period [dTS and (1 − d)TS ], the rate of change of current is constant. The current ripple can be determined using the following equation. Vo (1 − d)TS Vg d(1 − d)TS = (2.8) δIo = L L δIo (1 − d)RTS = δi = (2.9) Io L The value of the inductance L is designed such that δi is 10% of the output current Io . B. Design of Capcitor : The charging and discharging current of the capacitor decides the voltage ripple. The ac part of the inductor current flows into the capacitor. δVo =

1 1 δIo TS δQ = C C2 2 2

(2.10)

Vo (1 − d)TS2 8LC

(2.11)

δVo =

δVo (1 − d)TS2 = δv = (2.12) Vo 8LC The capacitor C is designed for δv to be 1% of the output voltage Vo .

16

Real-Time Simulation Of SMPC

2.3.2

Implementation

A. Parameters : The parameters of the Buck Converter used in the simulation program are shown in the Table 2.1. Quantity Vg L R C Tlr Trc d Ts 4t

Value 13.33V 0.64mH 5Ω 40µF 0.00013 0.0002 .75 102.4µsec 3.2µsec

Table 2.1: Parameters of the Buck converter

B. Base Values for Different Quantities : As the implementation is digitally realized, there arises the need for following a pu system for simple understanding. For perunitization of different quantities, the base values are required, which can be chosen as per convenience. The Table. 2.2 shows the base values for voltage, resistance and current. The other bases are calculated from the above mentioned base quantities. Voltage (Vb ) resistance (Rb ) Current (Ib )

13.33V 5Ω 2A

Table 2.2: Base Values for the Buck converter

C. PU System Followed : The Table 2.3 shows the digital equivalent for the pu values. The digital equivalent for a negative pu value is chosen as the 1’s compliment its corresponding positive pu value. pu value 2 pu 1 pu 0 pu -1 pu(16bit) -2 pu(16bit)

Equivalent digital Value 7F F FH 3F F FH 000H C000H 8000H

Equivalent decimal value 32767d 16383d 0d 49152d 32768d

Table 2.3: Per Unit Values

2.3 Buck Converter

2.3.3

17

Normalized Equations

In this section, all the equations are perunitized and are made ready for implementation. di = Vg (d) − Vc (2.13a) dt dvc Vc C = il − (2.13b) dt r Dividing the above equations by ib , and Vb respectively, Z
1 Vg(pu) d − Vc(pu) dt iL(pu) = Tlr Z
1 iL(pu) d − Vc(pu) dt Vc(pu) = Trc Using the Eulers Method of integration [1], the equation in digital domain can be written as L

iL (n) = iL (n − 1) + e (n − 1) (4t)

where

e (n − 1) = Vg (n − 1) (d) − Vc (n − 1)


1 Tlr

Vc (n) = Vc (n − 1) + e (n − 1) (4t)

where

(2.14)

(2.15)


1 Trc The digital realization for the above equations requires adders, subtractors, multipliers and dividers. All these entities are available in the library of Quartus-II tool. Apart from these arithimetic logic entities, D-Flip Flops are also needed for storing previous data values, in the case of performing integration. e (n − 1) = iL (n − 1) (d) − Vc (n − 1)

2.3.4

FPGA Design Files

FPGA Design files of Buck Converter are placed in ‘fpga program files’ folder. Fig. 2.3 and Fig. 2.4 are the FPGA design files to implements the equations given in eqns 2.14 and 2.15. 2.3.5

Waveforms

The program developed (using the equations 2.14 and 2.15 ) for direct online simulation in Quartus II tool are downloaded into FPGA board. The waveforms are recorded and are compared with the off-line simulation waveforms as shown in Figs 2.5 and 2.6.

18 Real-Time Simulation Of SMPC

Figure 2.3: FPGA Design File of Buck Converter for PWM wave generation and DAC Interfacing

2.3 Buck Converter

Figure 2.4: FPGA Design File of Buck Converter for Vc and iL

19

20

Real-Time Simulation Of SMPC

2 1.5 Vg 1 0.5 0

0

0.001

0.002

0.003

0.004

0.005

0.006

0.007

0.008

0.009

0.01

0

0.001

0.002

0.003

0.004

0.005

0.006

0.007

0.008

0.009

0.01

0

0.001

0.002

0.003

0.004

0.005

0.006

0.007

0.008

0.009

0.01

1 Vo 0.5

0 1.5 iL 1 0.5 0

t (sec)

Figure 2.5: Vg, Vo and iL waveforms (off-line simulation) for Buck Converter Scale: y-axis: all quantities in per unit

Figure 2.6: Vg, Vo and iL waveforms (real time simulation) for Buck Converter Scale: y-axis: 1 division = 5V (1 per unit = 5V )

2.4 Boost Converter

2.4

21

Boost Converter

Boost converter is also known as step-up converter. It produces a higher output voltage than the dc input voltage. Thus the gain of the converter is more than unity. The practical range of duty ratio is 0 to 0.66. Figure 2.7 shows the circuit diagram of a Boost Converter with a resistive load and a low pass filter. L

iL

Vg

off

+

on

−

Vc

C

R

Figure 2.7: Boost converter The dynamic equations and output equations of the Boost converter are obtained as follows. During ON time: diL = Vg dt Vc dvc =− C dt r L

(2.16a) (2.16b)

During OFF time: diL = Vg − Vc dt dvc Vc C = il − dt r L

(2.17a) (2.17b)

Combining equations 2.16 and 2.17 , following equations are obtained diL = Vg − Vc (1 − d) dt dvc Vc C = iL (1 − d) − dt r L

vo = v c

(2.18a) (2.18b) (2.19)

22

Real-Time Simulation Of SMPC

Vo =

Vg (1 − d)

(2.20)

Io (2.21) (1 − d) The above equations describe the modelling of the boost converter. The Eqn 2.18 is the dynamic equation of the converter. Eqn 2.20 and Eqn 2.21 give the relation between input-output voltage and current respectively. Ig =

2.4.1

Power Circuit Design

A. Design of Inductor : In each sub period [dTS and (1 − d)TS ], the rate of change of current is constant. The current ripple can be determined using the following equation. δIL =

Vg dTS L

(2.22)

δIL d(1 − d)2 RTS = δi = (2.23) IL L The value of the inductance L is designed such that δi is 10% of the output current Io . B. Design of Capacitor : The charging and discharging current of the capacitor decides the voltage ripple. The entire ac part of the inductor current flows into the capacitor. δVo =

Io dTS δQ = C C

(2.24)

δVo dTS = δv = (2.25) Vo RC The capacitor C is designed for δv to be 1% of the output voltage Vo . 2.4.2

Implementation

A. Parameters : The parameters of the Boost Converter used in the simulation program are shown in the Table 2.4. B. Base Values for Different Quantities : As the implementation is digitally realized, there arises the need for following a pu system for simple understanding. For perunitization of different quantities, the base values are required, which can be chosen as per convenience. The Table. 2.5 shows the base values for voltage, resistance and current. The other bases are calculated from the above mentioned base quantities.

2.4 Boost Converter

23 Quantity Vg L R C Tlr Trc d Ts 4t

Value 2.5V 0.32mH 5Ω 102.4µF 0.000064 0.000512 0.25 102.4µsec 3.2µsec

Table 2.4: Parameters of the Boost converter Voltage (Vb ) resistance (Rb ) Current (Ib )

10V 5Ω 2A

Table 2.5: Base Values for the Boost converter 2.4.3

Normalized Equations

In this section, all the equations are perunitized and are made ready for implementation. diL = Vg − Vc (1 − d) (2.26a) dt dvc Vc C = iL (1 − d) − (2.26b) dt r Dividing the above equations by ib , and Vb respectively, Z
1 Vg(pu) − Vc(pu) (1 − d) dt iL(pu) = Tlr Z
1 Vc(pu) = iL(pu) (1 − d) − Vc(pu) dt Trc Using the Eulers Method of integration, the equation in digital domain can be written as L

where

iL (n) = iL (n − 1) + e (n − 1) (4t) e (n − 1) = Vg (n − 1) − (1 − d)Vc (n − 1)

where

(2.27)
1 Tlr

Vc (n) = Vc (n − 1) + e (n − 1) (4t) e (n − 1) = (1 − d)iL (n − 1) − Vc (n − 1)

(2.28)
1 Trc

24

Real-Time Simulation Of SMPC

2.4.4

FPGA Design Files

FPGA Design files of Boost Converter are placed in ‘fpga program files’ folder. Fig. 2.8 and Fig. 2.9 are the FPGA design files to implement the equations given in eqns 2.27 and 2.28. 2.4.5

Waveforms

The program developed (using the equations 2.27 and 2.28 ) for direct online simulation in Quartus II tool are downloaded into FPGA board. The waveforms are recorded and are compared with the off-line simulation waveforms as shown in Figs 2.10 and 2.11.

2.4 Boost Converter

Figure 2.8: FPGA Design File of Boost Converter for PWM wave generation and DAC Interfacing

25

26 Real-Time Simulation Of SMPC

Figure 2.9: FPGA Design File of Boost Converter for Vc and iL

2.4 Boost Converter

27

2 1 Vg 0 −1

0

0.001

0.002

0.003

0.004

0.005

0.006

0.007

0.008

0.009

0.01

0

0.001

0.002

0.003

0.004

0.005

0.006

0.007

0.008

0.009

0.01

0

0.001

0.002

0.003

0.004

0.005

0.006

0.007

0.008

0.009

0.01

0.8 0.6 Vo 0.4 0.2 0 1.5

iL

1 0.5 0

time (sec)

Figure 2.10: Vg, Vo and iL waveforms (off-line simulation) for Boost Converter Scale: y-axis: all quantities in per unit

Figure 2.11: Vg, Vo and iL waveforms (real time simulation) for Boost Converter Scale: y-axis: 1 division = 2V (1 per unit = 5V )

28

Real-Time Simulation Of SMPC

2.5

Buck-Boost Converter

Buck-Boost converter can be obtained by the cascade connection of the two basic converters: the Buck converter and the Boost converter. The gain of this converter may be above or below unity. The output polarity is opposite to that of input polarity. The practical range of duty ratio is 0 to 0.66. Figure 2.12 shows the circuit diagram of a Boost Converter with a resistive load and a low pass filter. on Vg

off

+

Vc

L

−

C

R

iL

Figure 2.12: Buck-Boost Converter The dynamic equations and output equations of the Buck-Boost converter are obtained as follows. During ON time: diL = Vg dt Vc dvc =− C dt r L

(2.29a) (2.29b)

During OFF time: diL = Vc dt Vc dvc = −il − C dt r L

(2.30a) (2.30b)

Combining equations 2.29 and 2.30 , following equations are obtained diL = Vg (d) + Vc (1 − d) dt Vc dvc = −iL (1 − d) − C dt r L

vo = v c

(2.31a) (2.31b) (2.32)

2.5 Buck-Boost Converter

29

Vo = −Vg

d (1 − d)

(2.33)

d (2.34) (1 − d) The above equations describe the modelling of the Buck-Boost converter. The Eqn 2.31 is the dynamic equation of the converter. Eqn 2.33 and Eqn 2.34 give the relation between input-output voltage and current respectively. Ig = I o

2.5.1

Power Circuit Design

A. Design of Inductor : In each sub period [dTS and (1 − d)TS ], the rate of change of current is constant. The current ripple can be determined using the following equation. δIL =

Vg dTS L

(2.35)

δIL (1 − d)2 RTS = δi = (2.36) IL L The value of the inductance L is designed such that δi is 10% of the output current Io . B. Design of Capacitor : The charging and discharging current of the capacitor decides the voltage ripple. The entire ac part of the inductor current flows into the capacitor. δVo =

Io dTS δQ = C C

(2.37)

dTS δVo = δv = (2.38) Vo RC The capacitor C is designed for δv to be 1% of the output voltage Vo . 2.5.2

Implementation

A. Parameters : The parameters of the Buck-Boost Converter used in the simulation program are shown in the Table 2.6. B. Base Values for Different Quantities : As the implementation is digitally realized, there arises the need for following a pu system for simple understanding. For perunitization of different quantities, the base values are required, which can be chosen as per convenience. The Table. 2.7 shows the base values for voltage, resistance and current. The other bases are calculated from the above mentioned base quantities.

30

Real-Time Simulation Of SMPC Quantity Vg L R C Tlr Trc d Ts 4t

Value 7.5V 0.64mH 5Ω 102.4µF 0.000128 0.000512 .25 102.4µsec 3.2µsec

Table 2.6: Parameters of the Buck-Boost converter Voltage (Vb ) resistance (Rb ) Current (Ib )

10V 5Ω 2A

Table 2.7: Base Values for Buck-Boost converter 2.5.3

Normalized Equations

In this section, all the equations are perunitized and are made ready for implementation. diL = Vg (d) + Vc (1 − d) dt dvc Vc C = −iL (1 − d) − dt r

(2.39a)

L

(2.39b)

Dividing the above equations by ib , and Vb respectively, Z
1 iL(pu) = dVg(pu) + Vc(pu) (1 − d) dt Tlr Z
1 Vc(pu) = − iL(pu) (1 − d) + Vc(pu) dt Trc

Using the Eulers Method of integration, the equation in digital domain can be written as iL (n) = iL (n − 1) + e (n − 1) (4t) where e (n − 1) = (dVg (n − 1) + (1 − d)Vc (n − 1) Vc (n) = Vc (n − 1) + e (n − 1) (4t)

(2.40)
1 Tlr (2.41)

2.5 Buck-Boost Converter

where e (n − 1) = − (1 − d)iL (n − 1) − Vc (n − 1) 2.5.4

31


1 Trc

FPGA Design Files

FPGA Design files of Buck-Boost Converter are placed in ‘fpga program files’ folder. Fig. 2.13 and Fig. 2.14 are the FPGA design files to implement the equations given in eqns 2.40 and 2.41. 2.5.5

Waveforms

The program developed (using the equations 2.40 and 2.41 ) for direct online simulation in Quartus II tool are downloaded into FPGA board. The waveforms are recorded and are compared with the off-line simulation waveforms as shown in Figs 2.15 and 2.16.

32 Real-Time Simulation Of SMPC

Figure 2.13: FPGA Design File of Buck-Boost Converter for PWM wave generation and DAC Interfacing

2.5 Buck-Boost Converter

Figure 2.14: FPGA Design File of Buck- Boost Converter for Vc and iL

33

34

Real-Time Simulation Of SMPC

2 1 Vg 0 −1

0

0.001

0.002

0.003

0.004

0.005

0.006

0.007

0.008

0.009

0.01

0

0.001

0.002

0.003

0.004

0.005

0.006

0.007

0.008

0.009

0.01

0

0.001

0.002

0.003

0.004

0.005

0.006

0.007

0.008

0.009

0.01

0 −0.1 Vo −0.2 −0.3 −0.4 0.8 0.6 i 0.4 L 0.2 0

time (sec)

Figure 2.15: Vg, Vo and iL waveforms (off-line simulation) for Buck-Boost Converter Scale: y-axis: all quantities in per unit

Figure 2.16: Vg, Vo and iL waveforms (real time simulation) for Buck-Boost Converter Scale: y-axis: 1 division = 2V (1 per unit = 5V )

2.6 Conclusion

2.6

Conclusion

In this chapter Real Time Simulation of basic Switching Power Converters is presented. The Real time simulation is done by using Quartus II software (version 5.0). Results are also verified with MATLAB Simulation results. MATLAB models used for offline simulation are placed in folder named simulinkprogramfiles.

35

36

Real-Time Simulation Of SMPC

Chapter 3

Real-Time Simulation of Separately Excited DC Machine 3.1

Introduction

The Direct Current machine have been dominating the field of adjustable speed drives for over a century; they are still the most common choice if a controlled electric drive operating over a wide speed range is specified. This is due to their excellent operational properties and control characteristics.

3.2

Open Loop Control of DC Machine

The DC motor model used in the simulation is shown in Fig. 3.1. The model represents a separetly excited dc motor. The mechanical load is defined by the parameters J, B and mL . The state equations describing the dc motor drive used in the simulation are the followings: di = −Ra Ia − Ke ωm + Va dt dωm J = Ke Ia − Bωm − mL dt La

(3.1a) (3.1b)

The equations (3.1) are normalized with the help of rated values of Vb , Ib and ωmb . Other base values which can be inferred from these base values. The equations (3.1) are formulated in a way suitable for block diagram representation.   dIa∗   ∗    ∗  −Ra∗ −Ke∗ Ia 1 0 Va  τeb dt  (3.2) + ∗  =  ∗ dωm Ke∗ −B ∗ ωm 0 −1 m∗L τmb dt where x∗ equals to perunitized value of x.

38

Real-Time Simulation of Separately Excited DC Machine

+

Ia

Va

M

L

Ra

Ia

1

kφ

La

S

B

+

E = k φω −

_

ω

1

J

E

Electrical Section

kφ Mechanical Section

Ra , La = Armature resistance (0.024 Ω ) and inductance (0.7 mH) k φ = Ke = EMF Constant (frequency constant) = 8.5 v/rad/s B = Motar and load viscous friction coefficient = 0 J = Motar and load Inertia = 8.4 kg−m 2 Va = Input Voltage = 460 V , M L = Load torque Rated speed =500 rpm, Rated Power = 300 kW

Figure 3.1: DC Motor Model. Any Electrical machine can be represented in the form of state equations (3.2). A generalized user machine block(Fig 3.2) is developed such that any machine equations can be solved by knowing the state matrix and input matrix. xn−1 A11 yn−1 A12 Va B11 mL B12 xn−1 A21 yn−1 A22 Va B21 mL B22

Multiply Multiply Multiply

Integration

ADD

Block

Multiply

∆τ τe

Multiply

e yn−1

Multiply Multiply

xn−1

yn Integration

ADD

Block

yn−1

∆τ τm

Multiply

A= System Matrix

xn

e xn−1

B= Input Matrix

∆τ= Step Size

Figure 3.2: Generalized Machine Model.

3.2.1

Implementation

A Parameters : The details of the separetly excited DC machine and the values of other quantities are given in table. 3.1 and 3.2

3.2 Open Loop Control of DC Machine

39

VOLTAGE

460 V

RATED CURRENT

690 A

POWER

300 kW

SPEED

500 rpm

Table 3.1: Details of the DC Motor Voltage (Vb )

460V

Current (Ib )

690A

Mechanical Speed(ωmb )

2π ∗

Nb 60

= 52.359rad/sec

Ra∗

0.0359

Ke∗

0.9675

m∗L

1.0000

τeb

0.0011

τmb

0.0726

Step time (∆t)

6.400µ

Table 3.2: Parameters B PU System Followed : The Table 3.3 shows the digital equivalent for the pu values. The digital equivalent for a negative pu value is chosen as the 1’s compliment its corresponding positive pu value. pu value

Equivalent digital Value

Equivalent decimal value

1 pu

F F F F FH

1048575d

0 pu

00000H

0d

F 00001H

15728641d

-1 pu(24bit)

Table 3.3: PU Values

3.2.2

FPGA Design Files

FPGA Design files of DC Machine are placed in ‘fpga program files’ folder. Similarly simulink files are in ‘simulinkprogramfiles’ folder. Fig. 3.3 is the FPGA design file for DC machine. Real-time simulation of DC machine open loop consumed 4% of overall logic elements in FPGA board.

40

Real-Time Simulation of Separately Excited DC Machine

Figure 3.3: FPGA Design File for DC Machine 1.5

(1)

1 0.5 0 1.5

(2)

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1 0.5 0 10

(3)

0

5 0 −5 2

(4)

1 0

Time

(a)

(b)

Figure 3.4: DC Machine (1) Input Voltage (2) Load Torque (3) Armature Current (4) Speed. (a) MATLAB/SIMULINK OFF-Line Simulation Waveforms (b) FPGA Real-Time Simulation Waveforms Fig. 3.4(a) (OFF-Line Simulation Waveforms ) and Fig. 3.4(b) (Real Time Simulation Waveforms) shows the waveforms obtained for th DC machine in open loop.

3.3 Closed Loop Control of DC Machine vω m−ref (s)

vω m−error (s) GN(s) v ia−ref (s) + Limiter Speed Controller

41

v ia−error (s) Gc (s) + Limiter v ia−fb (s)

vω m−fb (s)

v ref (s)

Current Controller

Gch (s)

v a (s)

ωm DC MOTOR

i

Chopper

G2 (s)

G1 (s)

Current Feedback

Speed Feedback

Figure 3.5: Block Diagram of the DC Motor Drive

3.3

Closed Loop Control of DC Machine

In practice,the choice of DC motor drive is normally motivated by the possibility of operating over a wide range of the torque/speed plane with low losses and matching the behaviour of the motor to the needs of the mechanical load. To achieve the desired operating characteristics in the presence of supply-and load -disturbances,feedback control is usually necessary. Another reason why DC drives are normally contained in feedback loops is that the armature of a large motor represents a very small impedance which when supplied with nominal voltage would result in an excessive current of up to 10 times the nominal value. Under normal conditions, this is prevented by the induced armature voltage e, which cancels most of the applied voltage Va so that only the difference is driving the armature current ia . In transient operation,there is always the danger of excessive current due to rapidly changing armature voltage or speed; the same is true with a steady state overload of the motor. It is therefore important to provide a fast current or torque limit to protect the motor, the power supply and the load. This is best realized by FEEDBACK CONTROL establishing an effective safeguard against electrical and mechanical stresses. In most cases, the user of a controlled drive wants to be able to select a reference speed vwm−ref which the motor should maintain as long as it is not overloaded. The control schematic of a separately excited dc motor drive is shown in Fig. 3.5. The motor drive shown is a speed controlled system. The dc output of a converter is fed to the armature of the dc drive. The field is separately excited, and the field supply is kept constant for armature control. The dc motor has a tacho generator whose output is utilized for closing the speed loop. The output of the tachogenerator is filtered to remove the ripples to provide the signal, vwm−f b . The speed command vwm−ref is compared to the speed signal to produce a speed error sinal. This signal is processed through a proportional-plus-integral(PI) controller to determine the torque command. The torque command is limited, to keep it with in safe current limits, and

42

Real-Time Simulation of Separately Excited DC Machine

the current command is obtained by propoer scaling. The armature current command via−ref is compared to the actual armature current via−f b to have a zero current error. In case there is an error, a PI current controller processes it to alter the control signal vref . The control signal accordingly modifies the triggering angle of the converter and so the dc output of the converter. The inner current loop assures a fast current response and hence also limits the current to a safe preset level. This inner current loop makes the converter a linear current amplifier. The outer speed loop ensures that the actual speed is always equal to the command speed and that any transient is overcome within the shotest feasible time without exceeding the motor and converter capability.

3.4 3.4.1

Transfer Functions Of The Subsystems DC Motor and Load

The equivalent circuit of the separately excited DC motor can be represented as in Fig. 3.5. The transfer function first between speed and input voltage is given by 1

F1

ωm (s) = Ra 1 = Va (s) 1 + =

1 1 cφ + sTa J s (cφ)2 Ra (Ta s+1)Js

1 cφ

(3.3)

1 + sTem (1 + sTa )

where Ta = La /Ra is electrical time constant and Tem = JRa /(cφ)2 is electromechanical time constant. The transfer function between armature current and input voltage is given by 1

F2

ωm (s) ia (s) Js ia (s) cφ = = = Va (s) Va (s) ωm (s) 1 + sTem (1 + sTa ) cφ 1 sTem = Ra 1 + sTem (1 + sTa )

(3.4)

Similarly the transfer function between speed and load torque is given by F3 =

Ra ωm (s) 1 + sTa =− 2 mL (s) (cφ) 1 + sTem (1 + sTa )

(3.5)

The transfer function between armature current and load torque is given by 1

ia (s) cφ = F4 = mL (s) 1 + sTem (1 + sTa )

(3.6)

3.4 Transfer Functions Of The Subsystems

3.4.2

43

Chopper

The chopper is modeled as first-order lag with a gain of G. The time delay Td corresponds to the average conduction time. The transfer function is then Gch (s) =

Va (s) G = vref (s) 1 + sTd

(3.7)

where G = Vs /vref m , Vs is input to the chopper and vref m is the maximum control voltage. Increasing the chopper frequency decreases the delay time, and hence the transfer function becomes a simple gain. 3.4.3

Current and Speed Controllers

The current and speed controllers are of proportional-integral type. They are represented as Kc (1 + sTc ) vref (s) = via−ref (s) − via−f b (s) sTc

(3.8)

via−ref (s) KN (1 + sTN ) = vwm−ref (s) − vwm−f b (s) sTN

(3.9)

Gc (s) =

GN (s) =

where the subscripts c and N correspond to the current and speed controllers, respectively. The K and T correspond to the gain and time constants of the controller. Design of controllers is discussed in ref. [3] 3.4.4

Current Feedback

The gain of the current feedback is K2 . In the case of a filtering requirement, a low-pass filter can be included in the analysis. The equivalent transfer function is represented as via−f b (s) K2 G2 (s) = = (3.10) ia (s) 1 + sT2 where T2 is the smoothing filter time constant. 3.4.5

Speed Feedback

The transfer function of the speed feedback filter is G1 (s) =

K1 vωm−f b (s) = ωm (s) 1 + sT1

(3.11)

where K1 is gain, T1 is the time constant and vωm−f b is one of the inputs to speed error block.

44

Real-Time Simulation of Separately Excited DC Machine

3.5

Simulation of DC Motor Drive

The equations for various subsystems are derived in the last section and then assembled for real time simulation in this section. It is assumed that field current is constant. 3.5.1

DC Motor Equations

The motor equations are given by (3.1) and the normalized equations are given by (3.2) 3.5.2

Speed-Feedback Filter

The transfer function of the speed feedback filter is given by equation (3.11). In time domain, this equation can be arranged as following: dvωm−f b 1 = (K1 ωm − vωm−f b ) dt T1

(3.12)

This equation is normalized and resulted in the following form: ∗ dvωm−f 1 K1 ωmb ∗ b ∗ = ( ωm − vωm−f b) dt T1 Vb

(3.13)

By using Euler’s method of integration,   ∆t K1 ωmb ∗ ∗ ∗ ∗ ωm (n − 1) − vωm−f b (n − 1) vωm−f b (n) = vωm−f b (n − 1) + T1 Vb (3.14) 3.5.3

Current-Feedback Filter

The transfer function of the current feedback filter is given by equation (3.10). In time domain, this equation can be arranged as following: dvia−f b 1 = (K2 ia − via−f b ) dt T2

(3.15)

This equation is normalized and resulted in the following form: ∗ dvia−f 1 K2 I b ∗ b ∗ = ( i − via−f b) dt T2 Vb a

By using Euler’s method of integration,   ∆t K2 Ib ∗ ∗ ∗ ∗ i (n − 1) − via−f b (n − 1) via−f b (n) = via−f b (n − 1) + T2 Vb a

(3.16)

(3.17)

45

Figure 3.6: Filter

3.5 Simulation of DC Motor Drive

46

Real-Time Simulation of Separately Excited DC Machine

3.5.4

Speed Controller

The transfer function of the speed controller is given by equation (3.9). In time domain, this equation can be arranged as following: Z 1 via−ref = KN (vwm−ref − vwm−f b ) dt + KN (vwm−ref − vwm−f b ) (3.18) TN This equation is normalized and resulted in the following form: Z 1 ∗ ∗ ∗ ∗ ∗ via−ref = KN (vwm−ref − vwm−f b ) dt + KN (vwm−ref − vwm−f b ) T | {z } |N {z } P −Controller I−Controller

(3.19)

By using Euler’s method of integration, ∗ via−ref (n) =

∆t ∗ ∗ KN vwm−error (n − 1) + y(n − 1) + KN vwm−error (n) (3.20) TN

∗ ∗ ∗ where vwm−error = vwm−ref − vwm−f b , y(n − 1) is previous value of I-Controller.

In order to maintain the drive system in safe operating region, the current ∗ is limited to allowable maximum limits determined by the refernce via−ref motor peak current capabilities. This reference limit is integrated into the simulation as ∗ ∗ 0 ≤ via−ref ≤ via−ref (3.21) −max

3.5.5

Current Controller

The transfer function of the current controller is given by equation (3.8). In time domain, this equation can be arranged as following: Z 1 vref = Kc (via−ref − via−f b ) dt + Kc (via−ref − via−f b ) (3.22) Tc This equation is normalized and resulted in the following form: Z 1 ∗ ∗ ∗ ∗ ∗ vref = Kc (via−ref − via−f b ) dt + Kc (via−ref − via−f b ) Tc | {z } | {z } P −Controller

(3.23)

I−Controller

By using Euler’s method of integration, ∗ vref (n) =

∆t ∗ ∗ Kc via−error (n − 1) + y(n − 1) + KN via−error (n) Tc

(3.24)

∗ ∗ ∗ − via−f where via−error = via−ref b , y(n − 1) is previous value of I-Controller.

47

Figure 3.7: PI-Controller

3.5 Simulation of DC Motor Drive

48

Real-Time Simulation of Separately Excited DC Machine

Figure 3.8: Saturation 3.5.6

Chopper

The transfer function of the chopper is given by equation (3.7). At high frequency of chopper, the transfer function becomes a simple gain. Va = G vref

(3.25)

This equation is normalized and resulted in the following form: ∗ Va∗ = G vref

(3.26)

Discretizing the above equation results in ∗ Va∗ (n) = G vref (n)

3.6

(3.27)

Implementation

A. Closed Loop Parameters : The details of the separetly excited DC machine and the values of other quantities are given in table. 3.4. B. PU System Followed : The Table 3.3 shows the digital equivalent for the pu values. The digital equivalent for a negative pu value is chosen as the 1’s compliment its corresponding positive pu value.

3.7

FPGA Design Files

FPGA Design files of Closed loop DC Machine are placed in ‘fpga program files’ folder. Similarly simulink files are in ‘simulinkprogramfiles’ folder. Fig. 3.6,

3.8 Conclusion

49 DC Bus Voltage

650V

Maximum Current Chopper Switching frequency

1200A 1000Hz

K1

0.1909

T1

0.0167

K2

0.0083

T2

0.0016

KN

1.0308

TN

0.0837

KC

0.3089

TC

0.0292

G

65

Step time (∆t)

6.400µ

Table 3.4: Parameters Fig. 3.7 and Fig. 3.8 are the FPGA design files respectively, to implement filter, PI controller and saturation block. Figure 3.9 shows the waveforms obtained for th DC motor in close loop. Initially,the motor is running at no load along with full load refernce and 50 percent torque is applied after some time. Motor rotates in reverse direction when speed reference has changed from positive to negitive.

3.8

Conclusion

DC Motor open loop as well as closed loop has implemented in FPGA based controller. Both Real-time and offline simulation results are presented.

50

Real-Time Simulation of Separately Excited DC Machine

Figure 3.9: DC Motor Drive with Speed and Current Feedback [ (1) ωref (2) mL (3) ia (4) ωm ]

0.05

ωref

0

−0.05 1

mL

2

1

1.5

2

2.5

0

0.5

1

1.5

2

2.5

3

0 −2 2

ωm

0.5

0.5 0

ia

0

0

0.5

1

1.5

2

0

0.5

1

1.5

2

2.5

0 −2

2.5

time

Figure 3.10: DC Motor Drive with Speed and Current Feedback

Chapter 4

Real-Time Simulation of Induction Machine 4.1

Introduction

In the past, mostly DC motors alone were used for variable speed applications. With the advances in power electronics, induction motors are replacing DC Motors in variable speed drives. The 3-phase induction motors are most preferred for drive applications because of ruggedness, smaller size and low cost. The basic theory of the squirrel cage induction motor is reviewed here.

4.2

Basic Principle of Operation

The induction motor has a three phase winding on the stator and a rotor cage with end rings which electrically behaves as another three phase winding. When the stator windings are supplied with balanced three phase currents, a revolving magneto motive force is produced in the air gap. If the stator winding is designed properly, the spatial distribution of the stator mmf at any instant of time can be assumed to be sinusoidal. The location of the positive peak (north pole) of this mmf is taken as its instantaneous position. The speed of rotation of the stator mmf wave is given by 120 fs revolution per minute (4.1) Ns = p where fs is the frequency of the stator currents; P is the number of poles. Because of the stator mmf, a rotating flux wave is produced in the airgap of the machine. This flux wave has also sinusoidal spatial distribution at any instant of time and rotates in space in the same direction and with the same speed as the stator mmf. The speed of the stator mmf (or the flux) is referred to as the synchronous speed. As the flux sweeps past the rotor conductors, emfs are induced in these conductors. Since the rotor bars are shorted by the end rings, currents flow in

52

Real-Time Simulation of Induction Machine

Is Rs

I 'r Lls Ic

Vs

Rm

Io

L'lr Im

Lm

1:n

Vm

ws

E 'r = n s V m

R 'r

wr

Figure 4.1: Equivalent Circuit the rotor conductors. The interaction of the rotor currents and flux produces torque and the rotor begins to turn. The rotor attempts to catch up with the flux. However since this would result in disappearance of torque, an equlibrium is reached where the rotor runs at a speed such that the relative motion of the flux is sufficient to produce enough torque to sustain the rotor speed. If the rotor runs at a speed of N revolutions per minute, the relative speed of the flux with respect to the rotor is given by Nr = N s − N

(4.2)

The slip ’s’ of the machine is defined as the ratio Nr /Ns . Let ωr and ωs be the angular frequencies of the rotor and stator currents respectively. The airgap flux rotating at ωs electrical radians per second induces back emf Vm in the stator. The flux moves at a speed ωr with respect to the rotor. The corresponding emf induced in the rotor can be written as Er0 = n.s.Vm

(4.3)

where n is the rotor to stator turns ratio and s is slip. Therefore, the machine can be represented by an equivalent circuit as shown in figure 4.1. The two sides of the tranformer work at different frequencies, namely, ωr and ωs .

4.3 Modelling of Induction Machine using Space Phasors

53 bs

br is2

isb

ir1 irb

ε

ir2 is3

is1 ir3

ar

ira ε

Space Vector Transformation

isa

as

Figure 4.2: Twophase equivalent of a 3-phase induction motor

4.3

Modelling of Induction Machine using Space Phasors

The symmetrical three phase squirrel cage induction motor has a three phase system of coils on the stator and a cage on the rotor which can be considered to be equivalent to a three phase winding. The two sets of windings can be represented by two equivalent two phase coils as shown in Fig. 4.2. The rotor axis makes an angle ε (t) with respect to the stator axis. Two current space phasors is (t) and ir (t) can be defined for the stator and rotor current as follows: is (t) = isa (t) + jisb (t)

(4.4)

ir (t) = ira (t) + jirb (t)

(4.5)

The flux linkages of various coils can be written down as follows ψsa (t) = Ls isa (t) + M ira (t) cosε (t) − M irb (t) sinε (t)

(4.6)

ψsb (t) = Ls isb (t) + M ira (t) sinε (t) + M irb (t) cosε (t)

(4.7)

where Ls is self inductance of stator coils, M is the maximum value of mutual inductance between stator and rotor coils. Combining equations 4.6 and 4.7 to form the stator flux space phasor. ψ s (t) = ψsa (t) + jψsb (t) = Ls is (t) + M ir (t) ejε(t)

(4.8)

54

Real-Time Simulation of Induction Machine

Similarly the rotor flux linkage space phasor can be derived as ψ r (t) = ψra (t) + jψrb (t) = Lr ir (t) + M is (t) e−jε(t)

(4.9)

Note that Eqn 4.8 is with respect to stator coordinates and Eqn 4.9 is with respect to rotor coordinates. Multiplication of ejε(t) results in clockwise rotation of the coordinate system by an angle of ε (t), while e−jε(t) results in anticlockwise rotation of the coordinate system by the same angle. The voltage-current equations for the stator and rotor windings can be written as follows vsa (t) = Rs isa (t) +

dψsa (t) dt

(4.10)

vsb (t) = Rs isb (t) +

dψsb (t) dt

(4.11)

vra (t) = Rr ira (t) +

dψra (t) dt

(4.12)

dψrb (t) (4.13) dt With the help of equations 4.8, 4.9 the above equations can be rewritten as space phasors as follows, vrb (t) = Rr irb (t) +

dis (t) d + M [ir (t) ejε(t) ] dt dt

(4.14)

d dir (t) + M [is (t) e−jε(t) ] dt dt

(4.15)

v s (t) = vsa + jvsb = Rs is (t) + Ls

v r (t) = vra + jvrb = Rr ir (t) + Lr

For a squirrel cage induction motor v r (t) = 0. With the above two equations, the electrical behaviour of the machine is obtained. It can also be shown that the torque developed by the machine is given by 2P M Im[is (t) [ir (t) ejε(t) ]∗ ] (4.16) 32 Transformation of the rotor current equation 4.9 to the stator stationary coordinates can be done by multiplying ejε(t) , Md (t) =

isr (t) = ir (t) ejε(t)

(4.17)

Simplifying the above equations and separating out the real and imaginary parts, the following equations can be obtained. Rs isa (t) + σLs

M disa (t) M 2 − ωisb (t) − Rr isra (t) − M ωisrb (t) = vsa (t) (4.18) dt Lr Lr

4.4 Implementation

Rs isb (t) + σLs

55

disb (t) M 2 M + ωisa (t) + M ωisra (t) − Rr isrb (t) = vsb (t) (4.19) dt Lr Lr

Rr is ra (t) + σLr

Rr is rb (t) + σLr

J

dis ra (t) M M − Rs isa (t) + M ωisb (t) + Lr ωis rb (t) = − vsa (t) dt Ls Ls (4.20) M M dis rb (t) − M ωisa (t) − Rs isb (t) − Lr ωis ra (t) = − vsb (t) dt Ls Ls (4.21) 2P dωm = M [isra (t) isb (t) − isrb (t) isa (t)] − Ml dt 32 P dε (t) ωm = ω = 2 dt

(4.22)

(4.23)

i h 2 where σ = 1 − LMr Ls ωm - rotor speed in mechanical rad/sec ω-rotor speed in electrical rad/sec J-moment of inertia Ml -Load torque The above equations describe the complete dynamic behaviour of the induction machine. The Eqns. 4.18 and 4.19 serves the purpose of determning the stator voltage v s (t) and the eqns. 4.20 and 4.21 corresponding to the rotor, determine the machine electrical dynamic behaviour. The Eqn. 4.22 determines the mechanical dynamic behaviour of the machine.

4.4

Implementation

A. Parameters : The details of the induction motor is presented in Table. 4.1. The parameters of the Induction motor used in the simulation program are shown in the Table 4.2. VOLTAGE CURRENT POWER POLES (P) SPEED

240 V 40 A 1.5 KW 4 3000 rpm

Table 4.1: Details of the Induction Motor

56

Real-Time Simulation of Induction Machine Quantity Rs Lls Rr Llr M Ls = M + Lls Lr = M + Llr J B

Value O.2Ω 7.2mH 0.4011Ω 3.6mH 88mH 95.2mH 91.6mH 0.2Kg − m2 0.003

Table 4.2: Parameters of the Induction Motor B. Base Values for Different Quantities : As the implementation is digitally realized, there arises the need for following a pu system for simple understanding. For perunitization of different quantities, the base values are required, which can be chosen as per convenience. The Table. 4.3 shows the base values for voltage (chosen as per phase rated voltage of IM), current (chosen as more than the rated line current of IM and less than transient peak current) and frequency (chosen as rated frequency of IM). The other bases are calculated from the above mentioned base quantities. Voltage (Vb ) Current (Ib ) Frequency (fb ) Frequency in rad/sec (ωb ) Resistance(Rb ) Mechanical Speed(ωmb ) Torque(Mb )

240V 200A 50Hz 2π ∗ fb = 314.16rad/sec Vb Ib = 1.2Ω ωb = 157.08rad/sec P/2 3∗Vb ∗Ib = 916.73N − m ωmb

Table 4.3: Base Values

C. PU System Followed : The Table 4.4 shows the digital equivalent for the pu values. The digital equivalent for a negative pu value is chosen as the 1’s compliment its corresponding positive pu value. pu value 2 pu 1 pu 0 pu -1 pu(16bit) -2 pu(16bit)

Equivalent digital Value 7F F FH 3F F FH 000H C000H 8000H

Equivalent decimal value 32767d 16383d 0d 49152d 32768d

Table 4.4: PU Values

4.5 Normalized Equations

4.5

57

Normalized Equations

In this section, all the equations are perunitized and are made ready for implementation. The sampling time for the implementation is chosen as 25.6 µsec. The eqn. 4.18 is repeated here. M2 M disa (t) = vsa (t) + ωisb (t) + Rr isra (t) + M ωisrb (t) (4.24) dt Lr Lr Dividing the above equation by Vb , Rs isa (t) + σLs

disa(pu) (t) = esa(pu) (t) where dt M 2 ωb M ωb esa(pu) (t) =vsa(pu) (t) + ωpu isb(pu) (t) + Rr(pu) isra(pu) (t) + M ωpu isrb(pu) (t) Lr R b Lr Rb Z
1 esa(pu) (t) − Rs(pu) isa(pu) (t) dt =⇒ isa(pu) (t) = σLs Using the Eulers Method of integration, the equation in digital domain can be written as
Ts isa (n) = isa (n − 1) + esa (n − 1) − Rs(pu) isa (n − 1) σLs Note that, the sampling time Ts for the implementation is chosen as 25.6 µsec. Rs(pu) isa(pu) (t) + σLs

isa (n) = isa (n − 1) + (esa (n − 1) − 0.17pu isa (n − 1)) 0.0024pu

(4.25)

similarly other equations 4.19, 4.20, 4.21 and 4.22 can also be normalized. Table. 4.5 summarizes all the variables in the form easy for digital realization. All the operations are basically arithimetic operations. The digital realization for the above equations requires adders, subtractors, multipliers and dividers. All these entities are available in the library of Quartus-II tool. Apart from these arithimetic logic entities, D-Flip Flops are also needed for storing previous data values, in the case of performing integration.

4.6

FPGA Design Files

FPGA Design files of Induction Motor are placed in ‘fpga program files’ folder. Similarly simulink files are in ‘simulinkprogramfiles’ folder. Fig. 4.3 to Fig. 4.8 are the FPGA design files to implements the equations given in table 4.5.

4.7

Waveforms

The program developed (using the equations in table. 4.5) for direct online control of Induction machine in Quartus II tool are downloaded into FPGA board. The waveforms are recorded and are compared with the off-line simulation waveforms.

58

Real-Time Simulation of Induction Machine

√
2 pu Vs1 (n)

Vsa (n)

1.5 ∗

Vsb (n)

0.866 ∗

isa (n)

√
2 pu (Vs2 (n) − Vs3 (n))

isa (n − 1) − 0.00048puisa (n − 1) + 0.064pu ω (n − 1) isb (n − 1) + 0.00093puisra (n − 1) +0.066puω (n − 1) isrb (n − 1) + 0.00288puVsa (n − 1)

isb (n)

isb (n − 1) − 0.064pu ω (n − 1) isa (n − 1) − 0.00048puisb (n − 1) − 0.066pu ω (n − 1) isra (n − 1) +0.00093puisrb (n − 1) + 0.00288puVsa (n − 1)

isra (n)

isra (n − 1) + 0.00046puisa (n − 1) − 0.069puω (n − 1) isb (n − 1) − 0.001pu isra (n − 1) −0.072puω (n − 1) isrb (n − 1) − 0.00276puVsb (n − 1)

isrb (n)

isrb (n − 1) + 0.069pu ω (n − 1) isa (n − 1) + 0.00046puisb (n − 1) + 0.072pu ω (n − 1) isra (n − 1) −0.001puisrb (n − 1) − 0.00276puVsb (n − 1)

ωm (n)

ωm (n − 1) + [0.0038pu (isra (n) isb (n) − isrb (n) isa (n))] − 0.00074puMl (n − 1)

ω (n)

ωm (n)

Table 4.5: Equations for implementing in Digital Domain

4.7 Waveforms

Figure 4.3: FPGA Design File for isa

59

Real-Time Simulation of Induction Machine

Figure 4.4: FPGA Design File for isb

60

4.7 Waveforms

Figure 4.5: FPGA Design File for isra

61

Real-Time Simulation of Induction Machine

Figure 4.6: FPGA Design File for isrb

62

4.7 Waveforms

Figure 4.7: FPGA Design File for ωm

63

64

Real-Time Simulation of Induction Machine

Figure 4.8: FPGA Design File for Eulers Integration

4.7 Waveforms

65

Figure 4.9: Vsa*k and Vsb*k waveforms where k=1/(1.5*sqrt(2)) Scale: y-axis: 1 per unit = 5V = 240v

3 2 1

Vsa

0 −1 −2 −3 0.5

0.51

0.52

0.53

0.54

0.55

0.56

0.57

0.58

0.59

0.6

0.51

0.52

0.53

0.54

0.55 Time

0.56

0.57

0.58

0.59

0.6

3 2 1

Vsb

0 −1 −2 −3 0.5

Figure 4.10: Vsa and Vsb waveforms Scale: y-axis: 1 per unit = 1V = 240v

66

Real-Time Simulation of Induction Machine

Figure 4.11: isa ,isb , isra and isrb waveforms Scale: y-axis: 1 per unit = 5V = 200A

1

Isa

0 −1 0.5 1

Isb

0.8

0.9

1

1.1

0.6

0.7

0.8

0.9

1

1.1

0.6

0.7

0.8

0.9

1

1.1

0.6

0.7

0.8 Time

0.9

1

1.1

0 −1 0.5 1

Isrb

0.7

0 −1 0.5 1

Isra

0.6

0 −1 0.5

Figure 4.12: isa ,isb , isra and isrb waveforms Scale: y-axis: 1 per unit = 1V = 200A

4.7 Waveforms

67

Figure 4.13: ωm and Mg ∗ 0.2/16 waveforms

Scale:

y-axis1: 1 per unit = 5V = 157.08rad/sec; y-axis2: 1 per unit =5V = 916.73N − m

1.2 1 0.8 0.6

ωm(pu)

0.4 0.2 0 −0.2

0

0.2

0.4

0

0.2

0.4

0.6

0.8

1

0.6

0.8

1

0.06 0.04 0.02

M *0.2 g

0

−0.02 −0.04

Time

Figure 4.14: ωm and Mg ∗ 0.2 waveforms

Scale: y-axis1: 1 per unit = 1V = 157.08rad/sec; y-axis2: 1 per unit = 1V = 916.73N − m

68

Real-Time Simulation of Induction Machine

4.8

Conclusion

The principle of direct on line start Induction Motor has been explained. It is implemented in FPGA based controller. Both Real-time and offline simulation results are presented.

Chapter 5

V/F Control of Induction Motor Drive 5.1

Introduction

Variable Speed Drives (VSDs) are increasingly becoming popular in the industry. Many of the speed control applications such as Fan/Pump drives do not require very good dynamic performance. In such appications the most suitable method of speed control of Induction Motors is V/F control. In this Chapter, the implementation of a V/F Drive controller in FPGA is explained.

5.2

Basic Principle of V/F operation

By keeping the airgap flux constant, and varying the stator frequency ωs , a family of torque speed curves can be obtained for the Induction Motor as shown in Fig. 5.1. This method of speed control is also referred to as constant flux control. Note that constant flux control is only possible up to rated voltage and frequency. For further increase in the frequency beyond rated frequency, if the voltage be increased proportionally this would exceed the rating of the machine. Therefore, beyond the rated frequency the peak torque capability of the motor will come down as the airgap flux reduces below the rated value. This region is known as field weakening region. To keep the airgap flux constant, it is sufficient to keep the ratio of induced emf to stator frequency constant [5]. But this is difficult as the induced emf cannot be measured directly. However this can be done in an approximate manner by keeping the ratio of terminal voltage Vs to ωs a constant. Hence this method is popularly known as V/F control. The terminal voltage and the airgap voltage are reasonably close in magnitude at speeds above 10% of rated speed. At very low speeds (and hence stator frequencies) the drop in the stator resistance and leakage reactance becomes appreciable in magnitude compared to the airgap voltage. Therefore, at low speeds, keeping ωVss constant is not equivalent to

70

V/F Control of Induction Motor Drive

f1

T max

f2

f3

f4

Torque

Field weakening region

Speed

Figure 5.1: Torque-Speed Characteristics of Induction Motor for Constant Flux Control keeping the flux constant. To some extent the drop in torque ability at low speeds can be counterbalanced by giving a boost to the stator voltage Vs at low frequencies above the constant Vfs value. Fig. 5.2 shows one example of a v/f relation. In a V/F drive, the controller produces the required reference

V s(pu) 1.0

0.1 0.1

1.0

f s(pu)

Figure 5.2: V/F relation including low frequency voltage boost frequency command in accordance with the v/f relation. This command is then used by a modulator to produce the gating pulses for the inverter. The inverter

5.3 Sine-Triangle Modulation

71

subsequently drives the Induction Motor. In the following section a popular modulation technique known as Sine-Triangle Pulse Width Modulation (SinePWM) is explained.

5.3

Sine-Triangle Modulation

In Sine-Triangle modulation the duty cycle of the inverter switches is varied in a sinusoidal manner. Because of this, the average of the output voltage in each switching cycle will also vary sinusoidally [5]. This results in an output voltage whose harmonics are at the switching frequency and its sidebands. For obtaining Sine-Triangle PWM, the modulating sine wave is compared with a triangular carrier. For three-phase inverter, three reference sine waves which are shifted each other by 120o are compared against the carrier. The reference waves are produced by the controller preceding the modulator. The PWM signals thus obtained are used for the upper switches of each inverter legs. Fig. 5.3 shows the production of PWM signals for one phase. The lower switches are controlled by the complimentary signals for the respective upper switches. Fig. 5.4 shows the three-phase Voltage Source Inverter (VSI). The gate pulses for the switches are marked in the figure. The amplitude Ar of the reference sine wave is kept less than the amplitude r Ac of the carrier for linear modulation. The ratio m = A is called modulation Ac index. The maximum value of m is 1 for linear modulation. For m greater than 1, the middle pulses begin merging. This will introduce lower order harmonics. This case is known as overmodulation. Here only linear modulation is dealt with. For varying the amplitude of the output voltages produced by the VSI, the modulation index is varied. Similarly, for varying the output frequency, the referece frequency is varied. For low power drives where higher switching frequency is allowed, synchronisation of carrier and reference is not critical if the frequency ratio mf = ffrc is more than 21 [5]. In the forgoing discussion, asynchronous modulation is assumed. 2 pu

Ac

Tc

Ar

1 pu

PWM Tr

Figure 5.3: Sine-Triangle PWM

72

V/F Control of Induction Motor Drive

Sv

DC link

Su

Sw U

Su

Sv

Sw

V W

Figure 5.4: Three Phase VSI

5.4

Implementation of V/F Sine-Triangle Modulator in FPGA

In this section implementation of a V/F sine-triangle modulator with asynchronous PWM is described. The logical steps can be summarized as follows: • Generation of V/F sine references • Generation of Triangle carrier • PWM generation • Slow Start These are detailed in the following. 5.4.1

Generation of V/F sine waves

For sine wave generation 1024 samples per cycle are used. For each sample, the angle θ is incremented in steps of ∆θ. Calculation of ∆θ is as follows: Z θ = ωdt (5.1) ∆θ = 2πf Ts

(5.2)

5.4 Implementation of V/F Sine-Triangle Modulator in FPGA

73

where Ts is the sampling time. ∆θpu = fb .Ts .fpu = 50 × 102.4µs × fpu = 5.12 × 10−3 × fpu

(5.3)

It is to be noted that θb is 2π and fb is 50Hz. In the digital implementation, 1 p.u is 3FFFh, or 16383d . So, ∆θpu is expressed in digital domain as follows:
∆θ = 16383d × 5.12 × 10−3 fpu = 84d × fpu (5.4) ∆θ (n) = ∆θ (n − 1) + ∆θ (5.5) where ∆θ (n) is the nth sample and ∆θ (n − 1) is the (n − 1)th sample of θ. The above is realized in the FPGA as shown in Fig. 5.5. The sine values for each θ are stored in ROM. The address for each step in angle is generated as shown in the Fig. 5.5. In the figure, note that the p.u ∆θ, as in Eqn. 5.4, is obtained as a 32-bit number, and it has been scaled down to 16 bit. This is done by dividing ∆θ[31..0] by 3FFFh. This way, it is ensured that ∆θ remains perunitized. The sine values for 1024 samples are stored in a ROM, with 10bit-wide address bus. The address generated as shown in Fig. 5.5 is to be scaled down to 10 bit. Counter10 is the 10th bit of the up-counter, with a period of 102.4µs. The sine values can be generated by a C or MATLAB program. [6], and stored in the ROM configured in FPGA. The sine wave amplitude is chosen as 1 p.u (3FFFh). Fig. 5.6 shows the sine wave. For generating the three-phase waveforms, the respective angles, θy and θb are calculated by subtracting 120o and 240o from the R-phase angle, θr . Digitally, 120o is 5461d and 240o is 10922d , because 360o is represented by 3FFFh. For each phase a sine table may be used. Another way is to have two sine tables for the two phases and use the three-phase balance relation (Vr + Vy + Vb = 0) to get the third sine wave. Keeping V/F ratio constant

Per-unit values of maximum sine value and maximum frequency are the same (3FFFh). Hence, scaling of sine value for a particular reference frequency can be done by simply multiplying the sine values by the reference frequency with proper scaling. Fig. 5.7 shows the entire scheme in block diagram.

74

V/F Control of Induction Motor Drive freq_ref[15..0] 16 ∆ θ [29..14]

∆ θ[31..0]

θ (n)[15..0]

16 84H

θ (n−1)[15..0] Q

θ (n)[15..0]

D Counter10 clk

address_theta[15..0]

16383D

Figure 5.5: Theta Address Generation Scheme 3FFF H 1 pu

0

o

o

360

180

C000 H −1 pu

Figure 5.6: p.u Sine wave addr_theta_R[15..0] counter10

addr_theta_R[15..0]

A−B

addr_theta_Y[15..0]

5461d

ROM clk

sine_val_R[31..0] freq_ref[15..0]

addr_theta_Y[15..0]

A−B

addr_theta_B[15..0]

10922d

counter10

ROM clk

sine_val_Y[31..0] freq_ref[15..0]

addr_theta_B[15..0] counter10

ROM clk

sine_val_B[31..0] freq_ref[15..0]

Figure 5.7: Generation of Three-phase V/F Sine waves 5.4.2

Carrier Generation

The carrier used for Sine-Triangle Modulation is a triangular waveform. In the FPGA, it is generated digitally by using a counter. The triangular carrier,

5.4 Implementation of V/F Sine-Triangle Modulator in FPGA

75

in analog methods is usually a bipolar signal. In digital implementation both the modulating signal and the carrier used are unipolar in nature. Hence the peak of the carrier is kept at 2 p.u. The sine modulating signals are given an offset of 1 p.u, so that they also become unipolar. A binary up-down counter is configured as shown in Fig. 5.8 for generating the required carrier. 1 p.u is set as 3FFH. Since the carrier peak is set at 2 p.u, the maximum count is 7FFH. The p.u value for the amplitude of carrier is chosen based on the switching frequency required. In the FPGA controller board used, the clock frequency is 20MHz. This means for counting up to 7FFH, it takes 102.4µs. The frequency of carrier and hence the switching frequency used here is nearly 5 kHz. The period of the MSB of the 12-bit counter is 204.8µs.

12

Sub

Triangle carrier

MUX

clock

12 Bit Up Counter

12

A−B

2047 D

2048D count[11..0]

count11

Sub

7FFh

count[11..0]

0

count11

1

triangle carrier 0

102.4 µ s

204.8 µ s

Figure 5.8: Carrier Generation Scheme in FPGA

76

V/F Control of Induction Motor Drive

5.4.3

Generation of PWM

The carrier is compared with the three v/f sine waves generated as described in previous sections individually to get the three PWM pulses. Before comparison, the sine waves have to be given an offset of 1 p.u so that they become unipolar. Also, it has to be noted that the generated sine values are 16 bits wide and the triangle carrier is only 12 bits wide. So, the sine values have to be scaled accordingly, by selecting bits [15..4]. Fig. 5.9 shows the generated triangular carrier and the shifted sine wave for one phase. PWM generation for one phase is shown in Fig. 5.10. The remaining signals are generated similarly with the respective sine values. Fig. 5.11 shows the PWM signals for the upper switches in the U and V legs of VSI.

Figure 5.9: Sine Wave and Triangular Carrier sine_val_R[15..4] shifted_sine_R[11..0] 1024d

12 bit Comparator

triangle_carrier[11..0]

Figure 5.10: PWM Generation for U-phase

PWM_R

5.5 Open-loop V/F Control of IM - Real-time Simulation

Figure 5.11: PWM Signals for U and V phases

5.4.4

Slow Start of Induction Motor

To keep the motor currents within safe limits during starting, the speed reference has to be incremented slowly in a ramp fashion. The required ramping time depends on the motor full load slip. The slow-starting scheme is described in Fig. 5.12. Fig. 5.13 shows the slow rise of the frequency reference signal and the corresponding sinusoidal reference produced by the v/f signal generator.

5.5

Open-loop V/F Control of IM - Real-time Simulation

Once the modulators are developed as described in previous sections, performing a real-time simulation of the entire drive is possible if we can model the VSI and the Induction Motor in FPGA. Modelling of Induction Motor is dealt with in Ch. 4. Modelling of a VSI is a straight forward task, if we assume ideal switches. The equations are algebraic in nature, and are directly converted to their digital per-unit equivalent. The pole voltages of the VSI with respect to the DC link negative point

77

78

V/F Control of Induction Motor Drive Counter freq_cmd[15..0]

freq_input[15..0]

clk

Q a=b

en

enable ab

a=b

clk

D

freq_ref[15..0]

MUX

count enable

enable

MUX

a
freq_ref[15..0] freq_cmd[15..0]

a compare b

a=b ab

Figure 5.12: Slow Starting Logic

Figure 5.13: Slow Starting V/F Sine Wave Reference

can be expressed in terms of the switch states and DC link voltage, as:

Vu (t) = VDC .Su Vv (t) = VDC .Sv Vw (t) = VDC .Sw

(5.6)

5.5 Open-loop V/F Control of IM - Real-time Simulation

79

The line voltages are then given by, Vuv (t) = Vu (t) − Vv (t) Vvw (t) = Vv (t) − Vw (t) Vwu (t) = Vw (t) − Vu (t)

(5.7)

The line-neutral voltages at the load are evaluated from the above, as Vu v(t) − Vw u(t) 3 Vv w(t) − Vu v(t) Vvn (t) = 3 Vw u(t) − Vv w(t) Vwn (t) = 3 Vun (t) =

(5.8)

In the digital implementation of the above equations, 3FFFh is assumed as 1 p.u voltage. The implementation of the model in FPGA is shown in Fig. 5.14. Interconnection of different modules of the entire system for real-time simulation is shown in Fig. 5.15.Some of the important results are shown in Figs. 5.16(a) to 5.16(b). VDC

0

Vu MUX

16

16

Su

Vv

Vuv SUB 16

Vuv

Vwu

5431d

16

0

MUX

VDC 16

Vvw

Vv 16

Sv

Vw

Vvw SUB

16

5431d

0

MUX

VDC

Sw

Vuv

Vvn

SUB

16

16

Vun

SUB

Vwu

Vw 16

SUB Vu 16

Vwu 16

Vvw

Vwn

SUB 5431d

Figure 5.14: VSI Model Implementation in FPGA

80

V/F Control of Induction Motor Drive

Clock

Vdc(p.u)

Timing and Control Signals

Su Modulator

(Master Counter/ carrier generation)

freq_command

Slow Start Logic

Sv

Vu Inverter Model

Sw

freq_ref

Vv

Induction Motor Model

Vw

v/f sine waves

Clock

Figure 5.15: Interconnection of Different Modules for v/f Drive.

(a)

Figure 5.16: Real-Time Simulation: (a) Speed Response for Step Commands (b) Output Line and Neutral Voltages of Inverter Model

(b)

Speed

Torque

5.6 Conclusion

5.6

Conclusion

Basic principles of V/F control scheme for Induction Motor are explained. Developing a v/f controller has been described. The modulation used in the controller is on Sine-triangle modulation. Implementation details of modulator and the v/f controller in the FPGA controller board is also discussed. Finally, an entire open-loop v/f drive consisting of a VSI and an Induction motor is simulated in real-time and the results are given. This shows the capability of the FPGA controller board to work as a full-fledged control and real-time simulation platform.

81

82

V/F Control of Induction Motor Drive

Chapter 6

Real-Time Simulation Of Switched Reluctance Motor 6.1

Introduction

The SR motor differs from the conventional motors in many respects. The motor has saliency both in stator and rotor. The excitation is limited to stator only. The torque is developed by the tendency of the magnetic circuit to adopt a configuration of minimum reluctance. The excitation currents are unidirectional and discontinuous in nature. The stator phases are sequentially excited to obtain continuous rotation. So the SR motor cannot be operated with either AC or DC regular power sources. It has to be necessarily operated from a switching power converter.

6.2

Basic Principle of Operation

In SR motor, when a particular phase is excited, the flux in that phase will try to align the nearest rotor pole along the corresponding stator pole axis. The aligned position between the stator and the rotor pole provides minimum reluctance. This reluctance torque mechanism can be explained with the help of the diagram in Fig. 6.1. The figure shows that the rotor pole is lying along the axis OA. For a counter clockwise rotation, this position of the rotor is referred as unaligned position (0◦ ) with respect to Ph1. After 30◦ movement of the rotor in the same direction, the same rotor pole will lie along OB, which is referred as the aligned position (30◦ ) for Ph1. In Fig. 6.1, the rotor is shown in aligned position with respect to Ph3 and in unlaigned position with respect to Ph1, whereas it is at 15◦ position with respect to Ph2. On the account of the saliency in the rotor, the inductance(L) of the exciting coil is a function of rotor position.

84

Real-Time Simulation Of Switched Reluctance Motor

Figure 6.1: Cross-section of and 8/6 pole 4-phase SR Motor Consider the stator winding excited from a source voltage v dψ v = Ri + dt v = sourcevoltage i = coilcurrent R = coilresistance ψ = f luxlinkage L = coilinductance

(6.1)

d(Li) (6.2) dt L is a function of the rotor position. Equation 6.2 canbe decomposed as di dL v = Ri + L + iω (6.3) dt dθ ω = rotorspeed θ = rotorposition v = Ri +

The applied voltage is dropped in three parts, namely resistive drop(iR), inductive drop(Ldi/dt) and speed dependent counter emf (iωdL/dθ). It may be noted that (unlike other standard machines) the counter emf exists only when there is an inductance gradient with respect to position(dL/dθ 6= 0). We may now see the power relatinship, dL di (6.4) vi = Ri2 + iL + i2 ω dt dθ

6.3 Inductance Gradient (L vs θ)

85

The above equation may be now arranged as vi = Ri2 +

d(Li2 /2) + Tg ω dt

(6.5)

dL (6.6) dθ Equation 6.5 gives the power flow in the machine. The input power is made up of resistive loss (i2 R), rate of change of stored energy(d(Li2 /2)/dt), and the converted mechanical power(Tg ω). Equation 6.6 condenses the torque generating mechanism in the machine. Torque generation requires an excitation current in the coil and inductance gradient in the coil. the polarity of the generated torque is the independent of the polarity of the excitation current. The polarity of the generated torque is dependent only on the polarity of the inductance gradient(dL/dθ). Tg = i2 /2

6.3

Inductance Gradient (L vs θ)

Figure 6.2: Idealised Inductance Profile of the Four Different Phases For an 8/6 pole SR motor, the variation in self-inductances of the different phases with respect to rotor position will be as in Fig. 6.2, when the following assumptions are made1. all the phases are identical 2. magnetic saturation and fringing are neglected

86

Real-Time Simulation Of Switched Reluctance Motor

3. pole widths of the stator and the rotor are the same and 4. the stator has a pole width to pitch of 0.5. The inductance of each phase repeats periodically at 60◦ as shown in Fig. 6.2. The phase difference between two consecutive phases is 15◦ . The winding can be excited either in the positive or negative gradient region of the inductance profile. If the magnetic circuit is assumed to have no mutual coupling between phases and the magnetic characteristics is linear, the torque developed in SR motor can be expressed as given by Eqn. 6.6. By causing excitation during the positive or negative slope region of the inductance profile, the machine can be made to develop positive or negative torque. By sequential switching of the phases, the motor can be driven in either direction. In this set-up, the switching sequence for forward rotation (anticlockwise from the shaft end) is Ph1-Ph2-Ph3-Ph4-Ph1. The sequence for the reverse rotation (clockwise) will be Ph4-Ph3-Ph2-Ph1-Ph4. It can be concluded that the motor can be run in either direction and for both the directions of rotation, the torque can be either positive or negative. Therefore, all four quadrant operation is possible using this motor. Each phase is switched on and switched off at least once in every 60◦ . This is called the fundamental switching frequency for the SR motor. During each fundamental switching period all the phases are excited once and the interval between the excitation of two consecutive phases are called the stroke angle. The total number of strokes per revolution (n), stroke angle (qstroke ) and fundamental switching frequency (f1) in one one phase can be expressed as, n = qNr

(6.7)

2π (6.8) qNr r.p.m f1 = Nr (6.9) 60 where, q is number of phases and Nr is the number of rotor poles. For an 8/6 motor, strokes per revolution is 24, stroke angle is 15◦ and fundamental switching frequency for rated speed (1500 rpm) is 150Hz. Since switching of phases are done in accordance with the information of rotor position, a position sensor and a switching power converter are essential for an SR motor drive. θstroke =

6.4

Flux-Linkage Characterstics

When a voltage pulse is applied to one of the phases of SRM, with all other phases open, its voltage equation is given by v = Ri +

dψ dt

(6.10)

6.5 Torque Characterstics

87

Figure 6.3: Flux-linkage Characterstics where v is the instantaneous voltage across the phase winding; R is its resistance and i the current. The flux-linkage ψ is, Z ψ = (v − Ri)dt (6.11) The flux-linkage, can be computed for different values of current with the help of Eqn. 6.11. Flux-linkage is measured for a set of rotor positions spanning from 0◦ to 30◦ at the step of 1◦ . Since the inductance profile is symmetric with respect to the aligned position of a particular phase the flux-linkage characteristics of a phase will also be symmetric with respect to the aligned position (30◦ ). Flux-linkage characteristics of a 4 kW, 8/6 pole SRM are given in Fig. 6.3. The static flux-linkage characteristics can be approximated by the following mathematical expression. i = K1 (θ)ψ + (ψ > ψ1 )K2 (θ)(ψ − ψ1 )2 + (ψ > ψ2 )K3 (θ)(ψ − ψ2 )3

(6.12)

where ψ1 ,ψ2 are constants; K1 (θ),K2 (θ), K3 (θ) are functions of position. The above parameters K1 (θ),K2 (θ), K3 (θ) are stored in a look-up table for every 2◦ . Linear interpolation can be used for intermediate values. The said values are given in tabular form in Table 6.1.

6.5

Torque Characterstics

Once, the value of current and position of a particular phase is known by 6.12, the instantaneous torque due to that particular phase can be found using the stored static torque data, T = f (ij , θj ), given by table 6.2 and 6.3. In the similiar process, the torque due to other conducting phases also may be found.

88

Real-Time Simulation Of Switched Reluctance Motor

Table 6.1: Position(θ) K1

K2

K3

ψ1

ψ2

0

◦

68

0

0

0.2

0.45

2

◦

66.75

0

0

0.2

0.45

4

◦

65

0

0

0.2

0.45

6

◦

60

0

0

0.2

0.45

8

◦

52.5

0

0

0.2

0.45

10

◦

42

20

0

0.2

0.45

12

◦

29

48

0

0.2

0.45

14◦

22

40

200

0.2

0.45

16◦

17.5

25

400

0.2

0.45

18◦

14.5

13.5

300

0.2

0.45

20◦

13

5.5

200

0.2

0.45

22◦

12

1.5

150

0.2

0.45

24

◦

11

0

125

0.2

0.45

26

◦

10

0

110

0.2

0.45

28

◦

8.9

0

105

0.2

0.45

30

◦

8.5

0

110

0.2

0.45

40

30

20

10

0

−10

−20

−30

−40

0

10

20

30

40

50

60

Figure 6.4: Torque Characterstics The summation of all the phase torques at any instant gives the instantaneous torque of the motor. Torque characteristics of a 4 kW, 8/6 pole SRM are given in Fig. 6.4.

6.5 Torque Characterstics

89

Table 6.2: Torque Current(A)

0

1

2

3

4

5

6

7

8

9

10

0◦

0.00000

0.00000

0.00000

0.00000

0.00000

0.00000

0.00000

0.00000

0.00000

0.00000

0.00000

2◦

0.00000

0.00361

0.01787

0.02812

0.01801

0.00308

0.00343

0.00334

0.00264

0.00551

0.01451

4◦

0.00000

0.00690

0.02246

0.07362

0.13850

0.21330

0.32130

0.44540

0.58860

0.75030

0.91850

6◦

0.00000

0.01330

0.05761

0.10840

0.18600

0.30410

0.45740

0.64440

0.85890

1.11600

1.40700

8◦

0.00000

0.01440

0.07226

0.22610

0.47110

0.76540

1.12700

1.56500

2.08500

2.69000

3.37200

10◦

0.00000

0.09736

0.38110

0.86270

1.54300

2.44900

3.54700

4.80800

6.21700

7.71200

9.30100

12◦

0.00000

0.12260

0.52270

1.25100

2.29300

3.63800

5.25500

7.07300

9.03400

11.08000

13.16000

14◦

0.00000

0.12260

0.52820

1.27800

2.36600

3.76800

5.45400

7.34900

9.39800

11.54000

13.73000

◦

0.00000

0.05792

0.35600

1.00000

1.98800

3.30900

4.91900

6.74300

8.73200

10.83000

13.00000

18◦

0.00000

0.10010

0.45060

1.14900

2.19300

3.55200

5.19600

7.04500

9.03000

11.12000

13.27000

20◦

0.00000

0.08709

0.41210

1.06600

2.05100

3.33600

4.88100

6.61900

8.48800

10.44000

12.45000

22◦

0.00000

0.01385

0.23870

0.78180

1.62600

2.75200

4.10200

5.61500

7.23700

8.89900

10.56000

24◦

0.00000

0.08618

0.40740

1.04100

1.96400

3.10000

4.41000

5.82000

7.23100

8.57900

9.86000

26◦

0.00000

0.11910

0.46780

1.11000

1.99300

3.04100

4.21900

5.39400

6.47300

7.43500

8.32800

28◦

0.00000

0.10940

0.46230

1.10500

1.92900

2.90800

3.98900

4.99200

5.87000

6.62500

7.32000

30◦

0.00000

0.03928

0.22000

0.52070

0.93840

1.45200

1.93000

2.29700

2.58000

2.84500

3.09300

32◦

0.00000

-0.03928

-0.22000

-0.52070

-0.93840

-1.45200

-1.93000

-2.29700

-2.58000

-2.84500

-3.09300

34◦

0.00000

-0.10940

-0.46230

-1.10500

-1.92900

-2.90800

-3.98900

-4.99200

-5.87000

-6.62500

-7.32000

36◦

0.00000

-0.11910

-0.46780

-1.11000

-1.99300

-3.04100

-4.21900

-5.39400

-6.47300

-7.43500

-8.32800

◦

0.00000

-0.08618

-0.40740

-1.04100

-1.96400

-3.10000

-4.41000

-5.82000

-7.23100

-8.57900

-9.86000

40◦

0.00000

-0.01385

-0.23870

-0.78180

-1.62600

-2.75200

-4.10200

-5.61500

-7.23700

-8.89900

-10.56000

42◦

0.00000

-0.08709

-0.41210

-1.06600

-2.05100

-3.33600

-4.88100

-6.61900

-8.48800

-10.44000

-12.45000

44◦

0.00000

-0.10010

-0.45060

-1.14900

-2.19300

-3.55200

-5.19600

-7.04500

-9.03000

-11.12000

-13.27000

46◦

0.00000

-0.05792

-0.35600

-1.00000

-1.98800

-3.30900

-4.91900

-6.74300

-8.73200

-10.83000

-13.00000

48◦

0.00000

-0.12260

-0.52820

-1.27800

-2.36600

-3.76800

-5.45400

-7.34900

-9.39800

-11.54000

-13.73000

50◦

0.00000

-0.12260

-0.52270

-1.25100

-2.29300

-3.63800

-5.25500

-7.07300

-9.03400

-11.08000

-13.16000

52◦

0.00000

-0.09736

-0.38110

-0.86270

-1.54300

-2.44900

-3.54700

-4.80800

-6.21700

-7.71200

-9.30100

54◦

0.00000

-0.01440

-0.07226

-0.22610

-0.47110

-0.76540

-1.12700

-1.56500

-2.08500

-2.69000

-3.37200

56◦

0.00000

-0.01330

-0.05761

-0.10840

-0.18600

-0.30410

-0.45740

-0.64440

-0.85890

-1.11600

-1.40700

58◦

0.00000

-0.00690

-0.02246

-0.07362

-0.13850

-0.21330

-0.32130

-0.44540

-0.58860

-0.75030

-0.91850

◦

0.00000

-0.00361

-0.01787

-0.02812

-0.01801

-0.00308

-0.00343

-0.00334

-0.00264

-0.00551

-0.01451

60◦

0.00000

0.00000

0.00000

0.00000

0.00000

0.00000

0.00000

0.00000

0.00000

0.00000

0.00000

theta

16

38

59

90

Real-Time Simulation Of Switched Reluctance Motor

Table 6.3: Torque (contd..) Current(A)

11

12

13

14

15

16

17

18

19

20

0◦

0.00000

0.00000

0.00000

0.00000

0.00000

0.00000

0.00000

0.00000

0.00000

0.00000

2◦

0.04549

0.07810

0.11400

0.15260

0.19630

0.24820

0.30800

0.37420

0.44840

0.53060

4◦

1.10100

1.30600

1.51800

1.74800

1.99300

2.25600

2.54800

2.85800

3.16100

3.43300

6◦

1.72900

2.07600

2.45900

2.88200

3.34300

3.83600

4.35400

4.92100

5.56800

6.32600

8◦

4.12800

4.96300

5.87600

6.85000

7.89400

9.00800

10.19000

11.45000

12.71000

13.94000

10◦

10.97000

12.70000

14.49000

16.33000

18.21000

20.14000

22.10000

24.11000

26.21000

28.46000

◦

15.25000

17.37000

19.50000

21.67000

23.86000

26.05000

28.25000

30.46000

32.64000

34.77000

14◦

15.93000

18.15000

20.36000

22.57000

24.76000

26.94000

29.12000

31.30000

33.48000

35.66000

16◦

15.21000

17.41000

19.60000

21.77000

23.89000

25.99000

28.04000

30.05000

31.98000

33.82000

18◦

15.45000

17.64000

19.81000

21.94000

24.03000

26.07000

28.04000

29.92000

31.70000

33.35000

20◦

14.47000

16.49000

18.48000

20.42000

22.30000

24.13000

25.90000

27.58000

29.21000

30.79000

22◦

12.22000

13.85000

15.46000

17.04000

18.58000

20.08000

21.53000

22.93000

24.27000

25.59000

24◦

11.11000

12.33000

13.54000

14.74000

15.94000

17.11000

18.26000

19.39000

20.47000

21.52000

26◦

9.18100

10.01000

10.82000

11.63000

12.44000

13.24000

14.03000

14.82000

15.57000

16.28000

28◦

7.98000

8.61700

9.24100

9.85000

10.45000

11.04000

11.64000

12.23000

12.80000

13.33000

30◦

3.30800

3.50600

3.69900

3.87800

4.03400

4.18800

4.34200

4.49500

4.68300

4.95200

32◦

-3.30800

-3.50600

-3.69900

-3.87800

-4.03400

-4.18800

-4.34200

-4.49500

-4.68300

-4.95200

34◦

-7.98000

-8.61700

-9.24100

-9.85000

-10.45000

-11.04000

-11.64000

-12.23000

-12.80000

-13.33000

36◦

-9.18100

-10.01000

-10.82000

-11.63000

-12.44000

-13.24000

-14.03000

-14.82000

-15.57000

-16.28000

38◦

-11.11000

-12.33000

-13.54000

-14.74000

-15.94000

-17.11000

-18.26000

-19.39000

-20.47000

-21.52000

40◦

-12.22000

-13.85000

-15.46000

-17.04000

-18.58000

-20.08000

-21.53000

-22.93000

-24.27000

-25.59000

42◦

-14.47000

-16.49000

-18.48000

-20.42000

-22.30000

-24.13000

-25.90000

-27.58000

-29.21000

-30.79000

44◦

-15.45000

-17.64000

-19.81000

-21.94000

-24.03000

-26.07000

-28.04000

-29.92000

-31.70000

-33.35000

46◦

-15.21000

-17.41000

-19.60000

-21.77000

-23.89000

-25.99000

-28.04000

-30.05000

-31.98000

-33.82000

48◦

-15.93000

-18.15000

-20.36000

-22.57000

-24.76000

-26.94000

-29.12000

-31.30000

-33.48000

-35.66000

50◦

-15.25000

-17.37000

-19.50000

-21.67000

-23.86000

-26.05000

-28.25000

-30.46000

-32.64000

-34.77000

52◦

-10.97000

-12.70000

-14.49000

-16.33000

-18.21000

-20.14000

-22.10000

-24.11000

-26.21000

-28.46000

54◦

-4.12800

-4.96300

-5.87600

-6.85000

-7.89400

-9.00800

-10.19000

-11.45000

-12.71000

-13.94000

56◦

-1.72900

-2.07600

-2.45900

-2.88200

-3.34300

-3.83600

-4.35400

-4.92100

-5.56800

-6.32600

◦

-1.10100

-1.30600

-1.51800

-1.74800

-1.99300

-2.25600

-2.54800

-2.85800

-3.16100

-3.43300

59◦

-0.04549

-0.07810

-0.11400

-0.15260

-0.19630

-0.24820

-0.30800

-0.37420

-0.44840

-0.53060

60◦

0.00000

0.00000

0.00000

0.00000

0.00000

0.00000

0.00000

0.00000

0.00000

0.00000

theta

12

58

6.6 Position Sensor

6.6

Position Sensor

Figure 6.5: (a) Inductance Profiles of the Four Stator Phases

Figure 6.5: (b) Position Signals for Forward Rotation

Figure 6.5: (c) Position Signals for Reverse Rotation For an SR motor drive, switching on and switching off the phases are synchronised with the rotor position. The test motor is provided with four discrete sensors. The position signals made available from the position sensors. In real-time simulation, these position signals are generated continuously in

91

92

Real-Time Simulation Of Switched Reluctance Motor

the simulation itself and are given in Fig. 6.5. In this figure, the idealised inductance profiles of the four phases are also given.

6.7

Control Strategy

The traditional control method employs two regimes of control namely low speed chopping control, and high speed angle control. This angle control mode has been referred to as single pulse mode by many authors. For an 8/6 pole SR motor, each phase gets excited periodically at 60◦ interval. The phase difference between successive phases will be 15◦ each. The control is defined in all the four quadrants of operation of the motor. These are 1. FSFT: Forward Speed Forward Torque 2. FSRT: Forward Speed Reverse Torque 3. RSFT: Reverse Speed Forward Torque 4. RSRT: Reverse Speed Reverse Torque Again, in each quadrant, the control is divided in three speed ranges namely, 1. Starting speed((Less than 100 rpm in either direction) 2. Medium speed (Between 100 and 750 rpm in either direction) 3. High speed (Above 750 rpm in either direction). Table 6.4 gives the digital raw enabling signals (produced from P, Q, R, S) for each phase under different operating conditions stated above. It may be verified from the position signals that the right polarity of torque will be generated if the different phases are excited in the enabling periods given in Table 6.4. The raw enable signals are further mixed with other appropreiate signals for driving the switches in the four phases of the machine. These are explained in the following sections.

Phase

Starting Speed

Low Speed

High Speed

Forward

Reverse

Forward

Reverse

Forward

Reverse

A

P

P

PS

PR

S

R

B

Q

Q

QR

QS

R

S

C

P

P

PS

PR

S

R

D

Q

Q

QR

QS

R

S

Table 6.4: Switch Control Signals

6.7 Control Strategy

93

Starting Speed Current Controlled Operation: In the starting speed ranges, the individual phases are turned on/off in the raw enable duration and phase current is maintained at the desired current, I ∗ by chopping control. I ∗ is made a function of the desired torque. The control strategy is illustrated in Fig. 6.6. In the starting operation (or very low speed of operation), the raw enable signal is ended with the logic signal (I ≤ I ∗ ). The switch control signal for the different phases are given below. SA = P (I ≤ I ∗ )(T SB = Q(I ≤ I ∗ )(T SC = P (I ≤ I ∗ )(T SD = Q(I ≤ I ∗ )(T

> 0) + P (I ≤ I ∗ )(T > 0) + Q(I ≤ I ∗ )(T > 0) + P (I ≤ I ∗ )(T > 0) + Q(I ≤ I ∗ )(T

< 0) < 0) < 0) < 0)

Low Speed Current Controlled Operation: In the low speed of operation ( speed upto 750 rpm), current control is used. The switch enable signals are given by the equations below. In both the starting region of operation and low speed of operation the phase current feedback is also required to implement the switch control. SA = P S(I ≤ I ∗ )(T > 0) + P R(I ≤ I ∗ )(T SB = QR(I ≤ I ∗ )(T > 0) + QS(I ≤ I ∗ )(T SC = P S(I ≤ I ∗ )(T > 0) + P R(I ≤ I ∗ )(T SD = QR(I ≤ I ∗ )(T > 0) + QS(I ≤ I ∗ )(T

< 0) < 0) < 0) < 0)

High Speed Single Pulsed operation: In the high speed range, back-emf is considerable and it exceeds the supply voltage. Phase currents no longer can be controlled by chopping method. The individual phases are controlled with two parameters defined as T-on and T-off. These turn-on time, T-on and turn-off time, T-off are illustrated in Fig. 6.7. The raw enable signal for this mode (shown in Table 6.4) is mixed with a controlled T-on and controlled Toff angles. Hence control of torque in this region is realised by controlling the dwell angle. Normally the T-on angle is defined as a function of shaft speed and demanded torque, whereas T-off angle is defined as a function of speed only. At any particular speed, the desired average torque may be obtained by more than one combination of these angles. Among these, the combinations which give minimum torque ripple and minimum peak current are desired. Generally, exhaustive search method is employed in simulation to calculate the optimum value of these parameters. These are stored in a look up table as a function of load torque and speed and referred by the controller as desired. The angle θ1 is a function of shaft speed as well as the desired torque. The angle θ2 is a function of the shaft speed. The per unit shaft speed may vary in the range of 0.5 to 1 in either direction. The desired per unit torque may vary in the range of -1 to +1. For the controller the values of θ1 and θ2 are stored in a look-up Table 6.5, 6.6 and referred to as desired.

94

Table 6.5: θ1 Torque

-1.00

-0.90

-0.80

-0.70

-0.60

-0.50

-0.40

-0.30

-0.20

-0.10

0.00

0.10

0.20

0.30

0.40

0.50

0.60

0.70

0.80

0.90

1.00

Speed -1.00

55.4

54.7

53.85

53.05

52.1

51

49.85

48.5

46.6

44

41

38.9

41.5

43.2

44.7

45.7

46.7

47.6

48.5

49.1

49.8

-0.90

53.65

53.05

52.3

51.5

50.7

49.8

48.75

47.5

45.9

43.5

40.5

38.4

40.8

42.4

43.6

44.6

45.5

46.3

47

47.8

48.4

51.8

51.3

50.7

50.05

49.3

48.5

47.55

46.5

45

42.7

40

38

40

41.5

42.6

43.55

44.4

45.1

45.7

46.35

46.9

-0.70

50.05

49.6

49.1

48.5

47.9

47.2

46.4

45.4

44.05

42

39.5

37.6

39.5

40.9

41.9

42.7

43.5

44.05

44.55

45

45.6

-0.60

48.25

47.9

47.45

47

46.45

45.8

45.1

44.25

43.1

41.25

39

37.2

39

40.1

41

41.7

42.3

42.85

43.3

43.8

44.2

-0.51

46.4

46.05

45.7

45.3

44.9

44.4

43.8

43

42

40.4

38

36.5

38.2

39.2

39.9

40.4

40.9

41.4

41.9

42.2

42.5

0.51

17.5

17.8

18.1

18.6

19.1

19.6

20.1

20.8

21.8

23.5

21.5

19.6

18

17

16.2

15.6

15.1

14.7

14.3

13.95

13.6

0.60

15.8

16.2

16.7

17.15

17.7

18.3

19

19.9

21

22.8

20.8

18.85

16.9

15.75

14.9

14.2

13.55

13

12.55

12.1

11.75

0.70

14.4

15

15.45

15.95

16.5

17.3

18.1

19.1

20.5

22.4

20.2

18

15.95

14.6

13.6

12.8

12.1

11.5

10.9

10.4

9.95

0.80

13.1

13.65

14.3

14.9

15.6

16.45

17.4

18.5

20

22

19.6

17.3

15

13.5

12.45

11.5

10.7

9.95

9.3

8.7

8.2

0.90

11.6

12.2

13

13.7

14.5

15.4

16.4

17.6

19.2

21.6

19

16.5

14.1

12.5

11.25

10.2

9.3

8.5

7.7

6.95

6.35

1.00

10.2

10.9

11.5

12.4

13.3

14.3

15.3

16.8

18.5

21.1

18.5

16

13.4

11.5

10.15

9

7.9

6.95

6.15

5.3

4.7

Torque

-1.00

-0.90

-0.80

-0.70

-0.60

-0.50

-0.40

-0.30

-0.20

-0.10

0.00

0.10

0.20

0.30

0.40

0.50

0.60

0.70

0.80

0.90

1.00

-1.00

30

30

30

30

30

30

30

30

30

30

41

26.9

26.9

26.9

26.9

26.9

26.9

26.9

26.9

26.9

26.9

-0.90

30.50

30.50

30.50

30.50

30.50

30.50

30.50

30.50

30.50

30.50

40.50

27.00

27.00

27.00

27.00

27.00

27.00

27.00

27.00

27.00

27.00

-0.80

30.80

30.80

30.80

30.80

30.80

30.80

30.80

30.80

30.80

30.80

40.00

27.20

27.20

27.20

27.20

27.20

27.20

27.20

27.20

27.20

27.20

-0.70

31.20

31.20

31.20

31.20

31.20

31.20

31.20

31.20

31.20

31.20

39.50

27.50

27.50

27.50

27.50

27.50

27.50

27.50

27.50

27.50

27.50

-0.60

31.50

31.50

31.50

31.50

31.50

31.50

31.50

31.50

31.50

31.50

39.00

27.80

27.80

27.80

27.80

27.80

27.80

27.80

27.80

27.80

27.80

-0.51

31.80

31.80

31.80

31.80

31.80

31.80

31.80

31.80

31.80

31.80

38.00

28.00

28.00

28.00

28.00

28.00

28.00

28.00

28.00

28.00

28.00

0.51

32.00

32.00

32.00

32.00

32.00

32.00

32.00

32.00

32.00

32.00

21.50

28.20

28.20

28.20

28.20

28.20

28.20

28.20

28.20

28.20

28.20

0.60

32.20

32.20

32.20

32.20

32.20

32.20

32.20

32.20

32.20

32.20

20.80

28.50

28.50

28.50

28.50

28.50

28.50

28.50

28.50

28.50

28.50

0.70

32.50

32.50

32.50

32.50

32.50

32.50

32.50

32.50

32.50

32.50

20.20

28.80

28.80

28.80

28.80

28.80

28.80

28.80

28.80

28.80

28.80

0.80

32.80

32.80

32.80

32.80

32.80

32.80

32.80

32.80

32.80

32.80

19.60

29.20

29.20

29.20

29.20

29.20

29.20

29.20

29.20

29.20

29.20

0.90

33.00

33.00

33.00

33.00

33.00

33.00

33.00

33.00

33.00

33.00

19.00

29.50

29.50

29.50

29.50

29.50

29.50

29.50

29.50

29.50

29.50

1.00

33.10

33.10

33.10

33.10

33.10

33.10

33.10

33.10

33.10

33.10

18.50

30.00

30.00

30.00

30.00

30.00

30.00

30.00

30.00

30.00

30.00

Table 6.6: θ2 Speed

Real-Time Simulation Of Switched Reluctance Motor

-0.80

6.8 Implementation

Figure 6.6: Low Speed Control Strategy

Figure 6.7: Control Strategy at High Speed

6.8

Implementation

A. Parameters : The details of the switched reluctance motor is presented in Table. 6.7. B. Base Values for Different Quantities : The Table. 6.8 shows the base values for voltage (chosen as per phase rated voltage of SR Motor), current (chosen rated current) and frequency (chosen as rated frequency). The other bases are calculated from the above mentioned base quantities. C. PU System Followed : The Table 6.9 shows the digital equivalent for the pu values. The signed arithmetic, the digital equivalent for a negative pu value is chosen as the 1’s compliment of its corresponding positive pu value.

95

96

Real-Time Simulation Of Switched Reluctance Motor

VOLTAGE

280 V

CURRENT

18 A

POWER

4kW

POLES (P) SPEED

8/6 1500 rpm

Resistance

O.2Ω

Table 6.7: Details of the Switched Reluctance Motor

Voltage (Vb )

280V

Current (Ib )

18A

Speed (Nb )

1500rpm

Frequency in rad/sec (ωb )

2π ∗

Nb 60

∗ Nr = 942.48rad/sec Vb Ib

Resistance(Rb ) Mechanical Speed(ωmb )

2π ∗

Nb 60

= 15.556Ω

= 157.08rad/sec Vb ωmb

Flux Linkages(ψb )

= 0.29771

Vb ∗Ib ωmb

= 32.086N − m

K1(b)

Ib ψb

= 32.086N − m

K2(b)

Ib ψb2

= 32.086N − m

K3(b)

Ib ψb3

= 32.086N − m

Torque(Mb )

Table 6.8: Base Values

pu value

Equivalent digital Value

Equivalent decimal value

1 pu

3F F FH

16383d

0 pu

000H

0d

C000H

49152d

-1 pu(16-bit)

Table 6.9: PU Values

6.9 Normalized Equations

6.9

97

Normalized Equations

In this section, all the equations are perunitized and are made ready for implementation. The sampling time for the implementation is chosen as 25.6 µsec. The eqn. 6.1 is repeated here. v = Ri +

dψ dt

(6.13)

Dividing the above equation by Vb v(pu) = R(pu) i(pu) +

ψb dψ(pu) Vb dt

(6.14)

Using the Eulers Method of integration, the equation in digital domain can be written as
ψ (n) = ψ (n − 1) + v (n − 1) − R(pu) i (n − 1) Ts ωb

Note that, the sampling time Ts for the implementation is chosen as 25.6 µsec.
ψ (n) = ψ (n − 1) + v (n − 1) − 0.0129(pu) i (n − 1) ∗ 0.004pu (6.15) The flux linkage charcteristic equation is given by 6.12 and the corresponding normalized equation is as follows: i (n) = K1(pu) ψ (n) + (ψ (n) > ψ1(pu) ) K2(pu) (ψ (n) − ψ1(pu) )2 + (ψ (n) > ψ2(pu) ) K3(pu) (ψ (n) − ψ2(pu) )3

(6.16)

Once, the value of current and position of a particular phase is known, the instantaneous torque due to that particular phase can be found using the stored static torque data table 6.2, 6.3. In the similiar process, the torque due to other conducting phases also may be found. the summation of all the phase torques at any instant gives the instantaneous torque of the motor.

6.10

FPGA Design Files

FPGA Design files of Switched Reluctance Motor are placed in ‘fpga program files’ folder. Similarly simulink files are in ‘simulinkprogramfiles’ folder. Fig. 6.8 to Fig. 6.12 are the FPGA design files to generate enable signals explained in section 6.7.

6.11

Waveforms

The program developed for switched reluctance motor in Quartus II tool are downloaded into FPGA by using Byte-blaster cable. The waveforms are recorded and are compared with the off-line simulation waveforms.

98

Real-Time Simulation Of Switched Reluctance Motor

Figure 6.8: FPGA Design File for Speed to Position Conversion

6.11 Waveforms

Figure 6.9: FPGA Design File for Sector Selection

99

100

Real-Time Simulation Of Switched Reluctance Motor

Figure 6.10: FPGA Design File for Generation of Position Signals

6.11 Waveforms

Figure 6.11: (a) FPGA Design File for Generation of Enable Signals

101

102

Real-Time Simulation Of Switched Reluctance Motor

Figure 6.12: (b) FPGA Design File for Generation of Enable Signals

6.11 Waveforms

103

1.5

Enable signal

1 0.5 0 0.74

0.742

0.744

0.746

0.748

0.75

0.752

0.754

0.756

0.758

0.76

0.742

0.744

0.746

0.748

0.75

0.752

0.754

0.756

0.758

0.76

0.742

0.744

0.746

0.748

0.75

0.752

0.754

0.756

0.758

0.76

1.5

Amp

1 0.5 0 0.74 1.5

Nm

1 0.5 0 0.74

time

Figure 6.13: (i) Enable Signal, (ii) Phase Current, (iii) Average Torque [Scale: y-axis: 1 per unit = 5V , ωref = 1500 rpm (1 PU) and Mref = 32.1Nm (1 PU)] 1.5

Enable signal

1 0.5 0 1.065

1.07

1.075

1.08

1.085

1.09

1.095

1.1

1.105

1.07

1.075

1.08

1.085

1.09

1.095

1.1

1.105

1.07

1.075

1.08

1.085

1.09

1.095

1.1

1.5

Amp

1 0.5 0 1.065 1.5

Nm

1 0.5 0 1.065

1.105

time

Figure 6.14: (i) Enable Signal, (ii) Phase Current, (iii) Average Torque [Scale: y-axis: 1 per unit = 5V , ωref = 600 rpm (0.4 PU) and Mref = 32.1Nm (1 PU)] 1.5

Enable signal

1 0.5 0 1.65

1.7

1.75

1.7

1.75

1.7

1.75

1.5

Amp

1 0.5 0 1.65 1.5

Nm

1 0.5 0 1.65

time

Figure 6.15: (i) Enable Signal, (ii) Phase Current, (iii) Average Torque [Scale: y-axis: 1 per unit = 5V , ωref = 90 rpm (0.06 PU) and Mref = 32.1Nm (1 PU)]

104

Real-Time Simulation Of Switched Reluctance Motor

Enable signal

1.5 1 0.5 0 0.645

0.65

0.655

0.66

0.665

0.67

0.65

0.655

0.66

0.665

0.67

0.65

0.655

0.66

0.665

1.5

Amp

1 0.5 0 0.645 1.5

Nm

1 0.5 0 0.645

0.67

time

Figure 6.16: (i) Enable Signal, (ii) Phase Current, (iii) Average Torque [Scale: y-axis: 1 per unit = 5V , ωref = -1500 rpm (-1 PU) and Mref = 32.1Nm (1 PU)] 1.5

Enable signal

1 0.5 0 0.88

0.882

0.884

0.886

0.888

0.89

0.892

0.894

0.896

0.898

0.9

0.882

0.884

0.886

0.888

0.89

0.892

0.894

0.896

0.898

0.9

0.882

0.884

0.886

0.888

0.89

0.892

0.894

0.896

0.898

0.9

1.5

Amp

1 0.5 0 0.88 0

Nm

−0.5 −1 −1.5 0.88

time

Figure 6.17: (i) Enable Signal, (ii) Phase Current, (iii) Average Torque [Scale: y-axis: 1 per unit = 5V , ωref = -1500 rpm (-1 PU) and Mref = -32.1Nm (-1 PU)] 1.5

Enable signal

1 0.5 0 1.395

1.4

1.405

1.41

1.415

1.4

1.405

1.41

1.415

1.4

1.405

1.41

1.5

Amp

1 0.5 0 1.395 0

Nm

−0.5 −1 −1.5 1.395

1.415

time

Figure 6.18: (i) Enable Signal, (ii) Phase Current, (iii) Average Torque [Scale: y-axis: 1 per unit = 5V , ωref = 1500 rpm (1 PU) and Mref = -32.1Nm (-1 PU)]

6.11 Waveforms

105

1.5

Enable signal

1 0.5 0 1.845

1.85

1.855

1.86

1.865

1.85

1.855

1.86

1.865

1.85

1.855

1.86

0.8

Amp

0.6 0.4 0.2 0 1.845 0.8

Nm

0.6 0.4 0.2 0 1.845

1.865

time

Figure 6.19: (i) Enable Signal, (ii) Phase Current, (iii) Average Torque [Scale: y-axis: 1 per unit = 5V , ωref = 1500 rpm (1 PU) and Mref = 16Nm (0.5 PU)]

106

Real-Time Simulation Of Switched Reluctance Motor

6.12

Conclusion

The principle of switched reluctance motor has been explained. It was implemented in FPGA based controller. Both Real-time and offline simulation results are presented.

Chapter 7

Control and Real-Time Simulation of Matrix Converters 7.1

Introduction

Matrix Converters are direct AC-AC power converters without a DC link capacitor. Matrix Converters are now receiving considerable research attention due to a number of advantageous features. In a Matrix Converter, output voltages of desired frequency and amplitude (subjected to certain constraints) are directly synthesized from the input voltages. Matrix Converters can be designed to be more compact than the conventional AC-AC converters. In this chapter the implementation of modulators for Matrix Converters is discussed. The converters are also modelled in the FPGA and a real-time simulation of the same is given. Results are given for the direct on-line starting of an Induction Motor fed from the Matrix Converter. The FPGA platform is capable of implementing complex converter controls. It is possible to simulate the entire drive system consisting of controller, converter and the machine in real-time.

7.2

Basic Principle of Operation

The Matrix Converter is realized by a matrix arrangement of four-quadrant (bidirectional voltage-blocking, current-conducting) switches. Fig. 7.1 shows the topology of a three-phase to three-phase Matrix Converter. Each input phase is connected to all the output phases by bidirectional switches. Any input phase can be connected to any output phase, by turning on the corresponding switch. The basic principle of the Matrix Converter is that by properly switching the devices a desired set of output voltages can be synthesized from the set of input voltages. However there are certain constraints in the power conversion. The input is typically a voltage source and the output is normally connected to an inductive load. Simultaneous closing of more than

108

Control and Real-Time Simulation of Matrix Converters

A

B

SAv

SAw

SBu

SBu

SBw

SCu

SCv

SCw

SAu




C

u

v

w

Figure 7.1: Matrix Converter Topology one switch connected to any output phase (u,v or w) will short circuit the respective input phases. Also, if at-least one switch connected to each output phase is not ON, the current path will be broken. This will cause overvoltages to appear across the devices. The basic constraints for a three-phase to three-phase Matrix Converter can be stated as follows: SAu + SBu + SCu = 1 SAv + SBv + SCv = 1 SAw + SBw + SCw = 1

(7.1) (7.2) (7.3)

where, Sij = 1 or 0, representing the state of switch connecting the input phase i to output phase j. Due to the switching delays in the devices, commutation schemes are needed to avoid the violation of these constraints. Four-quadrant switches can be made with anti-series or anti-parallel connection of IGBTs or MOSFETs.

7.3 Direct and Indirect Matrix Converters

7.3

109

Direct and Indirect Matrix Converters

Matrix Converters are realized in two basic topologies. The classical Matrix Converter is known as Direct Matrix Converter, due to the direct AC-AC conversion without any explicit DC link. However there is an alternate topology in which the Matrix Converter is realized as a cascade connection of two converters. This topology is known as Indirect Matrix Converter. Both are functionally the same. 7.3.1

Direct Matrix Conversion

The converter principle can be explained with a 3-phase to 3-phase converter example. This clearly shows the switching constraints. There are 9 bidirectional switches which connect the input phases {a,b,c} to the output phases {u,v,w}. The switch states can be represented as, Sij = 1 or 0 where, i = {a, b, c} & j = {u, v, w} For example, when switch Sav is ON, input phase a is connected to output phase v. The instantaneous output voltages depend on the states of the switches. Hence the output voltages can be expressed in terms of the input voltages and the switch states as follows:       vu (t)   Sau Sbu Scu   va (t)            (7.4)  vv (t)  =  Sav Sbv Scv   vb (t)            vw (t) Saw Sbw Scw vc (t) For obtaining a desired low frequency averaged waveform, the switches are modulated at a switching frequency much higher than both the input and output frequencies. The averaged output voltages can then be represented in terms of the individual switch duty ratios instead of the switch states in Eqn. 7.4. The output voltages are represented as follows:       vu (t)   dau dbu dcu   va (t)            (7.5) =  vv (t)   dav dbv dcv   vb (t)            vc (t) daw dbw dcw vw (t) Or, v uvw = M (t) × vabc

(7.6)

where, M (t) is the modulation (duty ratio) matrix in Eqn. 7.5 The duty ratios are determined based on the desired amplitude and frequency of the output voltages. There are several modulation methods to

110

Control and Real-Time Simulation of Matrix Converters

achieve this. Modulation of the converter is described in section 7.4. The input currents are related to the output currents by the transpose relation given as; iabc = M T (t) × iuvw (7.7) 7.3.2

Indirect Matrix Conversion

In the Indirect Matrix Converter, the AC-AC conversion is done in two stages. The input converter is a current source type rectifier. This converter uses bidirectional switches as in the case of Direct Matrix Converter. The switchcount can be reduced if regeneration is not needed. A number of new topologies in this direction have been reported. The output converter is a voltage source inverter. Here the switches used are IGBTs with anti-parallel diodes. The DC link does not have a capacitor. The control can be separated between the two converters. The modulation of the Converters is done in an independent manner. Fig. 7.2 shows the topology. The conversion involves two stages. In vpn

idc 

p a

1

3







Su

5

u



n 

b

v 

c

Sv

Su

dc

Sw

Sv 

4

v

2

6





w

Sw

n



 



vnn

Figure 7.2: Indirect Matrix Converter Topology the first stage, the input converter is modulated to get a dc link voltage. In the second stage, the output converter is modulated to get the AC output from the dc link voltage. Both the modulations are independently done. There is an explicit DC link present in this topology. All modulation schemes applicable to VSI can be used here. Input converter is the dual topology of VSI. The DC link voltage produced by the input converter can be expressed as: VDC (t) = vpn (t) − vnn (t)

(7.8)

where vpn (t) and vnn (t) are the upper and lower pole voltages with respect to the supply neutral. The pole voltages can be represented in terms of the input

7.3 Direct and Indirect Matrix Converters

111

voltages in a compact form as follows. 





 S1 S3  vpn (t)   =      S4 S6 vnn (t)







 va (t)   S5      v (t) b     S2  vc (t)

(7.9)

The above expression gives the instantaneous voltages as the switch states change. The currents can also be represented in a similar manner. The output voltages are obtained by the switching action of the output converter. The relation between the DC link voltages vpn (t) & vnn (t) and the output voltages {u, v, w} can be shown to be: 







  Su Su   vu (t)       vpn (t)      vv (t)  =  Sv Sv           vnn (t) vw (t) Sw Sw

   

(7.10)

Comparing the direct and indirect conversion, it is clear (Eqns. 7.4, 7.9 and 7.10) that both are related. 





 vu (t)   Sau        vv (t)  =  Sav       vw (t) Saw   Su   =  Sv   Sw





Sbu Scu   va (t)        Sbv Scv   vb (t)     Sbw Scw vc (t)      Su   va (t)    S1 S3 S5          Sv     vb (t)    S4 S6 S2   Sw vc (t)

vuvw = I × R × vabc

(7.11)

(7.12)

Where I is the Inversion Matrix, and R is the Rectifier Matrix. Here, the input rectifier stage produces the DC link voltage from the input voltages and at the same time modulates the DC link current in to sinusoidal input currents. The DC link is a ‘virtual’ one in case of Direct Matrix Converter.

112

Control and Real-Time Simulation of Matrix Converters

7.4

Modulation of Matrix Converters

Modulation of the Matrix Converter can be done in several ways. There are classical methods like the Venturini method [9] and modern control techniques such as Space Vector Modulation [8]. Space vector Modulation method is described here. There is an inherent limitation to the voltage conversion ratio in the Matrix converter in the linear modulation range. With space phasor modulation the maximum amplitude of the output line voltages that we can synthesize is limited to 0.866 times the input line peak [9]. 7.4.1

Indirect Converter Modulation

Indirect Converter is a cascade connection of rectifier and inverter. Here, modulation can be done independently. The input converter is modulated based on the Current Space Vector and output converter is modulated based on Voltage Space Vector. Input Converter Modulation

In the input converter, there are 6 bidirectional switches. Fig. 7.3 shows the current phasors obtained for each switching combination. For each sector one switch is held ON during the sector, while the return phases are modulated. For example, in sector 1, the switch S1 is kept ON, while switches S6 and S2 are modulated. If the two switches connected to the same phase are closed, there is no current in that particular phase. Such switch combinations are the zero states of the converter. The switch states S1S4, S3S6, and S5S2 are the 3 zero states in this converter. The modulation index is kept at 1. For achieving a i dc 1

a 

3

p

2, 3

5

3, 4

III

II

vdc

b

I

IV

c 4

6

1, 2

4, 5

2 n

VI

V

6, 1

5, 6

Figure 7.3: Input Converter and the Current Space Phasors unity input power factor, the reference current space phasor should be in phase with the input voltage phasor. In each sector, one switch is kept ON, and the

7.4 Modulation of Matrix Converters

113

other two are modulated. The duty ratio of each combination of switch-states can be calculated from Fig. 7.4. These are given in Eqn. 7.13. The α and β directions show the active vectors, which arise from the switch combinations. In sector 1 (Fig.7.4), the switch combination S1S6 and S1S2 corresponds to the active vectors in α and β directions respectively. The switch combination S1S4 corresponds to the zero vector.

S1 S2

6

I

2

a

b

4

5

6

c

0

i(t)

iβ

3

θCSC iα

S1 S6 Figure 7.4: Sector Definition

dα = sin

π

− θCSC

3 dβ = sin (θCSC ) d0 = 1 − d α − d β

 (7.13)

Here, the modulation index is assumed to be 1. Sequencing the active and zero states can be done in several ways considering number of switchings in one switching cycle. The general approach is to get the raw switching signals first. These indicate the time duration for each active or zero vector. Then the sector information is used to produce the actual switch control signals from the raw switching signals. Once the sequencing of active vector durations is determined, the modulation can be implemented by a carrier based approach. A ramp or triangular carrier is compared against the modulating functions to get the raw switch signals. Fig. 7.5 shows the generation of raw switch signals. Eqns. 7.14- 7.17 give the modulating functions. Note that, the modulating function for odd sectors is m1 and for even sectors is m3 . In the figure, Ts is the sequence period. The switching frequency is 2T1 s . It is also possible to have a ramp based sequencing in which the zero states are not divided into two in one sequence period.

114

Control and Real-Time Simulation of Matrix Converters Carrier

1

m2 m1 /m3 m0

T0

Tα

Tβ

2T0

Tβ

Tα

T0

2 Ts

S0

Sα Sβ

Figure 7.5: Modulation Functions and Raw Switch Signals

m0 = m1 m2 m3

= = = = = = =

1 − d α − dβ 2 (0.5 − 0.5mSin(60o − θCSC ) − 0.5mSin(θCSC )) (m0 + dα ) (0.5 + 0.5mSin(60o − θCSC ) − 0.5mSin(θCSC )) (m1 + dβ ) (0.5 + 0.5mSin(60o − θCSC ) + 0.5mSin(θCSC )) m0 + d β (0.5 − 0.5mSin(60o − θCSC ) + 0.5mSin(θCSC ))

(7.14) (7.15) (7.16) (7.17)

where m is the modulation index. From Figs. 7.3 and 7.5 we can obtain the relation between the raw switch signals and the actual switch control signals.(See Table 7.1). The actual switch control signals derived from Table 7.1 are given in Eqns. 7.18.

7.4 Modulation of Matrix Converters

115

Table 7.1: Switch Signals Sector

Sr.1

Sr.2

Sr.3

Sr.4

Sr.5

Sr.6

S0

S1S4

S2S5

S3S6

S4S1

S5S2

S6S3

Sα

S1S6

S2S3

S3S2

S4S5

S5S4

S6S1

Sβ

S1S2

S2S1

S3S4

S4S3

S5S6

S6S5

S1 S2 S3 S4 S5 S6

= = = = = =

Sr.1 + S0 .Sr.4 + Sα .Sr.6 + Sβ .Sr.2 Sr.2 + S0 .Sr.5 + Sα .Sr.3 + Sβ .Sr.1 Sr.3 + S0 .Sr.6 + Sα .Sr.2 + Sβ .Sr.4 Sr.4 + S0 .Sr.1 + Sα .Sr.5 + Sβ .Sr.3 Sr.5 + S0 .Sr.2 + Sα .Sr.4 + Sβ .Sr.6 Sr.6 + S0 .Sr.3 + Sα .Sr.1 + Sβ .Sr.5

(7.18)

Output Converter Modulation

Output converter is a normal Voltage Source Inverter (VSI). Hence the familiar modulation schemes can be applied to get the required output waveforms. Here, the conventional space vector PWM scheme is explained. The modulation functions for the conventional space vector PWM are the same as those described for input modulation. The VSI configuration and the voltage space phasors that are derived from the switch states are shown in Fig. 7.6. The duty ratios are given in Eqn. 7.19- 7.21.

001 c

101 V

Vβ 111 000

011

*

Sector 1 Vdc a

θ VSI

Vα

1 0

a

b

100 VSI

010 b

110 Figure 7.6: VSI and Space vectors

c

116

Control and Real-Time Simulation of Matrix Converters

dα = m × sin dβ d0

π

− θV SI

3 = m × sin (θV SI ) = 1 − d α − dβ



(7.19) (7.20) (7.21)

where m is the modulation index. For a doublesided modulation the modulation functions are defined similar to the input converters (Eqns. 7.14 - 7.17). The generation of raw switching signals and the switch control signals are done in a similar manner. Fig. 7.7 shows how this is done for the sector 1. The switch signals are generated by a logic combination of the sector information and raw signals S0 , Sα and Sβ (Eqns. 7.22).

Carrier

1

m2 m1 /m3 m0

T0

Tα

Tβ

2T0

Tβ

Tα

T0

2 Ts

S0

Sα Sβ

000

100

110

111

110

100

000

Su Sv

Sw

Figure 7.7: Switch Signal Generation for VSI : Sector 1

7.4 Modulation of Matrix Converters

117

Su = S0 + Sα (Sr.1 + Sr.6) + Sβ (Sr.1 + Sr.2 + Sr.5 + Sr.6) Sv = S0 + Sα (Sr.2 + Sr.3) + Sβ (Sr.1 + Sr.2 + Sr.3 + Sr.4) Sw = S0 + Sα (Sr.4 + Sr.5) + Sβ (Sr.3 + Sr.4 + Sr.5 + Sr.6) (7.22) 7.4.2

Direct Converter Modulation

Direct Converter Modulation can be achieved in a simple method, derived from the Indirect Converter Control. First, modulation is carried out as if the converter is an indirect one. The switch control signals for the Direct Converter are then derived based on the relation between the two (Eqn. 7.11). This simpler approach is known as Indirect Modulation. The switch control signals for direct matrix converter from that of Indirect Converter are: Sau Sav Saw Sbu Sbv Sbw Scu Scv Scw

= = = = = = = = =

S1 .Su + S4 .Su S1 .Sv + S4 .Sv S1 .Sw + S4 .Sw S3 .Su + S4 .Su S3 .Sv + S4 .Sv S3 .Sw + S4 .Sw S5 .Su + S4 .Su S5 .Sv + S4 .Sv S5 .Sw + S4 .Sw

These can be realized with a logic circuit.

(7.23)

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Control and Real-Time Simulation of Matrix Converters

7.5

Implementation of Modulators in FPGA

The modulation methods described in the previous sections are implemented in the FPGA controller board. The modulator equations are implemented in digital circuits form. Fig. 7.8 shows the outline of implementation of the input modulator using a block diagram approach using the Quartus II software. For implementing the circuit, the structure shown in Fig. 7.9 is used. Fig. 7.10 shows the implementation of the output modulator. Both the modulators are similar except in the generation of PWM signals and sector defintion. Here, details are given for the output modulator. The input modulator can be implemented in a similar manner, following the description in the previous section.

Figure 7.8: Input Modulator Implementation in FPGA A fixed point scaling is used to represent the different variables in the FPGA program. For example, 1 p.u is represented by a 14 bit number 3F F F . Duty ratios and angles follow this p.u system. For calculating the duty ratios the sine table is stored in a ROM in the FPGA.

7.5 Implementation of Modulators in FPGA

Ref. input signals

119

Ref. Inputs

Sector

Angle Gen.

Identification

Ref. phase m0

d0

Clock

Carrier

Mod.Index

Duty Ratio Calc

Gen./Timing Sync. Circuit

dα dβ

Modulation Functions

PWM

m1 m2

Carrier

Figure 7.9: Structure of Input Modulator

Figure 7.10: Output Modulator Implementation in FPGA 7.5.1

Output Modulator

The major building blocks for the modulator are: • Angle Generation • Sector Identification • Carrier Generation • Modulation Functions Generation

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Control and Real-Time Simulation of Matrix Converters

• PWM generation Sector Identification and Reference Angle Generation

The angle θ, is generated from the reference output frequency by integrating it. The procedure is same as described in Ch. 5. Based on the angle, the sector can be identified. The reference angle for space vector, θV SI is generated from the sector information and A logic circuit for this purpose is designed based on Fig. 7.11.

p.u. angle

1 p.u/

3FFFh 3554h 2AAAh 2000h 1555h AAAh 60o

Sect 1

360

o

Sect 2 Sect 3 Sect 4 Sect 5 Sect 6 θ vsi

Figure 7.11: Reference angle Generation

Carrier Generation

A triangular carrier is required for the calculation of different dwell times (or the ’raw switch signals’). This can be generated as described in Ch. 5.

7.5 Implementation of Modulators in FPGA Generation of Modulation Functions and PWM

Generation of the modulation functions as described in Eqns. 7.17 are implemented by the per-unitized digital equations. The duty ratios dα , dβ and d0 are calculated first from Sine table. Figures 7.12 and 7.13 show how the duty ratios and modulating functions are generated. They are just digital equivalents of the equations presented in the previous sections. Modulation functions thus generated are compared against the carrier as shown in Fig. 7.7 and the raw functions S0 , Sα and Sβ are generated. Fig. 7.14 shows the duty ratios

Figure 7.12: Calculation of Duty Ratios dα and dbeta produced by the output modulator. Generation of PWM signals Su , Sv and Sw is by implementing the simple logic equation given in Eqn. 7.22 with AND, OR gates. Note that this requires the sector information. Fig. 7.15 shows the generated PWM signals for switches S1 and S2 in the input converter. Fig. 7.16 shows the PWM signals for switches Su and Sv . The switching frequency is 5 kHz. Fig. 7.17 shows the switch control signals for switch Sau and Sbu of the Direct Matrix Converter.

121

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Control and Real-Time Simulation of Matrix Converters

Figure 7.13: Calculation of Modulating Functions

Figure 7.14: Duty Ratios dα and dβ

7.6

Modelling of Direct and Indirect Matrix Converters

For a functional simulation, an idealized model can be derived from the Converter equations. In this section idealized models of both Direct and Indirect Converters are presented. Offline and real-time simulation can be done based on these models. Since the Converters doesnot contain any energy storage elements, the equations are simple algebraic equations.

7.6 Modelling of Direct and Indirect Matrix Converters

Figure 7.15: PWM signals for S1 and S2 of Input Converter

Figure 7.16: PWM signals for Su and Sv of Output Converter

123

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Control and Real-Time Simulation of Matrix Converters

Figure 7.17: PWM signals for Sau and Sbu of Direct Converter 7.6.1

Indirect Converter

The input converter model is given in Eqn. 7.24. Fig. 7.18 shows the DC link voltage produced by the input converter. Structure of the output converter modulator is shown in Fig. 7.19. The output converter model is based on Eqn. 7.25. VDC (t) ia (t) ib (t) ic (t)

= = = =

Va (S1 − S4 ) + Vb (S3 − S6 ) + Vc (S5 − S2 ) iDC (t) (S1 − S4 ) iDC (t) (S3 − S6 ) iDC (t) (S5 − S2 )

Vuv (t) = VDC (t) (Su − Sv ) Vvw (t) = VDC (t) (Sv − Sw ) Vwu (t) = VDC (t) (Sw − Su ) Vuv (t) − Vwu (t) Vun (t) = 3 Vvw (t) − Vuv (t) Vvn (t) = 3 Vwu (t) − Vvw (t) Vwn (t) = 3 iDC (t) = iu (t).Su + iv (t).Sv + iw (t).Sw

(7.24)

(7.25)

7.6 Modelling of Direct and Indirect Matrix Converters

125

The overall scheme of simulation for the indirect converter is shown in Fig. 7.20. Fig. 7.21 shows the output line-line voltage and Fig. 7.22 shows the output phase-neutral voltage.

Figure 7.18: DC link voltage : Indirect Matrix Converter

Ref. Out Freq.

Ref. Angle Gen

Sector Number

Sector Identification

Ref. Phase

Clock

Carrier Gen./Timing Sync. Circuit Mod.Index

m0

d0 Duty Ratio Calc

dα dβ

Modulation Functions

m1 m2

Carrier

Figure 7.19: Structure of Output Modulator

PWM

126

Control and Real-Time Simulation of Matrix Converters

Figure 7.20: Indirect Converter Model

Figure 7.21: Output Line Voltage: Indirect Matrix Converter 7.6.2

Direct Converter

The Direct Converter model is given in Eqn. 7.4. The overall structure of the Direct converter is shown in Fig. 7.23. Fig. 7.24 shows the output line-line voltage and Fig. 7.25 shows the output phase-neutral voltage.

7.7 Real-Time Simulation

Figure 7.22: Output Phase Voltage : Indirect Matrix Converter

Figure 7.23: Direct Matrix Converter Model

7.7

Real-Time Simulation

The Matrix Converter modulators are implemented in FPGA as described in the previous section. The Converters and the motor are also be modelled and implemented in the FPGA. Induction Motor model is implemented as explained in chapter ?. It then forms a real-time simulation of the converter and its controller. The advantage of such simulation is that it gives results

127

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Control and Real-Time Simulation of Matrix Converters

Figure 7.24: Line-Line Voltage : Direct Matrix Converter

Figure 7.25: Phase Voltage: Direct Matrix Converter

7.7 Real-Time Simulation

in real time. One can observe the nature and form of the output variables in a an Oscilloscope. For implementing the converters, the models described in Eqn. 7.24, 7.25 and 7.4 are used. These equations can be implemented in digital form using adders and subtracters. To illustrate how the converter equations are implemented in FPGA, the input converter model is shown in Fig. 7.26. While implementing the converter models, the per-unit system adopted is same as that of modulators. Sinusoidal sources are also generated in the FPGA with sine tables. Fig. 7.27 shows the DC link voltage of the indirect converter simulated in real-time in the FPGA. Fig. 7.28 shows the output phase voltage. These waveforms exactly match that of the offline simulation results presented in section 7.6. Fig. 7.29 shows the direct online starting characteristics of an

Figure 7.26: Input Converter Model in FPGA Induction Motor driven by the Direct Matrix Converter. Here, the converter, modulator and the machine are modelled together in the FPGA. This shows the capability of the FPGA platform to simulate in real-time, even a complex drive system as a Matrix Converter Drive.

129

130

Control and Real-Time Simulation of Matrix Converters

Figure 7.27: DC link voltage : Real-time simulation

Figure 7.28: Output Phase Voltage : Real-time simulation

7.8 Conclusion

Figure 7.29: DOL starting of Induction Motor fed by Matrix Converter : Realtime simulation

7.8

Conclusion

The principle of Direct and Indirect Matrix Converters has been explained. Modulation of Matrix Converters is shown and implemented in FPGA based controller. Both Real-time and offline simulation results are presented.

131

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Control and Real-Time Simulation of Matrix Converters

Bibliography [1] Steven C. Chapra, Raymond P. Canale, Numerical Methods for Engineers, 2nd edition, 1990. [2] Werner Leonhard, Control Of Electrical Drives, 3rd edition. [3] R.Krishnan, Electric Motor Drives Modeling, Analysis, and Control, Pearson Education, First Indian Reprint, 2003. [4] S. Venugopal and G. Narayanan ”Design of FPGA Based Digital Platform for Control of Power Electronics Systems”, Proceedings of 2nd National Power Electronics Conference, December 22-24, 2005, pp. 409-413. [5] V.T Ranganathan, “Course Notes on Electric Drives,”Department of Electrical Engg., IISc, Bangalore. [6] “Laboratory Manual for Digital Control of Power Converters,” Power Electronics Group, Department of Electrical Engg., Indian Institute of Science, Bangalore. [7] Patrick W, Wheeler,Jon C. Clare, Lee Empringham, and Alejandro Weinstein,“Matrix Converters: A Technology Review,” IEEE Trans. On IE, vol.49, No.2, pp. 276-287 [8] L. Huber, D. Borojevic,“Space Vector Modulated Three-Phase to Three Phase Matrix Converter with Input Power Factor Correction,” IEEE Trans. Ind.Appl., Vol. 31, No. 6, pp.1234-1246, Nov/Dec 1995. [9] A. Alesina, M.G.B Venturini, “Analysis and Design of Optimum Amplitude Nine-Switch Direct AC-AC Converters,” IEEE Trans. On PE, Vol.4, pp. 101-112, Jan. 1989. [10] Mohan Undeland Robbins, Power Electronics Converters, Application, Design, Third Edition, John Wiley and Sons. [11] Muhammad H. Rashid, Power Electronics Handbook, Academic Press. [12] V. Ramanarayanan, Course Material on Switched Mode Power Conversion, 2006.