Analog And Digital Vlsi Circuit Design Assignment 3.docx

Due date: 08.04.2019 Analog and Digital VLSI Circuit Design Assignment 3 This assignment pertains to circuit simulation and analysis using SPICE simulator. For this, you can use NI Multisim/LTSpice or any SPICE simulator of your choice. You have to simulate a) an inverter b) 4input NAND gate. a) INVERTER If you are using Multisim, you can use PMOS with component name BST100 and NMOS with component name 2N7000. Change the length to 1µm for both NMOS and PMOS transistors. Set PMOS width as 4µm and NMOS width as 2µm. Set VTO= 0.7V (NMOS) and VTO=-0.7V (PMOS). For changing the values, double click your transistor, a dialog box will open, where you will see a button ‘Edit Model’ in the bottom right corner; click on that button and you will be able to set the desired values. Save these and come back to your circuit. Complete the connections as shown in the figure 1 below. At the input, connect a PULSE VOLTAGE which can be found in the Place Source library. Set the values of input source as shown in figure 2. Name the input and output nets as Vin and Vout respectively.

Figure 1

Save your design and click on the Simulate tab. You will see Analyses and Simulation link in the drop down menu. When you click it, another window opens. Select transient and set the values as shown in figure 3.

Figure 2

Go to the output tab in the same window, Select Vin and Vout for Analyses. Click the Save button. Run your simulation. Another window ‘Grapher View’ will open and it will display the transient plot of both Vin and Vout. You can Zoom in/out by using different buttons provided in the panel. In this window, you have to calculate the propagation delay for rising and falling edges.

Figure 3

Q1. Calculate the propagation delay for this inverter. Q2. It is generally accepted that the W/L ratio of a PMOS should be about 1.6x to 4x larger than

that of the NMOS. What are the reasons for this? Q3. Complete the following table. 1.6x, 2x, 3x, 4x are the ratio of PMOS width to NMOS width.

1.6x

2x

tpHL (ps) tpLH (ps) Delay (ps) Rise Time, tr (s) Fall Time, tf (s) Comment on the observations recorded in the table. Q4. Propose ways to speed up the delay time.

3x

4x

b) 4-input NAND gate. Simulate a 4-input NAND gate in the similar manner. Set the width of NMOS and PMOS transistors so that i. Both pull-up and pull-down networks have equal current driving capabilities. ii.

The worst case delay for pull-up and pull-down network is equal to that of an inverter with sizes as given below: NMOS width = 2µm and PMOS width = 4µm. Length for all transistors is 1µm.

Analyze the worst- case situation and complete the following table for part i.

(W/L)PMOS: (W/L)NMOS Delay Values tpHL (A,B,C,D) tpHL (A,B,C) tpHL (A,B) tpHL (A) tpLH (A) tpLH (B) tpLH (C) tpLH (D)

2:1

4:1