An Adaptive Sleep Transistor Biasing Scheme For Low Leakage Sram

An Adaptive Sleep Transistor Biasing Scheme for Low Leakage SRAM Afshin Nourivand, Chunyan Wang, and M. Omair Ahmad Department of Electrical and Computer Engineering Concordia University 1455 de Maisonneuve Blvd. West, Montréal Québec, Canada H3G 1M8

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Outline Problem addressed: leakage currents in SRAM cells non-uniform device characteristics static noise margin reduction Approach to reducing the leakage currents using sleep transistor adaptive virtual ground voltage

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Leakage currents in SRAM cells BL

BL 0

WL

subthreshold current 1 MaL

MpL 1 Q

MpR 0 Q

MnL

MnR

1 MaR

reverse current gate current

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Leakage Current Reduction (1) by means of a sleep transistor

BL

BL 0

1 MaL

WL

MpL 1 Q

MpR 0 Q

MnL

MnR

1

V sourse : Virtual ground higher V sourse lower leakage

MaR

Static noise margin?

Vsource

Sleep#

Msl

A. Agarwal, H. Li, and K. Roy, A single-Vt low-leakage gated-ground cache for deep submicron, IEEE Journal of Solid State Circuits, vol. 38, no. 2, pp. 319 328, Feb. 2003.

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Leakage Current Reduction (2) by means of a sleep transistor

leakage current vs. SMN “optimal” virtual ground voltage non-uniform cell characteristics non-uniform optimal virtual ground voltage individual calibration in an automatic manner 5 of 8

Leakage Current Reduction by means of an adaptive virtual ground voltage BL

BL 0

1 MaL

WL

MpL 1 Q

MpR 0 Q

MnL

MnR

V sourse : Virtual ground adjusted to its maximum by means of a feedback process 1 MaR

Maximum V source of a cell/block adapted to its characteristics

Vsource

Vx

Sleep#

Msl

V y : active when V source reaches its maximum V x : incrementing V source incrementing if V y is not active 6 of 8

Leakage Current Reduction Address 4 cells

Adaptive Reference Voltage Generation

by means of an adaptive virtual ground voltage

BIST SRAM Block

Data Test

Pass/Fail

Source Line

Cal.

Controller From Inc/Dec Decoder Programmable Vref-opt Voltage Generator 0 Vref

Sleep# + -

P1

Msl

N1 Sleep#_Bias

Dynamic Sleep Transistor Biasing

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Conclusion Low-power in SRAM by leakage power reduction

• based on the sleeping-transistor method • automatic set-up of the virtual ground voltage of a cell/block by a feedback process

• dispersion of device characteristics taken into account

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