Amp Tutorial

Sheet 1 of 17

Amplifier Design Tutorial Introduction This tutorial will set out the design stages required to design a theoretical microwave amplifier with the following specification shown in Table 1: Table 1 Required Specification Parameter Frequency Gain Noise Figure Output VSWR Gain ripple

1.45 – 1.55 12.5 ± 0.2 ≤ 2.0 ≤ 1:1.5 (>13dB) < 1.5

Units GHz dB dB dB

The first stage in the design process is to pick a suitable device. For X-Band and above GaAs MESFETS are used while at lower frequencies Bipolar devices are used if noise is not so critical. Try to pick a device design for the range of frequencies you require. Don’t for example use an X-band device for an LNA at UHF – you are bound to run into stability problems. Also pick a device that will give you plenty of gain margin to allow for noise mismatching etc. For this design an Agilent AT41435 Bipolar transistor has been used. This device has > 14dB of gain at 2GHz with an associated noise figure of <1.7dB. To double-check the gain available we can use a simple ‘rule-of-thumb’ estimate by evaluating |S21|/|S12|. At 1.5GHz this will be 4.63/0.063 = 73.5 or 10*LOG(73.5) = 18.6dB We should easily meet the specification for overall gain and allow for significant output mismatch to allow for gain equalisation and minimum noise. This estimation needs to be checked against the stability factor K of the device as this effects the gain and gives an indication to whether the device is likely to oscillate or not. The device at 1.5GHz is unconditionally stable with a K of >1. The ADS simulation shown in Figure 1 has been setup to calculate K factor and plot minimum noise figure.

Sheet 2 of 17

S-PARAMETERS S_Param SP1 Start=1.0 GHz Stop=2.0 GHz Step= CalcNoise=yes

sp_hp_AT-41435_1_19921201 SNP1 Bias="Bjt: Vce=8V Ic=10mA" Frequency="{0.10 - 6.00} GHz" Noise Frequency="{0.10 - 4.00} GHz"

Term Term2 Num=2 Z=50 Ohm

Term Term1 Num=1 Z=50 Ohm

StabFact

StabFact StabFact1 StabFact1=stab_fact(S)

Figure 1 ADS simulation to calculate K and minimum noise figure. The resistorcapacitor combination connected between the gate and source are to ensure that the device is unconditionally stable at 1.5GHz. 2.0

m1 freq=1.526GHz nf(2)=1.589

1.8

nf(2)

m1

1.6

1.4

1.2 1.0

1.2

1.4

1.6

1.8

2.0

freq, GHz freq

StabFact1 1.000GHz 1.053GHz 1.105GHz 1.158GHz 1.211GHz 1.263GHz 1.316GHz 1.368GHz 1.421GHz 1.474GHz 1.526GHz 1.579GHz 1.632GHz 1.684GHz 1.737GHz 1.789GHz 1.842GHz 1.895GHz 1.947GHz

0.944 0.950 0.958 0.968 0.980 0.995 1.012 1.032 1.056 1.083 1.097 1.097 1.098 1.100 1.104 1.110 1.116 1.124 1.134

Figure 2 Results from the simulation shown in Figure 1, showing a K factor >= 1 at 1.4GHz and a minimum noise figure of 1.65dB at our highest frequency of 1.6GHz.

Sheet 3 of 17

General Amplifier Design Procedure Now that we have picked our device, stabilised it and checked it’s maximum available gain we can begin the process of designing the LNA. This process consists of the following steps:(1) Evaluate the Rollett’s stability factor to identify the possibility of instabilities depending on source and load matching. (2) Determine Bias conditions and circuit. (3) If a specified gain is required at a single frequency then the gain circles can be plotted on a Smith chart and the associated source match can be read off and the corresponding load match calculated. Careful consideration must be taken to the position of the source match in relation to the stability circles. (4) If a specified noise figure and gain at a frequency is required then the noise circles need to be added to the gain circles from (ii). The source match required will be the intersection of the required gain & noise circles. Again careful consideration must be given to the position of the source match in relation to the stability circles. (5) Once the required source impedance has been chosen the corresponding output match required for best return loss can be calculated. Gain & Noise Parameters Using the S-parameters of the device it is possible to calculate the overall transducer gain which consists of three parts, the gain factor of the input (source) matching network, the active device and the output (load) matching network:Gs =

1 − Γin .Γs

G o = S 21

GL =

2

1 − Γs

2

2

2

1 − Γs

1 − S 22 .ΓL

2

Overall Transducer gain = 10LOG10 (G s .G o .GL ) For the unilateral case where S12 = 0 (and a stable device) the above equations can be simplified to the following : Gs =

1 1 − S11

G o = S 21 GL =

2

2

1 1 − S 22

2

Sheet 4 of 17

For rough estimate of the maximum gain available we can assume that S12 = 0 therefore at 1.5GHz (Assuming a bias of 8V @ 10mA) the estimated gain is:Gs =

1 1 − S 11

1

=

2

2

= 1.17 = 0.68dB

2

1 - 0.38 2

G o = S 21 = 4.63 = 21.43 = 13.31dB GL =

1 1 − S 22

=

2

1 1 - 0.48

2

= 1.29 = 1.14dB

Total available gain = 0.68 + 13.31 + 1.14 = 15.13dB Constant Gain circles D 2 = S 22

2

−∆

2

C 2 = S 22 − ∆S 11 *

Gain = G =

Gain desired (absolute ie not in dB) S 21

Location of gain circle ro =

2

G.C 2 * 1 + D 2 .G 2

Radius of gain circle p o =

1 - 2K S 12 .S 21 .G + S 12 .S 21 .G 2 1 + D 2 .G

Note the 0dB gain circle will always pass through the centre of the Smith chart.

Sheet 5 of 17

Constant Noise circles Formula for calculation of noise circles:N=

F - Fmin 1 + Γopt 4R N Zo

Where F

2

⎛ NFdB ⎞ ⎜ ⎟ 10 ⎠

= required noise figure (noise factor = 10 ⎝

Fmin = Optimum noise figure (noise factor = 10

)

⎛ NFmin dB ⎞ ⎜ ⎟ 10 ⎝ ⎠

)

R N = Equivalent noise resistance of transistor Γopt = Reflection coefficien t to achieve optimum noise

Centre of noise figure circle =

Γopt N+1

and the radius of the noise figure circle is =

(

N N + 1 - Γopt

2

)

N +1

The values of Fmin, RN and Γopt are given in the manufacturer’s data sheet. However remember that that the parallel feedback resistor will now have modified the device noise parameters. Calculating these circles by hand is luckily not required these days, as this can be performed using the CAD simulator but before we progress to gain & noise we need to check on the stability of the device. Refer to the stability tutorial for a discussion of stability circles etc.

Sheet 6 of 17

Specifically we need to find the no-go matching zones that may cause the circuit to oscillate if we place these matches to the device. Again this is best performed using the CAD – the ADS simulation shown in Figure 3 has the basic FET device with stability circle simulation boxes.

S-PARAMETERS S_Param SP1 Start=1.0 GHz Stop=2.0 GHz Step= CalcNoise=yes

sp_hp_AT-41435_1_19921201 SNP1 Bias="Bjt: Vce=8V Ic=10mA" Frequency="{0.10 - 6.00} GHz" Noise Frequency="{0.10 - 4.00} GHz"

SStabCircle

Term Term1 Num=1 Z=50 Ohm

Term Term2 Num=2 Z=50 Ohm

S_StabCircle S_StabCircle1 S_StabCircle1=s_stab_circle(S,51)

Figure 3 ADS setup to simulate the Agilent AT41435 using a S-parameter simulator and output the input stability circles. The results from the ADS simulation (Figure 3) shows that the device is conditionally stable as the stability circles clip the edge of the smith chart so that there is a possibility of instability, if a match is placed on the device source with an impedance within the area of the smith chart covered by the stability circle (as shown by the shaded area). S_StabCircle1=1.009 / 179.579 freq=1.315789GHz impedance = Z0 * (-0.004 + j0.004)

S_ St ab m1 Cir cle 1

indep(S_StabCircle1) (0.000 to 51.000)

Figure 4 Result of the circuit simulation showing the input stability circles. The stability circles are outside the smith chart so that for any match applied to the device, the device will be unconditionally stable.

Sheet 7 of 17

We can now plot the gain circles and noise circles. The idea is to choose a matching point on the 10dB source and load constant gain circles and ensure the input matching point is either on the 2dB noise circle or within it. To perform the simulation we need to add the gain mismatch and noise mismatch simulator boxes, note too that the noise feature has been switched on in the S-parameter simulator box. The simulation is shown in Figure 5.

S-PARAMETERS S_Param SP1 Start=0.5 GHz Stop=3.5 GHz CalcNoise=yes

Meas SmGamma1 Eqn smg1 match_input=sm_gamma1(S) Meas SmGamma2 Eqn smg2 match_output=sm_gamma2(S)

Term Term1 Num=1 Z=50 Ohm

Term Term2 Num=2 Z=50 Ohm

sp_hp_AT-41435_1_19921201 SNP1 Bias="Bjt: Vce=8V Ic=10mA" Frequency="{0.10 - 6.00} GHz" Noise Frequency="{0.10 - 4.00} GHz"

Meas SmZ1 Eqn smz1 smz_in=sm_z1(S,PortZ1) smz_out=sm_z2(S,PortZ2)

Figure 5 ADS simulation showing the modified S-parameter simulation box set to include noise. The other measurement boxes are: SmGamma1 which, returns the simultaneous-match input-reflection coefficient. SmGamma2 which, returns the simultaneous-match output-reflection coefficient. Sm_z1 which, returns the simultaneous-match input impedance.

Sheet 8 of 17

m1 indep(m1)=4 GAcircles=0.337 / 48.137 gain=12.759112 impedance = Z0 * (1.335 + j0.75

m3 indep(m3)=3 Noise_circles=0.399 / 42.894 ns figure=1.900000 impedance = Z0 * (1.463 + j0.94

Eqn num_NFcircles=4 Eqn NFstep_size=.1

Noise_circles Noise_circleMin GAcircles GAcircleM ax

m3 m1

Set step sizes and number of circles, here.

Eqn Noise_circles=ns_circle(NFmin[m2]+NFstep_size*[0::num_NFcircles],NFmin[m2],Sopt[m2],Rn[m2]/50,51) Eqn Noise_circleMin=ns_circle(NFmin[m2],NFmin[m2],Sopt[m2],Rn[m2]/50,51) Eqn num_GAcircles=6 Eqn GAstep_size=1 Eqn GAcircles=ga_circle(S[m2],max_gain(S[m2])-GAstep_size*[0::num_GAcircles])

indep(GAcircleMax) (0.000 to 51.000) cir_pts (0.000 to 51.000) indep(Noise_circleMin) (0.000 to 51.000)

Eqn GAcircleMax=ga_circle(S[m2],max_gain(S[m2]))

RF Frequency Selector [0::sweep_size(freq)-1]

100 80

m2 indep(m2)=1500000000.000 vs([0::sweep_size(freq)-1],freq)=33.000

60

m2

40 20 0

3.60G

3.40G

3.20G

3.00G 2.80G

2.60G

2.40G

2.20G

2.00G

1.80G

1.60G

1.40G

1.20G

1.00G 800.M

600.M

400.M

freq, Hz

Figure 6 Data display setup to plot gain and noise circles. The slider m2 on the frequency selector can be moved to display the noise and gain circles at other frequencies.

Sheet 9 of 17

m1 indep(m1)=4 GAcircles=0.337 / 48.137 gain=12.759112 impedance = Z0 * (1.335 + j0.755)

m3 indep(m3)=45 Noise_circles=0.252 / -30.384 ns figure=1.900000 impedance = Z0 * (1.490 - j0.406)

Noise_circles Noise_circleMin

m1 m3

GAcircles

GAcircleMax

indep(GAcircleMax) (0.000 to 51.000) cir_pts (0.000 to 51.000) indep(Noise_circleMin) (0.000 to 51.000) Figure 7 The diagram shows a smith chart with constant gain and noise circles plotted. The brown circles show the constant noise circles with the blue dot showing the optimum noise point. The red circle shows the constant maximum available gain and the green circles are the constant gain circles. Marker 1 has been placed on the 12.5dB constant gain circle with the 2.0dB constant noise circle is indicated by marker 3. If we place a load at marker 1 ie an impedance of 1.335+j0.75 to the input of the Bipolar transistor then we should have an amplifier with 12.5dB of gain and a noise figure of <2.0dB. Figure 7 Shows the constant gain and noise circles plotted at 1.5GHz. Marker 1 has been placed on the 12.5dB gain circle and marker 3 has been placed on the 1.9dB noise circle. Referring back to the stability circle plots of Figure 4 we can see that our required matching point is clear of any ‘unstable’ regions. Clearly then the noise figure at our designated matching point should be lower than 1.9dB as it is within the 1.9dB constant noise circle. We can now generate our input matching circuit.

Sheet 10 of 17

The input matching circuit can be drawn onto a smith chart or it can be synthesised using the CAD. Using a program called ‘WinSmith’ the input matching circuit has been generated using ‘ideal’ micro-strip lines defined by electrical length (these electrical lengths then need to be converted to physical lengths depending on the characteristics and dimensions of the microstrip substrate used. Figure 8 Shows the ‘WinSmith’ design of the input matching circuit design to provide a load of 1.335+j0.755 ohms (ie 66.8+j37.8 ohms normalised to 50 ohms) to the base of the AT41435.

Figure 8 ‘WinSmith’ plot of the proposed input matching circuit designed to present a load of 66.8+j37.8 ohms to the input of the AT41435. The line length from the FET gate to the stub is 102 degrees long and the stub has an electrical length of 36 degrees. We can now simulate the circuit with the input matching circuit added to see if we get close to the required gain and noise figure. To do this the ideal transmission lines have been converted into real micro-strip transmission lines (Er=9.9,H=25thou) using ‘LineCalc’. The ADS schematic is shown in Figure 9.

Sheet 11 of 17

S-PARAMETERS

MSub

Term Term1 Num=1 Z=50 Ohm

MSUB MSub1 H=25 mil Er=9.6 Mur=1 Cond=1.0E+50 Hu=1.0e+033 mm T=0 mm TanD=0 Rough=0 mm

S_Param SP1 Start=1.45 GHz Stop=1.55 GHz Step= MLIN CalcNoise=yes TL1 Subst="MSub1" W=0.56 mm L=22.5 mm

Term Term2 Num=2 Z=50 Ohm

MLEF TL2 Subst="MSub1" W=0.56 mm L=7.96 mm sp_hp_AT-41435_1_19921201 SNP1 Bias="Bjt: Vce=8V Ic=10mA" Frequency="{0.10 - 6.00} GHz" Noise Frequency="{0.10 - 4.00} GHz"

Figure 9 ADS schematic of LNA with ‘real’ matching circuit added to the input. 12.6

12.2

m2 freq=1.500GHz dB(S(2,1))=11.887

12.0

m2

dB(S(2,1))

12.4

11.8 11.6 11.4 1.44

1.46

1.48

1.50

1.52

1.54

freq, GHz

m1

2.0

m1 freq=1.550GHz nf(2)=1.975

1.9

nf(2)

1.56

1.8

1.7

1.6 1.44

1.46

1.48

1.50

1.52

1.54

1.56

freq, GHz -7.8

m3 freq=1.501GHz dB(S(2,2))=-8.061 m3

dB(S(2,2))

-7.9 -8.0 -8.1 -8.2 -8.3 1.44

1.46

1.48

1.50

1.52

1.54

1.56

freq, GHz

Figure 10 Resulting simulation from the ADS schematic shown in Figure 9. As we can see the gain and noise figures don’t quite meet the requirements across our band of interest. However we have not added the load matching circuit, which we can now calculate as the device is unconditionally stable.

Sheet 12 of 17

The current design has no matching on the output and as we require a good output return loss we should match to S22* - Note S22 will now have been modified by adding the input matching circuit and will have to design the matching circuit to be the conjugate of S22 modified (This is because S22 is looking into the device and the conjugate will looking towards the matching circuit. In order to improve the gain and noise response we need to provide the RL = ROUT* given by:

R L = R OUT

⎛ S12 .S 21.Γopt * = ⎜ S 22 + ⎜ 1 − S11.Γopt ⎝

freq 1.000GHz 1.100GHz 1.200GHz 1.300GHz 1.400GHz 1.500GHz 1.600GHz 1.700GHz 1.800GHz 1.900GHz 2.000GHz

S(1,1) 0.400 / -152.000 0.396 / -158.400 0.392 / -164.800 0.388 / -171.200 0.384 / -177.600 0.380 / 176.000 0.382 / 174.000 0.384 / 172.000 0.386 / 170.000 0.388 / 168.000 0.390 / 166.000

⎞ ⎟ ⎟ ⎠

*

S(2,1) 6.730 / 85.000 6.310 / 82.200 5.890 / 79.400 5.470 / 76.600 5.050 / 73.800 4.630 / 71.000 4.412 / 68.800 4.194 / 66.600 3.976 / 64.400 3.758 / 62.200 3.540 / 60.000

S(1,2) 0.049 / 56.000 0.052 / 56.600 0.055 / 57.200 0.057 / 57.800 0.060 / 58.400 0.063 / 59.000 0.066 / 58.800 0.070 / 58.600 0.073 / 58.400 0.077 / 58.200 0.080 / 58.000

Calculation is long winded but has been included here for completeness:

S(2,2) 0.510 / -30.000 0.504 / -30.400 0.498 / -30.800 0.492 / -31.200 0.486 / -31.600 0.480 / -32.000 0.476 / -33.000 0.472 / -34.000 0.468 / -35.000 0.464 / -36.000 0.460 / -37.000

Sheet 13 of 17

⎛ S 12 .S 21.Γopt R L = R OUT * = ⎜ S 22 + ⎜ 1 − S 11.Γopt ⎝

⎞ ⎟ ⎟ ⎠

*

Γs = Γopt = 0.337 ∠48 ⎛ 0.063 ∠ 59 * 4.63 ∠ 71 * 0.337 ∠ 48 ⎞ ⎟ R L = R OUT * = ⎜⎜ 0.48 ∠ - 32 + 1 − (0.381∠ 176 * 0.337 ∠ 48 ) ⎟⎠ ⎝ ⎛ 0.098 ∠ 178 ⎞ ⎟ R L = R OUT * = ⎜⎜ 0.48 ∠ - 32 + (0.128∠ 224 ) ⎟⎠ − 1 ⎝

*

*

We need to convert 0.128 ∠224 to cartesian which will be in the 3rd quadrant ie - a − jb - (0.128cos(4 4)) − ( j0.128sin( 44) ) = - 0.092 − j0.089 So the bottom term will be (1 + j0 ) − (- 0.092 - j0.089 ) = 1.092 + j0.089 convert back to polar ⎛ 0.089 ⎞ = r = 1.092 2 + 0.089 2 = 1.095 θ = tan -1 ⎜ ⎟ = 4.67 ⎝ 1.092 ⎠ *

0.098 ∠ 178 ⎞ ⎛ R L = R OUT * = ⎜ 0.48 ∠ - 32 + ⎟ = 1.095∠4.67 ⎠ ⎝

( 0.48∠ - 32 + (0.089∠ 173.3 ))*

Convert 0.48 ∠ - 32 to cartesian will be the 4th sector ie + a - jb ∴ r cosφ + jsinφ = 0.48cos(32 ) - j0.48sin(3 2) = 0.407 - j0.254 Convert 0.089 ∠173.3 to cartesian will be the 2nd sector ie − a + jb ∴ −r cosφ + jsinφ = 0.089cos(1 80 - 173.3) + j0.089sin( 180 - 173.3) = 0.089cos(6 .7) + j0.089sin( 6.7) = - 0.088 + j0.01 So we have R L = (0.407 − j 0.254 ) + ( −0.088 + j 0.01) = 0.32 − j 0.244 Therefore Rout = (0.32 − j 0.244 ) = 0.32 + j 0.244 = 0.402∠37 *

The required output match is similar to the input match set for gain & noise performance. The electrical lengths were found to be line length = 100 deg with a stub of 39 degrees. The ADS simulation of the complete amplifier is shown in Figure 11, with the resulting plots of the simulation shown in Figure 12.

Sheet 14 of 17

S-PARAMETERS

MSub

Term Term1 Num=1 Z=50 Ohm

MSUB MSub1 H=25 mil Er=9.6 Mur=1 Cond=1.0E+50 Hu=1.0e+033 mm T=0 mm TanD=0 Rough=0 mm

S_Param SP1 Start=1.45 GHz Stop=1.55 GHz Step= CalcNoise=yes

MLIN TL1 Subst="MSub1" W=0.56 mm L=21.2 mm

MLEF TL2 Subst="MSub1" W=0.56 mm L=7.6 mm

MLIN TL3 Subst="MSub1" W=0.56 mm L=22 mm

Term Term2 Num=2 Z=50 Ohm

MLEF TL4 Subst="MSub1" sp_hp_AT-41435_1_19921201 W=0.56 mm SNP1 L=8.6 mm Bias="Bjt: Vce=8V Ic=10mA" Frequency="{0.10 - 6.00} GHz" Noise Frequency="{0.10 - 4.00} GHz"

Figure 11 ADS simulation of complete amplifier with real micro-strip input and output matching circuits.

Sheet 15 of 17

13.4

m2 freq=1.500GHz dB(S(2,1))=12.716 m2

dB(S(2,1))

13.2 13.0 12.8 12.6 12.4 12.2 1.44

1.46

1.48

1.50

1.52

1.54

1.56

freq, GHz

m1

1.95

m1 freq=1.550GHz nf(2)=1.924

1.90

nf(2)

1.85 1.80 1.75 1.70 1.65 1.44

1.46

1.48

1.50

1.52

1.54

1.56

freq, GHz

m3 freq=1.501GHz dB(S(2,2))=-34.519

-20

dB(S(2,2))

-25 -30

m3

-35 -40 -45 1.44

1.46

1.48

1.50

1.52

1.54

1.56

freq, GHz

Figure 12 Simulation of the complete amplifier as shown in the schematic of Figure 11. Here we can see that we have a gain of 12.7dB and gain ripple of 1.02dB and associated noise figure of 1.77dB at 1.5GHz (worst-case noise figure is at band-edge at 1.92dB. The output return loss is >20dB at 1.45GHz.

Sheet 16 of 17

Final design To physically realise the design we need to add the RF bias circuits and DC blocks. The RF bias circuits consist of ¼ wave inductive lines connected to a ¼ wave capacitive open-circuit stub (See tutorial on Bias Circuits for more details). The final schematic layout of the amplifier together with the RF bias circuits is shown in Figure 13. As a final check it is a good idea to perform a wide-band analysis of the circuit to ensure that at all frequencies S11 and S22 < 0. The wide-band plots of the circuit are shown in Figure 14.

Collector Bias Base Bias

50-ohm chip resistor L = 22mm(100°) L = 21.2mm (102°)

L = 7.6mm (36°) AT41435

L = 8.6mm (39°)

Figure 13 Final Amplifier schematic layout with RF bias circuits added, together with blocking capacitors.

As can be seen although the pass-band amplifier response is compliant with a pass-band gain ripple of <1.5dB, output return losses and noise figure (at a maximum values of ~ –20 dB & 1.9dB) are also compliant. The wide-band plots show that the return losses are always <0dB and this should ensure a stable amplifier design.

Sheet 17 of 17

0

dB(S(2,2))

-10

-20

m1 freq=1.503GHz dB(S(2,2))=-32.085

m1

-30

-40 0

1

2

3

4

5

6

7

8

9

10

7

8

9

10

freq, GHz 0

m2

dB(S(1,1))

-5

m2 freq=1.503GHz dB(S(1,1))=-2.971

-10

-15

-20 0

1

2

3

4

5

6

freq, GHz Figure 14 Results of S11 and S22 for the amplifier over a broad-band width (0.5 to 10GHz). The output return is very good as we specifically matched the output to give a good-return loss. As the input was mismatched to give a particular gain & noise figure the resulting return loss is poor. If this is deemed a problem, then either a balanced amplifier be used or an isolator added (NOTE in both cases this would add ~ 0.5dB to the noise figure of the amplifier).