Advanced Computer Architecture March06 Rr410408

Set No. 1

Code No: RR410408

IV B.Tech I Semester Supplementary Examinations, March 2006 ADVANCED COMPUTER ARCHITECTURE ( Common to Electronics & Communication Engineering and Electronics & Computer Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. (a) Explain Three level memory hierarchy, of a two-processor system. (b) Explain the concept of virtual memory and explain how virtual to real page address translation is performed. [8+8] 2. (a) Differentiate between Static and Dynamic Pipelines. (b) Compare and contrast Unifunctional and Multifunctional pipelines. (c) Explain the concept of Instructional pipeline.

[5+5+6]

3. (a) Explain the connectivity of Illiac Network with N = 16. (b) Draw a neat 16*16 baseline network and Explain its connectivity between its nodes. [8+8] 4. (a) Discuss the steps involved in M(j,2) sorting algorithm. (b) Describe Bit parallel Associative memory organization with suitable diagram. [8+8] 5. (a) Describe the desirable architectural features for a processor to be effective in a multiprocessing system. (b) Explain the architecture of Honeywell 60/66 multiprocessor system.

[8+8]

6. (a) Explain briefly the different methods proposed to solve the cache coherence problem. (b) Explain briefly how multiprocessor operating systems are classified ? [10+6] 7. (a) Explain the VLSI arithmetic module for the multiplication of the sequences of 2 x 2 matrices. (b) Explain the principles of a pipelined VLSI matrix inverter.

[8+8]

8. (a) Give the characteristics of the Cray-1 computer system. (b) Explain with neat diagrams the 4 types of vector instruction in Cray and give example. [8+8] ⋆⋆⋆⋆⋆

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Set No. 2

Code No: RR410408

IV B.Tech I Semester Supplementary Examinations, March 2006 ADVANCED COMPUTER ARCHITECTURE ( Common to Electronics & Communication Engineering and Electronics & Computer Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. (a) Explain Flynn’s computer classification in detail with suitable block diagrams. (b) Differentiate between WORD-Slice processing and bit-slice processing. (c) A Computer system can be characterized by T (C) =< K × K ′ , D × D ′ , W × W ′ > What are these six entities ? [6+6+4] 2. (a) How the vector length effects the processing efficiency ? Explain different enhancement techniques. (b) Describe memory interleaving mechanisms.

[8+8]

3. (a) Explain the various configurations of an SIMD array Processors. (b) List down the similarities and differences between them.

[10+6]

4. (a) Describe O (n log2 n) algorithm used for matrix multiplication. (b) Describe the connection issues of PEs for efficient SIMD processing.

[8+8]

5. (a) With a block diagram explain the working of a multi-bus interconnection network for multiprocessor system. What are its advantages and drawbacks? (b) Explain briefly the following techniques used in bus control algorithms i. Polling. ii. Independent requesting.

[10+6]

6. (a) What is meant by cache coherence? Explain how this problem can be avoided. (b) Derive an expression for processor utilization U, for the multiprocessor system with set-associative caches. [6+10] 7. (a) Compare data driven and dependence driven computing models. (b) Explain the multilevel program abstraction in the event driven data flow computing model. [8+8] 8. Write notes on (a) Characteristics of querying structure. (b) Discrete time markov chains.

[8+8] ⋆⋆⋆⋆⋆

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Set No. 3

Code No: RR410408

IV B.Tech I Semester Supplemetary Examinations, March 2006 ADVANCED COMPUTER ARCHITECTURE ( Common to Electronics & Communication Engineering and Electronics & Computer Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. (a) Distinguish among Data processing, information processing, knowledge processing and Intelligence processing. (b) Compare an contrast Parallel processing at the job level, task level, inter instruction level and intra instruction level. [8+8] 2. (a) Describe the effect of conditional statements on pipeline processes Suggest improvements. (b) Explain how Data Buffering and Busing Structures improves efficiency of pipeline processors. [8+8] 3. (a) What routing function are used by a N-dimensional cube Network? (b) Implement a single stage Cube Network with 8 nodes. (c) Name any two multistage cube networks.

[6+8+2]

4. (a) Describe any two associative searching algorithms. (b) Explain the architecture of STARAN associative processor.

[8+8]

5. (a) What is the principle characteristics of Multiprocessor systems? (b) Compare time-shared bus, crossbar switch and multi port memory interconnection network performances. [4+12] 6. (a) Explain performance tradeoffs in memory organizations. (b) How caches can be associated with shared memory? How this configuration avoids cache coherence. [8+8] 7. (a) Explain the organization of a ring structured data flow computer. (b) Construct and explain the data flow graph for the function z = xn .

[8+8]

8. (a) Explain the functions of bus in C.mmp (b) Describe two stage memory configuration in C.mmp. ⋆⋆⋆⋆⋆

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[8+8]

Set No. 4

Code No: RR410408

IV B.Tech I Semester Supplementary Examinations, March 2006 ADVANCED COMPUTER ARCHITECTURE ( Common to Electronics & Communication Engineering and Electronics & Computer Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. (a) What are the different types of memories that are present in a memory hierarchy? Describe the characteristics of each of these memories. (b) What is meant by interleaving memory addresses? Describe the different ways of implementing interleaving schemes. Illustrate with the help of proper diagrams. What are the relative merits and demerits of these schemes? [8+8] 2. A certain pipeline with four stages S1 , S2 , S3 , and S4 is characterized by the following reservation table.As shown in figue1 [16]

Figure 1: (a) Determine latencies in the forbidden list F and the collision vector C. (b) Determine the minimum constant latency L by checking the forbidden list. (c) Draw the state diagram for this pipeline. (d) Determine the minimal average latency (MAL) and (e) the maximum throughout of this pipeline. 3. (a) Explain the conceptual view of a single stage interconnection network and a switch. (b) Give basic organization of Illiac-IV array processor.Explain the its operation. [8+8] 4. Explain the following terminologies associated with SIMD computers (a) Lock-step Operations. 1 of 2

Set No. 4

Code No: RR410408 (b) Associative Memory. (c) Adjacency search. (d) Bit serial Associative Processor.

[16]

5. (a) Explain a crossbar organization for inter-processor-memory-I/O connection. Also bring out the details of the structure of a crossbar point. (b) Compare the multiprocessors with time shared bus and cross - bar switch. [10+6] 6. (a) Explain software requirements for multiprocessors. (b) What is cache coherence? Describe method to avoid this problem.

[8+8]

7. (a) Discuss in detail about the Manchester data flow computer organization. (b) Explain how an exchange switch network is used in the multiple ring architecture. [8+8] 8. (a) How memory mapping is done in Cyber-205? Explain (b) List various functions of virtual memory in Cyber 205. (c) Describe any two special vector instruction of Cyber 205. ⋆⋆⋆⋆⋆

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[8+8]