Adc Registers

Here are the registers concerned : ADMUX Bits 7,6 (REFS 1,0) are for voltage reference selection. We set them to 1,0 for selecting AVCC as the reference voltage. Bits 5 (ADLAR) left aligns the result. That way, we can read the 8 most significant bits by reading ADCH and ignore the last 2 (stored in ADCL) if needed. Bits 4,3,2,1,0 are the bits to select which of the 8 channels to use as input. ADCSRA Bit 7 (ADCEN) enables ADC Bit 6 (ADSC) starts an ADC conversion if set. Bit 5 (ADATE) enables Auto Triggering of ADC. Bit 4 (ADIF) is the ADC Interrupt Flag. It is set when an ADC conversion is complete. Bit 3 (ADIE) enables the interrupt on ADC Conversion complete. Bits 2,1,0

(ADPS) is the ADC Prescaler Select, for selection of the prescaler.

ADCH and ADCL store the results of the conversion. If ADLAR is enabled the 8 most significant bits are in ADCH and the least 2 significant bits are in ADCL. If ADLAR is disabled the 2 most significant bits are in ADCH and the least 8 significant bits are in ADCL.