A Bit-line Leakage Compensation Scheme For Low-voltage Sram's

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A Bit-Line Leakage Compensation Scheme for Low-Voltage SRAM’s Ken’ichi Agawa, Hiroyuki Hara, Toshinari Takayanagi, and Tadahiro Kuroda System ULSI Engineering Laboratory, Toshiba Corporation 580-1 Horikawa-cho, Saiwai-ku, Kawasaki, 21 2-8520, Japan

Abstract Bit-line leakage current of an SRAM, induced by transistor leakage at low V,,, and dependent on cell data associated with the bit-line, is detected in a pre-charge cycle and compensated for during a read/write cycle. By this scheme, V,* can be lowered to 0.23V,, in a 0.07pm/l .OV CMOS, as it was before, keeping V,, and delay scalability of the high-speed SRAM. Introduction Threshold voltage of a transistor, Vrh, cannot be lowered in an SRAM than in a logic circuit because of three reasons: increased bit-line leakage current, degraded cell-data stability, and increased static power dissipation. Among the reasons, the bit-line leakage problem is becoming crucial. Measured cell current (Ic,,,) and bit-line leakage (Ile,) in the worst case data pattern of an SRAM with 256 rows, fabricated in a 0.15pm CMOS technology, is depicted in Fig.1. Rapid increase in at low V,, degrades operation speed and finally causes operation error. If I,<, should be kept below 0. lI,cll,V,, should be higher than 0.35V, considering f O . 1V fluctuation. As illustrated in Fig. 2, V,, has been about 23% of power supply voltage, V,, in SRAM’s and around 15% in logic circuits in the 0.18pm and 0.15pm high-speed device generations. However, in a 0.07pm technology where V,,)=l.OV, it is predicted that V,, cannot be scaled to 0.23V,,, under the cover of excessive Ilrak,which becomes three times as large as Ice,,in the worst case. Several schemes are proposed to solve the problem [ I j[2j, but not perfectly. A negative word-line scheme [ I ] may suffer from gate-induced drain leakage. A dynamic leakage cut-off scheme [2] may degrade operation speed since additional time is required for applying reverse substrate bias. In this paper, another scheme, namely a bit-line leakage compensation (BLC) scheme, is proposed which does not suffer from these penalties. Bit-Line Leakage Compensation (BLC) Scheme A proposed circuit for the BLC scheme is illustrated in Fig. 3. Bit-line leakage is detected by P2 (and P2B) in a precharge cycle, and the same amount of current is injected to the bit-line for compensation by P4 (and P4B) during a read/write cycle. P2 and P4 are symmetric for current mirror operation. A control signal ‘/cal’ passes and stores the detected current as potential in CAP7 (and CAP7B), and a control signal ‘/camp' enables the current injection. Area penalty caused by the additional circuit is only 3% in a l k x 8b SRAM which is experimentally fabricated. Waveforms of the bit-lines are simulated by SPICE for the 0.07pm technology under 105°C. Figs. 4(a) and (b) show waveforms in the conventional circuit with no leakage in both bit-lines, and 70pA leakage only in ‘BL’, respectively. Due to the leakage, potential difference between the two bit-lines is reduced in Fig. 4(b). On the other hand, in Fig. 4(c) where

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0-7803-6309-4/00/$10.00 0 2000 IEEE

the BLC scheme is employed, the potential difference is kept almost the same with that in Fig. 4(a), in spite of the 70pA leakage. Fig. 4(d) shows waveforms of the control signals. It should be remarked that after completion of the leakage detection, the ‘kal’ signal should be reset so that the compensation as well as equalization of the bit-lines can start immediately for the succeeding readlwrite operation. Even with the additional operation for leakage detection in the pre-charge cycle, write-recovery can be completed with little speed penalty as shown in Fig. 4(c), since P3 assists P1 with the pre-charge operation while ‘komp’ is low. Capacitance associated with CAP7 should be carefully designed, because too small capacitance causes charge sharing and reduces injection current due to coupling noise from the source of P4, whereas too large capacitance increases detection time and hence the pre-charge cycle time.

Experimental Results Intensive simulation was performed to evaluate the effectiveness of the BLC scheme. All the parasitic capacitance and resistance was extracted from a layout and included in the simulation. Simulated delay time in which the potential difference between the two bit-lines reaches lOOmV is plotted in Fig. 5. If the budget of the bit-line delay is OSns, the bit-line leakage should be less than 30pA without the compensation, whereas it can be as large as 320pA with the proposed compensation scheme. This advantage corresponds to 0.1V V,, reduction. It is also found from Fig. 2 that V,, can be scaled to 0.23VD, in the 0.07pm technology as it was before, when the BLC scheme is employed. A test chip depicted in Fig. 6 is designed and fabricated for various V,,’s in the 0.25pm CMOS technology to investigate if any problem may occur that is difficult to be found in the simulation study. No functional problem associated with noise, data stability, and static power dissipation, was found in the measurement. Conclusion Bit-line leakage as much as 320pA can be compensated for by the BLC scheme. By this scheme, V,,, can be lowered to 0.23V,>,>in the 0.07pm/l.OV CMOS as it was in the highspeed SRAM of the previous generations, and SRAM operation speed can be improved by 25% at 0.9V VDD, compared with the case where this scheme is not applied. References [ 11 H. Tanaka et al., “A Precise On-Chip Voltage Generator for a Gigascale DRAM with a Negative Word-Line Scheme,” IEEE JSSC, ~01.34,pp.1084-1090, Aug. 1999. [2] H. Kawaguchi et al., “Dynamic Leakage Cut-off Scheme for Low-Voltage SRAM’s,” Symp. on VLSI Circuits, pp.140-141, June 1998.

2000 Symposium on VLSI Circuits Digest of Technical Papers

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Fig. 6 Microphotograph of SRAM test chip. 2000 Symposium on VLSl Circuits Digest of Technical Papers

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