86db Single Stage Vga

86 dB 1.4 mW 1.8 V 0.07 mm2 single-stage variable gain amplifier in 0.18 lm CMOS Q.-H. Duong and S.-G. Lee

highest dB-linear range ever reported. A noteworthy attribute of (1) is that the numerator and denominator resemble the drain current expression of a CMOS transistor as a function of the body voltage, which hints at the direction of the actual circuit implementation.

A simple single-stage variable gain amplifier that offers 86 dB of gain variation, consumes 1.4 mW, and occupies 0.07 mm2 is introduced and shown to have the largest gain range, lowest power, and smallest chip size ever reported based on 0.18 mm CMOS technology. A new approximated exponential equation is proposed, which offers the largest dB-linear range compared to all previously-reported approximated equations.

Table 1: Summary of approximated exponential equations, reported and proposed Aproximated exponential equation

Obtainable dB-linear range with  0.5 dB error

f (x) ¼ 1 þ (1=1!) x þ (1=2!) x2

12 dB

References Taylor series approximation equation [1] Pseudo-exponential approximation equation [1] Abdelfattah’s approximated equation [2] Duong’s approximated equation [1] Newly proposed approximated equation

f (x) ¼ (1 þ (x=2))=(1  (x=2))  f ðxÞ ¼

ð1 þ ð3x=4ÞÞ=ð1  ðx=4ÞÞ for x > 0 ð1  ðx=4ÞÞ=ð1  ð3x=4ÞÞ for x < 0

f (x) ¼ k þ (1 þ ax)2=k þ (1 þ ax)2

60 40

f (x), dB

20 0 –20 c=0 c = 0.3 c = 0.9 c = 1.0

–40 –60 –80 –2.0

–1.5

–1.0

–0.5

0 x a

0.5

1.0

1.5

2.0

1.5

2.0

80 60 40 20 f (x), dB

Introduction: Variable gain amplifiers (VGAs) are used to accommodate a large dynamic range of signals in given systems for applications like disc drives, hearing aids, medical equipments, telecommunications, etc. [1, 2]. The VGAs require dB-linear gain variation which can easily be implemented using components with exponential I-V characteristics like bipolar transistors. Because of the square-law I-V characteristic, CMOS transistors cannot directly be applied for dB-linear VGAs. Instead, dB-linear performance is achieved by adopting circuits that approximate the exponential equations [1, 2]. Conventional CMOS-based VGAs, which are based on the previously reported approximated equations, provide a limited amount of gain variations such that the number of VGAs must be cascaded to satisfy the required gain range, leading to high power dissipation, large chip area, high noise figure, poor linearity, and high cost. A single-stage VGA with wide dB-linear gain range is an efficient solution to the aforementioned problems. Therefore, to extend the dB-linear range, starting the VGA design based on a good approximated exponential equation is critical.

80

0 –20 –40

d = 0 × 10–3

–60

d = 2 × 10–3 d = 6.5 × 10–3

–80 –2.0

–1.5

–1.0

–0.5

0 x b

0.5

1.0

15 dB

Fig. 1 Plots of (1) for various values of c where a ¼ 1=4, b ¼ 1=2, d ¼ 0, and for various values of d where a ¼ 1=4, b ¼ 1=2 and c ¼ 1

40 dB

a Plots for values of c where a ¼ 1=4, b ¼ 1=2 and d ¼ 0 b Plots for values of d where a ¼ 1=4, b ¼ 1=2 and c ¼ 1



56 dB VDD

p f (x) ¼ p ((b  ax)  c)2 þ d= ((b þ ax)  c)2 þ d

M5

84 dB

M6

VS

Table 1 summarises the reported approximated exponential equations that have been adopted for dB-linear VGA design [1, 2]. In Table 1, the Taylor series approximation, pseudo-exponential approximation, Abdelfattah and Duong equations offer 12, 15, 40 and 56 dB of dB-linear variations with linearity error of less than  0.5 dB, respectively [1, 2]. These equations have been adopted for VGA designs with gain variations limited to 15, 17, 40 and 45 dB with linearity error of less than  0.5 dB in one stage, respectively [1, 2]. This Letter reports a new approximated exponential equation which is given as pffiffiffiffiffiffiffiffiffiffiffiffiffi ð b  ax  cÞ2 þ d ð1Þ f ðxÞ ¼ pffiffiffiffiffiffiffiffiffiffiffiffiffi ð b þ ax  cÞ2 þ d where a, b, c and d are constants. For c ¼ d ¼ 0, (1) is identical to the pseudo-exponential equation [1]. Fig. 1a shows the dB-linear behaviour of (1) as a function of the parameter c where a, b, d are set to 1=4, 1=2, 0, respectively. In Fig. 1a, for c ¼ 1 (solid line), (1) can offer up to 45 dB-linear range with linearity error of less than  0.5 dB. Now, for the given set of parameters a, b, c (1=4, 1=2, 1, respectively), Fig. 1b shows the dB-linear behaviour of (1) as a function of parameter d. As can be seen in Fig. 1b, for d ¼ 6.5  103 (solid line), (1) offers 84 dB-linear range with linearity error of less than  0.5 dB, the

M7 CMFB

+ –

VBIAS – VCTRL/2

M8

Vref VBIAS +VCTRL/2

M1 ID2

VG

M2 ID1 Vin+

Vout–

M9

+ – buffer – +

C

Vout+ M10

M11

M13

M12

Vin –

M3 M4

gain control circuit

M14

ID1

I0

M15

ID2

I0

variable gain amplifier

Fig. 2 Newly proposed VGA

Circuit design: The schematic diagram of the proposed VGA is shown in Fig. 2, which consists of a variable gain amplifier, a gain control circuit, and a buffer. The buffer is used for measurement purposes only. In Fig. 2, the gain control voltage VCTRL is applied as a differential voltage signal. In the gain control circuit in Fig. 2, PMOS transistors M1,2 are the ones that generate the control bias currents for the variable gain amplifier, where the differential control voltage VCTRL is applied to the body terminals of PMOS transistors M1,2. Transistors M10,11,12,13 are long-channel devices to minimise the second-order effects so that the gain of the VGA can be

ELECTRONICS LETTERS 4th January 2007 Vol. 43 No. 1 Authorized licensed use limited to: NATIONAL INSTITUTE OF TECHNOLOGY WARANGAL. Downloaded on October 15, 2008 at 01:15 from IEEE Xplore. Restrictions apply.

expressed as An ¼ gm;M10;11 

!1=2 ðW =LÞM10;11 ðID1 þ I0 Þ

1 ¼ gm;M12;13 ðW =LÞM12;13 ðID2 þ I0 Þ

ð2Þ

where gm,M10,11 and gm,M12,13 are the transconductances of transistors M10,11 and M12,13, W=L the aspect ratio of the corresponding transistors, ID1,D2 the drain currents of M2,1, and I0 the bias current. From device physics, the drain currents ID1,D2 of transistors M2,1, which operate in the saturation region, are given by [3] n ID1;D2 ¼ K VGS  VTHO pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffio2 þg 2jfF j þ jVS  ðVBIAS  VCTRL =2Þj  2jfF j ð3Þ where K ¼ mpCoxW=2L, VGS is the gate-source voltage of M1,2, VTH0 the threshold voltage of M1,2 when the source-body voltage is zero, g the body-effect coefficient, fF the equilibrium electrostatic potential of the semiconductor, VS the source voltage of transistors M1,2, and VBIAS the common-mode bias voltage, respectively. From (2) and (3), for (W=L)M10,11 ¼ (W=L)M12,13 the gain of the proposed VGA can be expressed as pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 11=2 0 0:5 þ ðVCTRL =4ð2jfF j  VS þ VBIAS ÞÞ pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi  C B  pffiffiffiffiffiffiffiffiffiffiffi B  ½ 2jfF j  ðVGS  VTH0 Þ=g= 2ð2jfF j  VS þ VBIAS Þ 2 C C B C B þðI0 =ð2g2 Kð2jfF j  VS þ VBIAS ÞÞÞ C B An ¼ B pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi C C B =ð4ð2jf j  V þ V ÞÞÞ 0:5  ðV CTRL S BIAS F C B pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2 C B  pffiffiffiffiffiffiffiffiffiffiffi @  ½ 2jfF j  ðVGS  VTH0 Þ=g= 2ð2jfF j  VS þ VBIAS Þ A þðI0 =ð2g2 Kð2jfF j  VS þ VBIAS ÞÞÞ pffiffiffiffiffiffiffiffiffiffiffiffiffi

1=2 ð b  ax  cÞ2 þ d ¼ pffiffiffiffiffiffiffiffiffiffiffiffiffi ð4Þ ð b þ ax  cÞ2 þ d where a ¼ 1=4, b ¼ 0.5, x p ¼  (VCTRL=(2jfFj  VS þ VBIAS)), c ¼ p and d¼ [ (2jfFj  (VGS  VTH0)=g]=( (2(2jfFj  VS þ VBIAS)), I0=(2g2K(2jfFj þ VS  VBIAS)), respectively. As can be seen above, (4) is identical to (1); therefore, for the proper values of parameters VS, VBIAS, VG (the gate voltage of M1,2) and I0 to make c ¼ 1 and d ¼ 6.5  103, the VGA in Fig. 2 can offer wide dB-linear gain variation as a function of VCTRL. The procedure for choosing the bias voltages and current is as follows. First, fix VS and choose VBIAS ¼ VS þ njfFj, where n is a constant, then from (4) the gate voltage of 1, and the VG transistors M1,2 can be determined by the condition of c ¼p is determined from the relation VG ¼ VS  jVTH0j  g( (2 þ n)  1) p (2jfFj). Finally, the bias current I0 can be adjusted for 3 VG is set to zero and therefore VS ¼ d ¼ 6.5  10 p . For simplicity, p jVTH0j þ g( (2 þ n)  1) (2jfFj). The VS is set by a reference voltage Vref through a feedback to the gate of transistor M5 as shown in Fig. 2.

Measurement results: The proposed VGA is designed to dissipate 1.4 mW (excluding the buffer) from a 1.8 V supply based on 0.18 mm CMOS technology. Fig. 3 shows the measured gain of the proposed VGA as a function of VBIAS  VCTRL=2. As can be seen in Fig. 3, the proposed VGA shows 86 dB of gain variation over the VBIAS  VCTRL=2 range of 0.2 to 1.8 V, where VBIAS ¼ 1 V. The measured gain variation of 86 dB is the largest amount in a singlestage VGA that has ever been reported in bipolar or CMOS technology. In Fig. 3, the proposed VGA offers 68 dB of dB-linear gain variation with linearity error of less than 1 dB. As shown in Fig. 3, the gain deviates from the linear behaviour at high values of jVCTRLj where the source-body junction of transistors M1 or M2 is forward biased. The measured 3 dB bandwidth, P1 dB, and IIP3 are 23–120 MHz, 52–8 dBm, and 35–1 dBm, respectively. The active area of the VGA excluding the buffer is 0.07 mm2. Conclusion: A new technique is proposed for high performance CMOS-based VGA designs. The design technique described in this work can be extended to improve the performance of other CMOSbased circuits which require the exponential transfer characteristic such as automatic gain control amplifiers, log-domain filters, exponential V-I=I-V=I-I=V-V converters, etc. The proposed VGA is compact and features the largest gain range, lowest power, and smallest chip size ever reported based on 0.18 mm CMOS. Acknowledgment: This work was supported in part by MOST=KOSEF (Intelligent Radio Engineering Center) under the SRC=ERC Program. # The Institution of Engineering and Technology 2007 27 October 2006 Electronics Letters online no: 20073325 doi: 10.1049/el:20073325 Q.-H. Duong and S.-G. Lee (School of Engineering, RFME Laboratory, Information and Communications University, 119-Mujro, Daejeon 305-714, Republic of Korea) E-mail: [email protected] References 1 Duong, Q.-H., et al.: ‘A 95-dB linear low-power variable gain amplifier’, IEEE Trans. Circuits Syst., 2006, 53, (8), pp. 1648–1657 2 Abdelfattah, K.M., and Soliman, A.M.: ‘Variable gain amplifiers based on a new approximation method to realize the exponential function’, IEEE Trans. Circuits Syst. I, 2002, 49, (9), pp. 1348–1354 3 Muller, R.S., and Kamins, T.I.: ‘Device electronics for integrated circuits’ (John Wiley & Sons, New York, 1986), pp. 473–474

40

Av, dB

20

0

–20

–40 VBIAS –60 0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

VBIAS ± VCTRL/2, V

Fig. 3 Measured VGA gain against VBIAS  VCTRL=2, where VBIAS ¼ 1 V

ELECTRONICS LETTERS 4th January 2007 Vol. 43 No. 1 Authorized licensed use limited to: NATIONAL INSTITUTE OF TECHNOLOGY WARANGAL. Downloaded on October 15, 2008 at 01:15 from IEEE Xplore. Restrictions apply.